Digital Logic & Computer Design CS Professor Dan Moldovan Spring 2010
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1 Digital Logic & Computer Design CS 434 Professor Dan Moldovan Spring 2 Copyright 27 Elsevier 5-<> Chapter 5 :: Digital Building Blocks Digital Design and Computer Architecture David Money Harris and Sarah L. Harris Copyright 27 Elsevier 5-<2>
2 Chapter 5 :: Topics Introduction Arithmetic Circuits umber Systems Sequential Building Blocks Memory Arrays Logic Arrays Copyright 27 Elsevier 5-<3> Introduction Digital building blocks: Gates, multiplexers, decoders, registers, arithmetic circuits, counters, memory arrays, logic arrays Building blocks demonstrate hierarchy, modularity, and regularity: Hierarchy of simpler components Well-defined interfaces and functions Regular structure easily extended to different sizes Will use many of these building blocks to build a microprocessor in Chapter 7 Copyright 27 Elsevier 5-<4> 2
3 -Bit Adders Half Adder Full Adder A B A B C out + C out + C in S S A B S = C out = C out S C in A B C out S S = C out = Copyright 27 Elsevier 5-<5> -Bit Adders Half Adder Full Adder A B A B C out + C out + C in S S A B S = C out = C out S C in A B C out S S = C out = Copyright 27 Elsevier 5-<6> 3
4 -Bit Adders Half Adder Full Adder A B A B C out + C out + C in S S A B C out S = A B C out = AB S C in A B C out S S = A B C in C out = AB + AC in + BC in Copyright 27 Elsevier 5-<7> Multibit Adder, also called CPA Several types of carry propagate adders (CPAs) are: Ripple-carry adders (slow) Carry-lookahead adders (fast) Prefix adders (faster) Carry-lookahead and prefix adders are faster for large adders but require more hardware. Symbol A B C out + S C in Copyright 27 Elsevier 5-<8> 4
5 Ripple-Carry Adder Chain -bit adders together Carry ripples through entire chain Disadvantage: slow A 3 B 3 A 3 B 3 A B A B C out + C + 3 C 29 C + C + C in S 3 S 3 S S Copyright 27 Elsevier 5-<9> Ripple-Carry Adder Delay The delay of an -bit ripple-carry adder is: t ripple = t FA where t FA is the delay of a full adder Copyright 27 Elsevier 5-<> 5
6 Carry-Lookahead Adder Compute carry out (C out ) for k-bit blocks using generate and propagate signals Some definitions: A column (bit i) produces a carry out by either generating a carry out or propagating a carry in to the carry out. Generate (G i ) and propagate (P i ) signals for each column: A column will generate a carry out if A i AD B i are both. G i = A i B i A column will propagate a carry in to the carry out if A i OR B i is. P i = A i + B i The carry out of a column (C i ) is: C i = A i B i + (A i + B i )C i- = G i + P i C i- Copyright 27 Elsevier 5-<> Carry-Lookahead Addition Step : compute generate (G) and propagate (P) signals for columns (single bits) Step 2: compute G and P for k-bit blocks Step 3: C in propagates through each k-bit propagate/generate block Copyright 27 Elsevier 5-<2> 6
7 Carry-Lookahead Adder For example, we can calculate generate and propagate signals for a 4-bit block (G 3: and P 3: ) : A 4-bit block will generate a carry out if column 3 generates a carry (G 3 ) or if column 3 propagates a carry (P 3 ) that was generated or propagated in a previous column as described by the following equation: G 3: = G 3 + P 3 (G 2 + P 2 (G + P G ) A 4-bit block will propagate a carry in to the carry out if all of the columns propagate the carry: P 3: = P 3 P 2 P P The carry out of the 4-bit block (C i ) is: C i = G i:j + P i:j C j- Copyright 27 Elsevier 5-<3> 32-bit CLA with 4-bit blocks A 3:28 B 3:28 A 27:24 B 27:24 B 7:4 A 7:4 B 3: A 3: C out 4-bit CLA Block C 27 4-bit CLA C 23 Block C 7 4-bit CLA Block C 3 4-bit CLA Block C in S 3:28 S 27:24 S 7:4 S 3: B 3 A 3 C 2 + B 2 A 2 C + B A C + B + A C in S 3 S 2 S S G 3: G 3 P 3 G 2 P 2 G P G C out C in P 3: P 3 P 2 P P Copyright 27 Elsevier 5-<4> 7
8 Carry-Lookahead Adder Delay Delay of an -bit carry-lookahead adder with k-bit blocks: t CLA = t pg + t pg_block + (/k )t AD_OR + kt FA where t pg : delay of the column generate and propagate gates t pg_block : delay of the block generate and propagate gates t AD_OR : delay from C in to C out of the final AD/OR gate in the k-bit CLA block An -bit carry-lookahead adder is generally much faster than a ripple-carry adder for > 6 Copyright 27 Elsevier 5-<5> Prefix Adder Computes the carry in (C i- ) for each of the columns as fast as possible and then computes the sum: S i = (A i B i ) C i Computes G and P for -bit, then 2-bit blocks, then 4-bit blocks, then 8-bit blocks, etc. until the carry in (generate signal) is known for each column Has log 2 stages Copyright 27 Elsevier 5-<6> 8
9 Prefix Adder A carry in is produced by being either generated in a column or propagated from a previous column. Define column - to hold C in, so G - = C in, P - = Then, the carry in to column i = the carry out of column i-: C i- = G i-:- G i-:- is the generate signal spanning columns i- to -. There will be a carry out of column i- (C i- ) if the block spanning columns i- through - generates a carry. Thus, we can rewrite the sum equation as: S i = (A i B i ) G i-:- Goal: Quickly compute G :-, G :-, G 2:-, G 3:-, G 4:-, G 5:-, (These are called the prefixes) Copyright 27 Elsevier 5-<7> Prefix Adder The generate and propagate signals for a block spanning bits i:j are: G i:j = G i:k + P i:k G k-:j P i:j = P i:k P k-:j In words, these prefixes describe that: A block will generate a carry if the upper part (i:k) generates a carry or if the upper part propagates a carry generated in the lower part (k- :j) A block will propagate a carry if both the upper and lower parts propagate the carry. Copyright 27 Elsevier 5-<8> 9
10 Prefix Adder Schematic :3 2: :9 8:7 6:5 4:3 2: :- 4: 3: :7 9:7 6:3 5:3 2:- :- 4:7 3:7 2:7 :7 6:- 5:- 4:- 3:- 4:- 3:- 2:- :- :- 9:- 8:- 7: Legend i i:j i B i A i P i:k P k-:j G i:k G k-:j B i G i-:- A i P i:i G i:i Copyright 27 Elsevier P i:j G i:j 5-<9> S i Prefix Adder Delay The delay of an -bit prefix adder is: t PA = t pg + log 2 (t pg_prefix ) + t XOR where t pg is the delay of the column generate and propagate gates (AD or OR gate) t pg_prefix is the delay of the black prefix cell (AD-OR gate) Copyright 27 Elsevier 5-<2>
11 Adder Delay Comparisons Compare the delay of 32-bit ripple-carry, carry-lookahead, and prefix adders. The carry-lookahead adder has 4-bit blocks. Assume that each two-input gate delay is ps and the full adder delay is 3 ps. Copyright 27 Elsevier 5-<2> Adder Delay Comparisons Compare the delay of 32-bit ripple-carry, carry-lookahead, and prefix adders. The carry-lookahead adder has 4-bit blocks. Assume that each two-input gate delay is ps and the full adder delay is 3 ps. t ripple t CLA = t FA = 32(3 ps) = 9.6 ns = t pg + t pg_block + (/k )t AD_OR + kt FA = [ (7)2 + 4(3)] ps = 3.3 ns t PA = t pg + log 2 (t pg_prefix ) + t XOR = [ + log 2 32(2) + ] ps =.2 ns Copyright 27 Elsevier 5-<22>
12 Subtracter Symbol A B - Y Implementation A B + Y Copyright 27 Elsevier 5-<23> Comparator: Equality Symbol Implementation A 3 B 3 A 4 = B 4 A 2 B 2 A Equal Equal B A B Copyright 27 Elsevier 5-<24> 2
13 Comparator: Less Than For unsigned numbers A B [-] - A < B Copyright 27 Elsevier 5-<25> Arithmetic Logic Unit (ALU) A ALU Y B 3 F F 2: Function A & B A B A + B not used A & ~B A ~B A - B SLT Copyright 27 Elsevier 5-<26> 3
14 ALU Design C out Zero Extend 3 A + [-] S 2 B Y 2 F 2 F : F 2: Function A & B A B A + B not used A & ~B A ~B A - B SLT Copyright 27 Elsevier 5-<27> Set Less Than (SLT) Example A B Configure a 32-bit ALU for the set if less than (SLT) operation. Suppose A = 25 and B = 32. F 2 C out + [-] S Zero Extend F : Y Copyright 27 Elsevier 5-<28> 4
15 Set Less Than (SLT) Example C out Zero Extend 3 A + [-] S 2 B Y 2 F 2 F : Configure a 32-bit ALU for the set if less than (SLT) operation. Suppose A = 25 and B = 32. A is less than B, so we expect Y to be the 32-bit representation of (x). For SLT, F 2: =. F 2 = configures the adder unit as a subtracter. So = -7. The two s complement representation of -7 has a in the most significant bit, so S 3 =. With F : =, the final multiplexer selects Y = S 3 (zero extended) = x. Copyright 27 Elsevier 5-<29> Shifters Logical shifter: shifts value to left or right and fills empty spaces with s Ex: >> 2 = Ex: << 2 = Arithmetic shifter: same as logical shifter, but on right shift, fills empty spaces with the old most significant bit (msb). Ex: >>> 2 = Ex: <<< 2 = Rotator: rotates bits in a circle, such that bits shifted off one end are shifted into the other end Ex: ROR 2 = Ex: ROL 2 = Copyright 27 Elsevier 5-<3> 5
16 Shifters Logical shifter: shifts value to left or right and fills empty spaces with s Ex: >> 2 = Ex: << 2 = Arithmetic shifter: same as logical shifter, but on right shift, fills empty spaces with the old most significant bit (msb). Ex: >>> 2 = Ex: <<< 2 = Rotator: rotates bits in a circle, such that bits shifted off one end are shifted into the other end Ex: ROR 2 = Ex: ROL 2 = Copyright 27 Elsevier 5-<3> Shifter Design A 3 A 2 A A shamt : 2 S : Y 3 shamt : A 3: >> Y 3: S : S : Y 2 Y S : Y Copyright 27 Elsevier 5-<32> 6
17 Shifters as Multipliers and Dividers A left shift by bits multiplies a number by 2 Ex: << 2 = ( 2 2 = 4) Ex: << 2 = ( = -2) The arithmetic right shift by divides a number by 2 Ex: >>> 2 = (8 2 2 = 2) Ex: >>> 2 = ( = -4) Copyright 27 Elsevier 5-<33> Multipliers Steps of multiplication for both decimal and binary numbers: Partial products are formed by multiplying a single digit of the multiplier with the entire multiplicand Shifted partial products are summed to form the result Decimal 23 x Binary multiplicand multiplier x partial products + result 23 x 42 = x 7 = 35 Copyright 27 Elsevier 5-<34> 7
18 4 x 4 Multiplier A 3 A 2 A A B B A B 4 4 x P 8 x A 3 A 2 A A B 3 B 2 B B A 3 B A 2 B A B A B A 3 B A 2 B A B A B A 3 B 2 A 2 B 2 A B 2 A B 2 + A 3 B 3 A 2 B 3 A B 3 A B 3 P 7 P 6 P 5 P 4 P 3 P 2 P P B 2 B 3 P 7 P 6 P 5 P 4 P 3 P 2 P P Copyright 27 Elsevier 5-<35> Division Algorithm Q = A/B R: remainder D: difference R = A for i = - to D = R - B if D < then Q i =, R = R // R < B else Q i =, R = D // R B R = 2R Copyright 27 Elsevier 5-<36> 8
19 4 x 4 Divider Copyright 27 Elsevier 5-<37> umber Systems What kind of numbers do you know how to represent using binary representations? Positive numbers Unsigned binary egative numbers Two s complement Sign/magnitude numbers What about fractions? Copyright 27 Elsevier 5-<38> 9
20 umbers with Fractions Two common notations: Fixed-point: the binary point is fixed Floating-point: the binary point floats to the right of the most significant Copyright 27 Elsevier 5-<39> Fixed-Point umbers Fixed-point representation of 6.75 using 4 integer bits and 4 fraction bits: = 6.75 The binary point is not a part of the representation but is implied. The number of integer and fraction bits must be agreed upon by those generating and those reading the number. Copyright 27 Elsevier 5-<4> 2
21 Fixed-Point umbers Ex: Represent 7.5 using an 8-bit binary representation with 4 integer bits and 4 fraction bits. Copyright 27 Elsevier 5-<4> Fixed-Point umbers Ex: Represent 7.5 using an 8-bit binary representation with 4 integer bits and 4 fraction bits. Copyright 27 Elsevier 5-<42> 2
22 Signed Fixed-Point umbers As with integers, negative fractional numbers can be represented two ways: Sign/magnitude notation Two s complement notation Represent -7.5 using an 8-bit binary representation with 4 integer bits and 4 fraction bits. Sign/magnitude: Two s complement: Copyright 27 Elsevier 5-<43> Signed Fixed-Point umbers As with integers, negative fractional numbers can be represented two ways: Sign/magnitude notation Two s complement notation Represent -7.5 using an 8-bit binary representation with 4 integer bits and 4 fraction bits. Sign/magnitude: Two s complement: Copyright 27 Elsevier 5-<44> 22
23 Signed Fixed-Point umbers As with integers, negative fractional numbers can be represented two ways: Sign/magnitude notation Two s complement notation Represent -7.5 using an 8-bit binary representation with 4 integer bits and 4 fraction bits. Sign/magnitude: Two s complement:. +7.5: 2. Invert bits: 3. Add to lsb: + Copyright 27 Elsevier 5-<45> Floating-Point umbers The binary point floats to the right of the most significant. Similar to decimal scientific notation. For example, write 273 in scientific notation: 273 = In general, a number is written in scientific notation as: ± M B E Where, M = mantissa B = base E = exponent In the example, M = 2.73, B =, and E = 2 Copyright 27 Elsevier 5-<46> 23
24 Floating-Point umbers bit 8 bits 23 bits Sign Exponent Mantissa Example: represent the value 228 using a 32-bit floating point representation We show three versions - final version is called the IEEE 754 floating-point standard Copyright 27 Elsevier 5-<47> Floating-Point Representation Convert the decimal number to binary: 228 = 2 =. 2 7 Fill in each field of the 32-bit number: The sign bit is positive () The 8 exponent bits represent the value 7 The remaining 23 bits are the mantissa bit 8 bits 23 bits Sign Exponent Mantissa Copyright 27 Elsevier 5-<48> 24
25 Floating-Point Representation 2 First bit of the mantissa is always : 228 = 2 =. 2 7 Thus, storing the most significant, also called the implicit leading, is redundant information. Instead, store just the fraction bits in the 23-bit field. The leading is implied. bit 8 bits 23 bits Sign Exponent Fraction Copyright 27 Elsevier 5-<49> Floating-Point Representation 3 Biased exponent: bias = 27 ( 2 ) Biased exponent = bias + exponent Exponent of 7 is as: = 34 = x 2 The IEEE bit floating-point representation of 228 bit 8 bits 23 bits Sign Biased Exponent Fraction Copyright 27 Elsevier 5-<5> 25
26 Floating-Point Example Write the value using the IEEE bit floatingpoint standard. Copyright 27 Elsevier 5-<5> Floating-Point Example Write the value using the IEEE bit floatingpoint standard. Convert the decimal number to binary: = Fill in each field in the 32-bit number: Sign bit: 8 Exponent bits: 23 fraction bits: bit 8 bits 23 bits Sign Exponent Fraction In hexadecimal: Copyright 27 Elsevier 5-<52> 26
27 Floating-Point Example Write the value using the IEEE bit floatingpoint standard. First, convert the decimal number to binary: =. 2 =. 2 5 ext, fill in each field in the 32-bit number: Sign bit: (negative) 8 exponent bits: (27 + 5) = 32 = 2 23 fraction bits: bit 8 bits 23 bits Sign Exponent Fraction In hexadecimal: xc269 Copyright 27 Elsevier 5-<53> Floating-Point umbers: Special Cases The IEEE 754 standard includes special cases for numbers that are difficult to represent, such as because it lacks an implicit leading. umber Sign Exponent Fraction X - a X non-zero a is used for numbers that don t exist, such as - or log(-5). Copyright 27 Elsevier 5-<54> 27
28 Floating-Point umber Precision Single-Precision: 32-bit notation sign bit, 8 exponent bits, 23 fraction bits bias = 27 Double-Precision: 64-bit notation sign bit, exponent bits, 52 fraction bits bias = 23 Copyright 27 Elsevier 5-<55> Floating-Point umbers: Rounding Overflow: number is too large to be represented Underflow: number is too small to be represented Rounding modes: Down Up Toward zero To nearest Example: round. (.57825) so that it uses only 3 fraction bits. Down:. Up:. Toward zero:. To nearest:. (.625 is closer to than.5 is) Copyright 27 Elsevier 5-<56> 28
29 Floating-Point Addition. Extract exponent and fraction bits 2. Prepend leading to form mantissa 3. Compare exponents 4. Shift smaller mantissa if necessary 5. Add mantissas 6. ormalize mantissa and adjust exponent if necessary 7. Round result 8. Assemble exponent and fraction back into floating-point format Copyright 27 Elsevier 5-<57> Floating-Point Addition: Example Add the following floating-point numbers: x3fc x45 Copyright 27 Elsevier 5-<58> 29
30 Floating-Point Addition: Example. Extract exponent and fraction bits bit 8 bits 23 bits Sign Exponent Fraction bit 8 bits 23 bits Sign Exponent Fraction For first number (): S =, E = 27, F =. For second number (2): S =, E = 28, F =. 2. Prepend leading to form mantissa :. 2:. Copyright 27 Elsevier 5-<59> Floating-Point Addition: Example 3. Compare exponents = -, so shift right by bit 4. Shift smaller mantissa if necessary shift s mantissa:. >> =. ( 2 ) 5. Add mantissas Copyright 27 Elsevier 5-<6> 3
31 Floating-Point Addition: Example 6. ormalize mantissa and adjust exponent if necessary. 2 = Round result o need (fits in 23 bits) 8. Assemble exponent and fraction back into floating-point format S =, E = = 29 = 2, F =.. bit 8 bits 23 bits Sign Exponent Fraction Written in hexadecimal: x498 Copyright 27 Elsevier 5-<6> Counters Increments on each clock edge. Used to cycle through numbers. For example,,,,,,,,,, Example uses: Digital clock displays Program counter: keeps track of current instruction executing Symbol Implementation CLK CLK Q Reset + r Reset Q Copyright 27 Elsevier 5-<62> 3
32 Shift Register Shift a new value in on each clock edge Shift a value out on each clock edge Serial-to-parallel converter: converts serial input (S in ) to parallel output (Q :- ) Symbol: Q Implementation: CLK S in S out S in S out Q Q Q 2 Q - Copyright 27 Elsevier 5-<63> Shift Register with Parallel Load When Load =, acts as a normal -bit register When Load =, acts as a shift register ow can act as a serial-to-parallel converter (S in to Q :- ) or a parallel-to-serial converter (D :- to S out ) Load Clk S in D D D 2 D - S out Q Q Q 2 Q - Copyright 27 Elsevier 5-<64> 32
33 Memory Arrays Efficiently store large amounts of data Three common types: Dynamic random access memory (DRAM) Static random access memory (SRAM) Read only memory (ROM) An M-bit data value can be read or written at each unique - bit address. Address Array M Data Copyright 27 Elsevier 5-<65> Memory Arrays Two-dimensional array of bit cells Each bit cell stores one bit An array with address bits and M data bits: 2 rows and M columns Depth: number of rows (number of words) Width: number of columns (size of word) Array size: depth width = 2 M Address Array M Data Address 2 Array 3 Data Address Data width depth Copyright 27 Elsevier 5-<66> 33
34 Memory Array: Example bit array umber of words: 4 Word size: 3-bits For example, the 3-bit word at address is Example: Address Data Address 2 Array depth 3 Data width Copyright 27 Elsevier 5-<67> Memory Arrays Address 24-word x 32-bit Array 32 Data Copyright 27 Elsevier 5-<68> 34
35 Memory Array Bit Cells Example: Copyright 27 Elsevier 5-<69> Memory Array Bit Cells Example: Z Z Copyright 27 Elsevier 5-<7> 35
36 Memory Array Wordline: similar to an enable allows a single row in the memory array to be read or written corresponds to a unique address only one wordline is HIGH at any given time 2:4 Decoder bitline 2 bitline bitline Address 2 wordline 3 wordline 2 wordline wordline bit = bit = bit = bit = bit = bit = bit = bit = bit = bit = bit = bit = Copyright 27 Elsevier 5-<7> Data 2 Data Data Types of Memory Random access memory (RAM): volatile Read only memory (ROM): nonvolatile Copyright 27 Elsevier 5-<72> 36
37 RAM: Random Access Memory Volatile: loses its data when the power is turned off Read and written quickly Main memory in your computer is RAM (DRAM) Historically called random access memory because any data word can be accessed as easily as any other (in contrast to sequential access memories such as a tape recorder) Copyright 27 Elsevier 5-<73> ROM: Read Only Memory onvolatile: retains data when power is turned off Read quickly, but writing is impossible or slow Flash memory in cameras, thumb drives, and digital cameras are all ROMs Historically called read only memory because ROMs were written at manufacturing time or by burning fuses. Once ROM was configured, it could not be written again. This is no longer the case for Flash memory and other types of ROMs. Copyright 27 Elsevier 5-<74> 37
38 Types of RAM Two main types of RAM: Dynamic random access memory (DRAM) Static random access memory (SRAM) Differ in how they store data: DRAM uses a capacitor SRAM uses cross-coupled inverters Copyright 27 Elsevier 5-<75> Robert Dennard, Invented DRAM in 966 at IBM Others were skeptical that the idea would work By the mid-97 s DRAM was in virtually all computers Copyright 27 Elsevier 5-<76> 38
39 DRAM Data bits on a capacitor Called dynamic because the value needs to be refreshed (rewritten) periodically and after being read: Charge leakage from the capacitor degrades the value Reading destroys the value wordline bitline bit Copyright 27 Elsevier 5-<77> DRAM wordline bitline wordline bitline bit = + + bit = Copyright 27 Elsevier 5-<78> 39
40 SRAM wordline bit bitline wordline bitline bitline Copyright 27 Elsevier 5-<79> Memory Arrays 2:4 Decoder bitline 2 bitline bitline Address 2 wordline 3 wordline 2 wordline wordline bit = bit = bit = bit = bit = bit = bit = bit = bit = bit = bit = bit = Data 2 Data Data DRAM bit cell: wordline bitline SRAM bit cell: wordline bitline bitline Copyright 27 Elsevier 5-<8> 4
41 ROMs: Dot otation wordline bitline wordline bit cell containing bit cell containing bitline Copyright 27 Elsevier 5-<8> Fujio Masuoka, 944- Developed memories and high speed circuits at Toshiba from Invented Flash memory as an unauthorized project pursued during nights and weekends in the late 97 s. The process of erasing the memory reminded him of the flash of a camera Toshiba slow to commercialize the idea; Intel was first to market in 988 Flash has grown into a $25 billion per year market. Copyright 27 Elsevier 5-<82> 4
42 ROM Storage Address Data width depth Copyright 27 Elsevier 5-<83> ROM Logic Data 2 = A A Data = A + A Data = A A Copyright 27 Elsevier 5-<84> 42
43 Example: Logic with ROMs Implement the following logic functions using a bit ROM: X = AB Y = A + B Z = AB Copyright 27 Elsevier 5-<85> Example: Logic with ROMs Implement the following logic functions using a bit ROM: X = AB 2:4 Y = A + B Decoder Z = A B A, B 2 X Y Z Copyright 27 Elsevier 5-<86> 43
44 Logic with Any Memory Array 2:4 Decoder bitline 2 bitline bitline Address 2 wordline 3 wordline 2 wordline wordline bit = bit = bit = bit = bit = bit = bit = bit = bit = bit = bit = bit = Data 2 Data Data Data 2 = A A Data = A + A Data = A A Copyright 27 Elsevier 5-<87> Logic with Memory Arrays Implement the following logic functions using a bit memory array: X = AB Y = A + B Z = A B A, B 2 2:4 Decoder wordline 3 wordline 2 wordline wordline bit = bit = bit = bit = bitline 2 bitline bitline bit = bit = bit = bit = bit = bit = bit = bit = X Y Z Copyright 27 Elsevier 5-<88> 44
45 Logic with Memory Arrays Called lookup tables (LUTs): look up output at each input combination (address) 4-word x -bit Array Truth Table A B Y A B 2:4 Decoder A A bit = bit = bit = bit = bitline Copyright 27 Elsevier 5-<89> Y Multi-ported Memories Port: address/data pair 3-ported memory 2 read ports (A/RD, A2/RD2) write port (A3/WD3, WE3 enables writing) Small multi-ported memories are called register files CLK A A2 WE3 RD RD2 M M M A3 WD3 Array Copyright 27 Elsevier 5-<9> 45
46 Verilog Memory Arrays // 256 x 3 memory module with one read/write port module dmem( input clk, we, input [7:] a input [2:] wd, output [2:] rd); reg [2:] RAM[255:]; assign rd = RAM[a]; clk) if (we) RAM[a] <= wd; endmodule Copyright 27 Elsevier 5-<9> Logic Arrays Programmable logic arrays (PLAs) AD array followed by OR array Perform combinational logic only Fixed internal connections Field programmable gate arrays (FPGAs) Array of configurable logic blocks (CLBs) Perform combinational and sequential logic Programmable internal connections Copyright 27 Elsevier 5-<92> 46
47 PLAs X = ABC + ABC Y = AB Inputs M AD ARRAY Implicants OR ARRAY P Outputs A B C OR ARRAY ABC ABC AB AD ARRAY X Y Copyright 27 Elsevier 5-<93> PLAs: Dot otation Inputs M AD ARRAY Implicants OR ARRAY A B C P Outputs OR ARRAY ABC ABC AB Copyright 27 Elsevier AD ARRAY 5-<94> X Y 47
48 FPGAs: Field Programmable Gate Arrays Composed of: CLBs (Configurable logic blocks): perform logic IOBs (Input/output buffers): interface with outside world Programmable interconnection: connect CLBs and IOBs Some FPGAs include other building blocks such as multipliers and RAMs Copyright 27 Elsevier 5-<95> Xilinx Spartan 3 FPGA Schematic Copyright 27 Elsevier 5-<96> 48
49 CLBs: Configurable Logic Blocks Composed of: LUTs (lookup tables): perform combinational logic Flip-flops: perform sequential functions Multiplexers: connect LUTs and flip-flops Copyright 27 Elsevier 5-<97> Xilinx Spartan CLB Copyright 27 Elsevier 5-<98> 49
50 Xilinx Spartan CLB The Spartan CLB has: 3 LUTs: F-LUT (2 4 x -bit LUT) G-LUT (2 4 x -bit LUT) H-LUT (2 3 x -bit LUT) 2 registered outputs: XQ YQ 2 combinational outputs: X Y Copyright 27 Elsevier 5-<99> CLB Configuration Example Show how to configure the Spartan CLB to perform the following functions: X = ABC + ABC Y = AB Copyright 27 Elsevier 5-<> 5
51 CLB Configuration Example Show how to configure the Spartan CLB to perform the following functions: X = ABC + ABC Y = AB F4 X X X X X X X x (A) (B) (C) (X) F3 F2 F F G4 X X X X G3 X X X X (A) (B) (Y) G2 G G A B A B C G4 G3 G2 G F4 F3 F2 F G F Y X Copyright 27 Elsevier 5-<> FPGA Design Flow A CAD tool (such as Xilinx Project avigator) is used to design and implement a digital system. It is usually an iterative process. The user enters the design using schematic entry or an HDL. The user simulates the design. A synthesis tool converts the code into hardware and maps it onto the FPGA. The user uses the CAD tool to download the configuration onto the FPGA This configures the CLBs and the connections between them and the IOBs. Copyright 27 Elsevier 5-<2> 5
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