Chapter 3 Top Level View of Computer Function and Interconnection
Contents Computer Components Computer Function Interconnection Structures Bus Interconnection PCI 3-2
Program Concept Computer components Hardwired systems are inflexible General purpose hardware can do different tasks, given correct control signals Instead of re-wiring, supply a new set of control signals 3-3
What Is A Program? Computer components A sequence of steps For each step, an arithmetic or logical operation is done For each operation, a different set of control signals is needed 3-4
Function of Control Unit Computer components For each operation a unique code is provided e.g. ADD, MOVE A hardware segment accepts the code and issues the control signals We have a computer! 3-5
Hardware & Software Approaches Computer components 3-6
Computer Components Computer components Programming is now much easier To distinguish this new method of programming, a sequence of codes or instruction is called software Instruction interpreter & a module of general-purpose arithmetic and logic functions 3-7
Components Computer components The process of connecting together the various components in the desired configuration as a form of programming The resulting program is in the form of hardware and is termed a hardwired program The system accepts data and produces results For each step, a new set of control signals is needed 3-8
Components The Control Unit and the Arithmetic and Computer components Logic Unit constitute the Central Processing Unit Data and instructions need to get into the system and results out Input/output Temporary storage of code and results is needed Main memory 3-9
Computer Components:Top Level View Computer components 3-10
Basic Instruction Cycle Computer function Two steps: Fetch Execute 3-11
Instruction Fetch & Execute Computer function Program Counter (PC) holds address of next instruction to fetch Processor fetches instruction from memory location pointed to by PC Increment PC (Unless told otherwise) Instruction loaded into Instruction Register (IR) Instruction contains bits to act of processor Processor interprets instruction and performs required actions 3-12
Execute Cycle Processor-memory data transfer between CPU and main memory Processor I/O Data transfer between CPU and I/O module Data processing Some arithmetic or logical operation on data Control Alteration of sequence of operations e.g. jump Combination of above Computer function 3-13
Characteristics of A Hypothetical Machine Instruction Format 0 3 4 15 Computer function Opcode Integer Format 0 1 s Magnitude Address 15 internal CPU register Program Counter(PC) = Address of Instruction Instruction Register(IR) = Instruction Being Executed Accumulator(AC) = Temporary Storage Partial List of Opcodes 0001 = Load AC from Memory 0010 = Store AC to Memory 0101 = Add to AC from Memory 3-14
Example of Program Execution Computer function 3-15
Instruction Fetch & Execute Computer function With a more complex set of instruction, need fewer cycle Modern processor include instruction of containing more than one address Execution cycle for a particular instruction involve more than one reference to memory 3-16
Instruction Cycle State Diagram Computer function 3-17
Instruction Cycle State Instruction address calculation (iac) Determine the address of the next instruction to be executed Instruction fetch (if) Read instruction from its memory location into the processor Instruction operation decoding (iod) Analyze instruction to determine type of operation to be performed & operands to be used Operand address calculation (aoc) Determine the address of operand (If operation involve reference to an operand in memory or I/O module Computer function 3-18
Instruction Cycle State Computer function Operand fetch (of) Fetch the operand from memory or read it from I/O Data operation (do) Perform the operation indicated in the instruction Operand store (os) Write the result into memory or out to I/O 3-19
Instruction Cycle State Single Instruction specify an operation to be performed on a vector of numbers or a string of characters (on some machines) Computer function 3-20
Interrupts Virtually all computers provide a mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing Computer function Interrupts provided to improve processing efficiency 3-21
Class of Interrupts Program Timer I/O Hardware failure Computer function Generated by some condition that occurs as a result of an instruction execution such as arithmetic overflow division by zero, attempt to execute an illegal machine instruction, and reference outside a user s s allowed memory space Generated by a timer within the processor. sor. This allows the operating system to perform certain functions on a regular basis Generated by an I/O controller, to signal normal completion of an operation or to signal a variety of error conditions Generated by a failure such as power failure or memory parity error 3-22
No Interrupts Most external devices are much slower than the processor Suppose that the processor is transferring data to a printer, the processor must pause and remain idle until the printer catches up The Write Calls are to an I/O program In label 4(figure), processor prepare for the actual I/O operation Without the use of interrupts, once I/O operation command is issued, the program must wait for the I/O device to perform the requested function and repeatedly perform a test operation to determine if the I/O operation is done In label 5(figure) processor complete the operation This may include setting a flag indication the success or failure of the operation Computer function 3-23
Interrupts The user program performs a series of WRITE calls interleaved with processing The WRITE calls are to an I/O program that is a system utility and that will perform the actual I/O operation I/O program consists of three sections A sequence of instruction to prepare actual I/O operation The actual I/O command A sequence of instruction to complete operation Computer function 3-24
Interrupts & The Instruction Cycle Computer function With interrupts, the processor engaged in executing other instructions while I/O operation is in progress When the external device becomes ready to be serviced, the I/O module sends interrupt request signal to the processor The processor responds by suspending operation of the current program, branching off to a program to service that particular I/O device and resuming the original execution after the device is served 3-25
Program Flow Control Computer function User Program 1 WRITE 4 I/O program 5 I/O command User Program 1 WRITE 4 I/O program 2 2a interrupt 5 I/O command 2b WRITE WRITE 3a 3 interrupt 3 3-26
Program Flow Control Computer function 3-27
Transfer of Control Via Interrupts Computer function The processor and the operating system are responsible for suspending user program and resuming it at the same point 1 Interrupt Occurs Here 2 i i+1......... M 3-28
Interrupt Cycle Computer function Added to instruction cycle Processor checks for interrupt Indicated by an interrupt signal If no interrupt, fetch next instruction If interrupt pending processor does: Suspend execution of current program Save context Set PC to start address of interrupt handler routine Process interrupt Restore context and continue interrupted program 3-29
Instruction Cycle With Interrupts Computer function 3-30
Program Timing: Short I/O Wait Less than time to complete execution of instructions between write operations in user program Computer function 3-31
Program Timing: Short I/O Wait User Program 1 WRITE 4 I/O program 5 I/O command Computer function 2 WRITE 3 User Program 1 WRITE 2a interrupt 2b 4 I/O program 5 I/O command 3-32 WRITE 3a interrupt 3
Program Timing: Long I/O Wait User program reaches second WRITE call before I/O operation spawned by the first call is complete User program is hung up at that point Gain efficiency because of time during which I/O operation underway overlaps with execution of user instructions Computer function 3-33
Program Timing: Long I/O Wait Computer function 3-34
Instruction Cycle (with Interrupts) Computer function 3-35
Multiple Interrupts Computer function The first approach is to disable interrupts while an interrupt is being processed Nice & simple, Interrupts handled in strict sequential order Drawback : Do not take into account relative priority or time-critical needs 3-36
Multiple Interrupts A second approach is to define priorities for interrupts and to allow interrupt of higher priority to cause a lower-priority interrupt handler to be itself interrupted Computer function higher priority than X 3-37
Time Sequence of Multiple Interrupts Computer function t = 10 printer interrupt t = 15 communication interrupt t = 20 Disk interrupt Communication > Disk > Printer 3-38
Multiple Interrupts Computer function Disable interrupts The processor will ignore further interrupts while processing one interrupt Interrupts remain pending and are checked after first interrupt has been processed Interrupts handled in sequence as they occur Define priorities Low priority interrupts can be interrupted by higher priority interrupts When a higher priority interrupt has been processed, the processor returns to the previous interrupt 3-39
I/O Function Computer function An I/O module can exchange data directly with the processor Desirable to allow I/O exchanges to occur directly with memory The processor grants to an I/O module the authority to read from or write to memory, so that the I/O memory transfer can occur without tying up the processor 3-40
Interconnection Structures Interconnection structures The collection of paths connecting various modules is called interconnection structure The design of the structure depends on the exchanges that must be made between modules Memory Input/Output CPU 3-41
Memory Connection Interconnection structures Receives and sends data Receives addresses (of locations) Receives control signals Read Write Timing 3-42
Input/Output Connection Interconnection structures Similar to memory from computer s viewpoint Output Receive data from computer Send data to peripheral Input Receive data from peripheral Send data to computer 3-43
Input/Output Connection Receive control signals from computer Send control signals to peripherals e.g. spin disk Receive addresses from computer e.g. port number to identify peripheral Send interrupt signals (control) Interconnection structures 3-44
CPU Connection Interconnection structures Reads instruction and data Writes out data (after processing) Sends control signals to other units Receives (& acts on) interrupts 3-45
Interconnection Structure Interconnection structures Interconnection structure support this type of transfers Memory to processor: The processor reads instruction or unit of data from memory Processor to memory: The processor writes unit of data to memory I/O to processor: The processor reads data from I/O device via I/O module Processor to I/O: The processor sends data to the I/O device I/O to or from memory : using DMA, an I/O module is allowed to exchange data directly with memory 3-46
Bus Interconnection Bus interconnection A bus is a communication pathway connecting two or more devices A key characteristic of bus is a shared transmission medium A system bus connects major computer components (processor, memory, I/O) There are a number of possible interconnection systems Single and multiple BUS structures are most common e.g. Control/Address/Data bus (PC) e.g. Unibus (DEC-PDP) 3-47
What Is A Bus? Bus interconnection A communication pathway connecting two or more devices Usually broadcast Often grouped A number of channels in one bus e.g. 32 bit data bus is 32 separate single bit channels Power lines may not be shown 3-48
Bus Structure Data Bus Bus interconnection Data lines provide path for moving data be tween system module Data lines collectively called data bus Remember that there is no difference between data and instruction at this level The data bus width is a key determinant of performance 8, 16, 32, 64 bit 3-49
Bus Structure - Address Bus Bus interconnection Address lines used to designate source or destination of the data on the data bus e.g. CPU needs to read an instruction (data) from a given location in memory The address bus width determines maximum memory capacity of system e.g. 8080 has 16 bit address bus giving 64k address space 3-50
Bus Structure - Control Bus Bus interconnection Control lines used to control access to and use of data and address lines Control and timing information Memory write/read I/O write/read Transfer ACK Bus request Bus grant Interrupt request Interrupt ACK Clock Reset 3-51
Bus Interconnection Scheme Bus interconnection 3-52
Operation of Bus Bus interconnection One module wishes to send data to another Obtain the use of the bus Transfer data via the bus One module wishes to request data from another module Obtain the use of the bus Transfer a request of the other module over the appropriate control and address lines Wait for second module to send the data 3-53
Typical Physical Realization Bus interconnection 3-54
Big And Yellow? Bus interconnection What do buses look like? Parallel lines on circuit boards Ribbon cables Strip connectors on mother boards e.g. PCI Sets of wires 3-55
Single Bus Problems Bus interconnection If a great number of devices connected to the bus, performance will suffer More devices attached to the bus, the greater bus length and hence greater propagation delay Bus become a bottleneck as the aggregate data transfer demand approaches capacity of bus Therefore, most systems use multiple buses 3-56
Multiple-Bus Hierarchies Bus interconnection I/O devices attached to expansion bus To build high-speed bus that closely integrated with the rest of system, requiring only a bridge between the processor s bus and high speed bus 3-57
Traditional Bus Architecture Bus interconnection 3-58
High Performance Architecture The high speed bus brings high-demand devices into closer integration with the processor and at the same time is independent of the processor Bus interconnection Differences in processor and high-speed bus speeds and signal line definitions are tolerated Changes in processor architecture do not affect the high-speed bus, and vice versa 3-59
High Performance Architecture Bus interconnection 3-60
Elements of f Bus Design Type Dedicated Multiplexed Method of Arbitration Timing Centralized Distributed Synchronous Asynchronous Bus Width Address Data Data Transfer Type Read Write Read-modify-write Read-after-write Block Bus interconnection 3-61
Bus Types Dedicated bus line Bus interconnection Functional dedication - Assign one function Physical dedication - Refers to use of multiple bus & Connects subset of modules Advantage High through-put Disadvantage Increased size and cost of the system Multiplexed Shared lines Address valid or data valid control line Advantage - Fewer lines Disadvantages - More complex control & Ultimate performance 3-62
Method of Arbitration Bus interconnection Method of arbitration needed because only one unit can successfully transmit over the bus at a time Bus Arbitration More than one module controlling the bus e.g. CPU and DMA controller Only one module may control bus at one time Arbitration may be centralised or distributed Centralised Arbitration Single hardware device controlling bus access Bus Controller Arbiter May be part of CPU or separate Distributed Arbitration Each module may claim the bus Control logic on all modules 3-63
Timing Bus interconnection Co-ordination of events on bus The bus includes a clock line upon which clock transmits a regular sequence of alternating 1s & 0s of equal duration A single 1-0 transmission is referred to as a clock cycle of bus cycle 3-64
Synchronous Timing Bus interconnection Events determined by clock signals Control Bus includes clock line A single 1-0 transmission is a clock cycle or a bus cycle All devices can read the clock line Usually bus signal change on leading edge Usually a single cycle for an event Synchronous timing is simpler to implement and test Less flexible than asynchronous timing 3-65
Synchronous Timing Bus interconnection 3-66
AsynchronousTiming Bus interconnection The occurrence of one event depends on the occurrence of a previous event A mixture of slow and fast devices, using older and newer technology, can share a bus 3-67
Asynchronous Timing Bus interconnection 3-68
BUS Width Bus interconnection The wider the data bus, the greater the number of bits transferred at one time The wider the address bus, the greater range of locations that can be referenced 3-69
Bus Data Transfer Types Bus interconnection 3-70
PCI PCI Peripheral Component Interconnection A popular high-bandwidth, processor-independent bus that can function as a mezzanine or peripheral bus Delivers better system performance for high-speed I/O subsystems Supports a variety of microprocessor-based configurations Uses of synchronous timing and a centralized arbitration scheme 32 or 64 bit 528MB/s-4.224Gbps 3-71
Example PCI Configurations Typical Desktop System PCI 3-72
Example PCI Configurations Typical Server System PCI 3-73
Interpretation of PCI Read Commands PCI Read Command Type Memory Read Memory Read Line Memory Read Multiple For Cachable Memory Bursting one-half or less of a cache line Bursting more than one-half a cache line to three cache lines Bursting more than three cache lines For Noncachable Memory Bursting 2 data transfer cycles of less Bursting 3 to 12 data transfers Bursting more than 12 data transfers 3-74
PCI Bus Lines - Required PCI Systems Lines Including clock and reset Address & Data 32 time mux lines for address/data Interrupt & validate lines Interface Control Arbitration Not shared Direct connection to PCI bus arbiter Error-reporting Lines 3-75
PCI Bus Lines - Optional PCI Interrupt lines Not shared Cache support 64-bit Bus Extension Additional 32 lines Time multiplexed 2 lines to enable devices to agree to use 64-bit transfer JTAG/Boundary Scan For testing procedures 3-76
PCI Commands Interrupt Acknowledge Special Cycle I/O Read I/O Write Memory Read Memory Read line Memory Read Multiple Memory Write Memory Write and Invalidate Configuration Read Configuration Write Dual Address Cycle PCI 3-77
PCI Commands 3-78 Interrupt Acknowledge is a read command intended for the device that functions as an interrupt controller on the PCI bus The Special Cycle command is used by the initiator to broadcast a message to one or more targets I/O Read and Write commands are used to transfer data between the initiator and an I/O controller The Memory Read/Write commands are used to specify the transfer of a burst of data occupying one or more clock cycles PCI
PCI Commands PCI The Memory Write & Invalidate command transfers data in one or more cycles to memory and guarantees that at least one cache line is written Two configuration commands enable a master to read and update configuration parameters in a device connected to PCI The Dual Address Cycle command is used by an initiator to indicate that it is using 64-bit addressing 3-79
PCI Read Operation PCI 3-80
Arbitration PCI makes use of a centralized, synchronous arbitration scheme Each master has unique request(req) and grant(gnt) signal A simple request-grant handshake used to grant access to bus Arbitration can take place at the same time that current bus master performing data transfer Hidden arbitration No bus cycles lost in performing arbitration PCI 3-81
PCI Bus Arbiter PCI 3-82
PCI Bus Arbitration Between Two Master PCI 3-83