5-23 The course that gies CMU its Zip! Cache Memories Oct, 2 Topics Generic cache memory organization Direct mapped caches Set associatie caches Impact of caches on performance Cache memories Cache memories are small, fast SRAM-based memories managed automatically in hardware. Hold frequently accessed blocks of main memory CPU looks first for data in L, then in L2, then in main memory. Typical bus structure: CPU chip register file L ALU cache cache bus system bus memory bus L2 cache bus interface I/O bridge main memory 2 Inserting an L cache between the CPU and main memory The transfer unit between the CPU register file and the cache is a 4-byte block. line line The transfer unit between the cache and main memory is a 4-word block (6 bytes). block block 2 block 3 a b c d... p q r s... w x y z... 3 The tiny, ery fast CPU register file has room for four 4-byte words. The small fast L cache has room for two 4-word blocks. The big slow main memory has room for many 4-word blocks. General organization of a cache memory Cache is an array of sets. Each set contains one or more lines. Each line holds a block of data. S = 2 s sets set : set : set S-: bit per line t bits per line B = 2 b bytes per B Cache size: C = B x E x S data bytes 4 B B B B B E lines per set
Addressing caches Address A: t bits s bits b bits Direct-mapped cache Simplest kind of cache Characterized by exactly one line per set. set : B B m- <> <set index> <block offset> set : set S-: B B B B The word at address A is in the cache if the bits in one of the <> lines in set <set index> match <>. The word contents begin at offset <block offset> bytes from the beginning of the block. set : set : set S-: E= lines per set 5 6 Accessing direct-mapped caches Set selection Use the set index bits to determine the set of interest. Accessing direct-mapped caches Line matching and word selection find a line in the selected set with a matching (line matching) then extract the word (word selection) set : =? () The bit must be set m- t bits selected set s bits b bits set index block offset set : set S-: selected set (i): (2) The bits in the cache line must match the bits in the address m- t bits 2 3 4 5 6 7 w w w 2 w 3 =? (3) If () and (2), then cache hit, and block offset s bits b bits i set index block offset selects starting byte. 7 8
Direct-mapped cache simulation t= s=2 b= x xx x () (3) M=6 byte addresses, B=2 bytes/block, S=4 sets, E= entry/set Address trace (reads): [] [] 3 [] 8 [] [] [] (miss) data m[] m[] 8 [] (miss) data m[9] m[8] 9 (2) (4) 3 [] (miss) data m[] m[] m[3] m[2] [] (miss) data m[] m[] m[3] m[2] Why use middle bits as index? High-Order Bit Indexing Adjacent memory lines would map to same cache entry Poor use of spatial locality Middle-Order Bit Indexing Consecutie memory lines map to different cache lines Can hold C-byte region of address space in cache at one time 4-line Cache High-Order Bit Indexing Middle-Order Bit Indexing Set associatie caches Characterized by more than one line per set Accessing set associatie caches Set selection identical to direct-mapped cache set : E=2 lines per set set : set : Selected set set : set S-: m- t bits s bits b bits set index block offset set S-: 2
Accessing set associatie caches Line matching and word selection must compare the in each line in the selected set. =? () The bit must be set. Multi-leel caches Options: separate data and instruction caches, or a unified cache Processor TLB selected set (i): 2 3 4 5 6 7 w w w 2 w 3 regs L Dcache L Icache L2 Cache Memory disk disk (2) The bits in one of the cache lines must match the bits in the address m- =? t bits s bits b bits i set index block offset (3) If () and (2), then cache hit, and block offset selects starting byte. size: speed: $/Mbyte: line size: 2 B 3 ns 8-64 KB 3 ns 8 B 32 B larger, slower, cheaper -4MB SRAM 6 ns $/MB 32 B 28 MB DRAM 6 ns $.5/MB 8 KB 3 GB 8 ms $.5/MB larger line size, higher associatiity, more likely to write back 3 4 Intel Pentium cache hierarchy Regs. L Data cycle latency 6KB 4-way assoc Write-through 32B lines L Instruction 6KB, 4-way 32B lines Processor Chip L2 Unified 28KB--2 MB 4-way assoc Write-back Write allocate 32B lines Main Memory Up to 4GB Cache performance metrics Miss Rate fraction of memory references not found in cache (misses/references) Typical numbers: Hit Time 3-% for L can be quite small (e.g., < %) for L2, depending on size, etc. time to delier a line in the cache to the processor (includes time to determine whether the line is in the cache) Typical numbers: clock cycle for L 3-8 clock cycles for L2 Miss Penalty additional time required because of a miss Typically 25- cycles for main memory 5 6
Writing cache friendly code Repeated references to ariables are good (temporal locality) Stride- reference patterns are good (spatial locality) Example cold cache, 4-byte words, 4-word s The Memory Mountain Read throughput (read bandwidth) Number of bytes read from memory per second (MB/s) Memory mountain Measured read throughput as a function of spatial and temporal locality. Compact way to characterize memory system performance. int sumarrayrows(int a[m][n]) { int i, j, sum = ; int sumarraycols(int a[m][n]) { int i, j, sum = ; for (i = ; i < M; i++) for (j = ; j < N; j++) sum += a[i][j]; return sum; for (j = ; j < N; j++) for (i = ; i < M; i++) sum += a[i][j]; return sum; Miss rate = Miss rate = 7 8 Memory mountain test function /* The test function */ oid test(int elems, int stride) { int i, result = ; olatile int sink; for (i = ; i < elems; i += stride) result += data[i]; sink = result; /* So compiler doesn't optimize away the loop */ /* Run test(elems, stride) and return read throughput (MB/s) */ double run(int size, int stride, double Mhz) { double cycles; int elems = size / sizeof(int); test(elems, stride); /* warm up the cache */ cycles = fcyc2(test, elems, stride, ); /* call test(elems,stride) */ return (size / stride) / (cycles / Mhz); /* conert cycles to MB/s */ Memory mountain main routine /* mountain.c - Generate the memory mountain. */ #define MINBYTES ( << ) /* Working set size ranges from KB */ #define MAXBYTES ( << 23) /*... up to 8 MB */ #define MAXSTRIDE 6 /* Strides range from to 6 */ #define MAXELEMS MAXBYTES/sizeof(int) int data[maxelems]; /* The array we'll be traersing */ int main() { int size; /* Working set size (in bytes) */ int stride; /* Stride (in array elements) */ double Mhz; /* Clock frequency */ init_data(data, MAXELEMS); /* Initialize each element in data to */ Mhz = mhz(); /* Estimate the clock frequency */ for (size = MAXBYTES; size >= MINBYTES; size >>= ) { for (stride = ; stride <= MAXSTRIDE; stride++) printf("%.f\t", run(size, stride, Mhz)); printf("\n"); exit(); 9 2
read throughput (MB/s) Slopes of Spatial Locality 2 8 6 4 2 s The Memory Mountain s3 stride (words) s5 s7 s9 s s3 mem s5 xe 8m L2 2m 52k 28k L 32k 8k 2k Pentium III Xeon 55 MHz 6 KB on-chip L d-cache 6 KB on-chip L i-cache 52 KB off-chip unified L2 cache Ridges of Tem poral Locality working set size (bytes) Ridges of temporal locality Slice through the memory mountain with stride= illuminates read throughputs of different caches and memory read througput (MB/s) 2 8 6 4 2 8m main memory region 4m 2m 24k 52k 256k L2 cache region 28k 64k 32k working set size (bytes) 6k 8k L cache region 4k 2k k 2 22 A slope of spatial locality Slice through memory mountain with size=256kb shows size. read throughput (MB/s) 8 7 6 5 one access per cache line 4 3 2 s s2 s3 s4 s5 s6 s7 s8 s9 s s s2 s3 s4 s5 s6 stride (words) 23 Matrix multiplication example Major Cache Effects to Consider Total cache size Exploit temporal locality and keep the working set small (e.g., by using blocking) Block size /* /* ijk ijk */ */ Variable sum for Exploit spatial locality for (i=; (i=; i<n; i<n; i++) i++) { held in register for for (j=; (j=; j<n; j<n; j++) j++) { sum sum =.;.; for for (k=; (k=; k<n; k<n; k++) k++) sum sum += += a[i][k] a[i][k] * b[k][j]; b[k][j]; Multiply N x N matrices c[i][j] c[i][j] = sum; sum; O(N 3 ) total operations Accesses Description: N reads per source element N alues summed per destination» but may be able to hold in register 24
Miss rate analysis for matrix multiply Assume: Line size = 32B (big enough for 4 64-bit words) Matrix dimension (N) is ery large Approximate /N as. Cache is not een big enough to hold multiple rows Analysis Method: Look at access pattern of inner loop i k A k j B i j C Layout of arrays in memory C arrays allocated in row-major order each row in contiguous memory locations Stepping through columns in one row: for (i = ; i < N; i++) sum += a[][i]; accesses successie elements if block size (B) > 4 bytes, exploit spatial locality compulsory miss rate = 4 bytes / B Stepping through rows in one column: for (i = ; i < n; i++) sum += a[i][]; accesses distant elements no spatial locality! compulsory miss rate = (i.e. %) 25 26 Matrix multiplication (ijk) Matrix multiplication (jik) /* /* ijk ijk */ */ for for (i=; (i=; i<n; i<n; i++) i++) { for for (j=; (j=; j<n; j<n; j++) j++) { sum sum =.;.; for for (k=; (k=; k<n; k<n; k++) k++) sum sum += += a[i][k] * b[k][j]; c[i][j] = sum; sum;.25.. (i,*) (*,j) (i,j) Row-wise /* /* jik jik */ */ for for (j=; (j=; j<n; j<n; j++) j++) { for for (i=; (i=; i<n; i<n; i++) i++) { sum sum =.;.; for for (k=; (k=; k<n; k<n; k++) k++) sum sum += += a[i][k] * b[k][j]; c[i][j] = sum sum.25.. Row-wise (i,*) (*,j) Columnwise Columnwise (i,j) 27 28
Matrix multiplication (kij) Matrix multiplication (ikj) /* kij */ for (k=; k<n; k++) { for (i=; i<n; i++) { r = a[i][k]; for (j=; j<n; j++) c[i][j] += r * b[k][j]; (i,k) (k,*) (i,*) /* ikj */ for (i=; i<n; i++) { for (k=; k<n; k++) { r = a[i][k]; for (j=; j<n; j++) c[i][j] += r * b[k][j]; (i,k) (k,*) (i,*) Row-wise Row-wise Row-wise Row-wise..25.25..25.25 29 3 Matrix multiplication (jki) Matrix multiplication (kji) /* jki */ for (j=; j<n; j++) { for (k=; k<n; k++) { r = b[k][j]; for (i=; i<n; i++) c[i][j] += a[i][k] * r;... (*,k) (k,j) (*,j) Column - wise /* kji */ for (k=; k<n; k++) { for (j=; j<n; j++) { r = b[k][j]; for (i=; i<n; i++) c[i][j] += a[i][k] * r;... (*,k) (k,j) (*,j) Columnwise Columnwise Columnwise 3 32
Summary of matrix multiplication ijk (& jik): 2 loads, stores misses/iter =.25 kij (& ikj): 2 loads, store misses/iter =.5 jki (& kji): 2 loads, store misses/iter = 2. Pentium matrix multiply performance Notice that miss rates are helpful but not perfect predictors. Code scheduling matters, too. 6 for (i=; i<n; i++) { for (k=; k<n; k++) { for (j=; j<n; j++) { 5 for (j=; j<n; j++) { for (i=; i<n; i++) { for (k=; k<n; k++) { sum =.; for (k=; k<n; k++) sum += a[i][k] * b[k][j]; c[i][j] = sum; r = a[i][k]; for (j=; j<n; j++) c[i][j] += r * b[k][j]; r = b[k][j]; for (i=; i<n; i++) c[i][j] += a[i][k] * r; Cycles/iteration 4 3 2 kji jki kij ikj jik ijk 33 25 5 75 25 5 75 2 225 25 275 3 325 35 375 4 Array size (n) 34 Improing temporal locality by blocking Example: Blocked matrix multiplication block (in this context) does not mean. Instead, it mean a sub-block within the matrix. Example: N = 8; sub-block size = 4 A A2 B B2 C C2 X = A2 A22 B2 B22 C2 C22 Key idea: Sub-blocks (i.e., A xy ) can be treated just like scalars. C = A B + A 2 B 2 C 2 = A B 2 + A 2 B 22 C 2 = A 2 B + A 22 B 2 C 22 = A 2 B 2 + A 22 B 22 Blocked matrix multiply (bijk) for (jj=; jj<n; jj+=bsize) { for (i=; i<n; i++) for (j=jj; j < min(jj+bsize,n); j++) c[i][j] =.; for (kk=; kk<n; kk+=bsize) { for (i=; i<n; i++) { for (j=jj; j < min(jj+bsize,n); j++) { sum =. for (k=kk; k < min(kk+bsize,n); k++) { sum += a[i][k] * b[k][j]; c[i][j] += sum; 35 36
Blocked matrix multiply analysis Innermost loop pair multiplies a X bsize slier of A by a bsize X bsize block of B and accumulates into X bsize slier of C Loop oer i steps through n row sliers of A & C, using same B for (i=; i<n; i++) { for (j=jj; j < min(jj+bsize,n); j++) { sum =. for (k=kk; k < min(kk+bsize,n); k++) { sum += a[i][k] * b[k][j]; Innermost c[i][j] += sum; Loop Pair kk jj jj i row slier accessed bsize times block reused n times in succession 37 kk i Update successie elements of slier Pentium blocked matrix multiply performance Blocking (bijk and bikj) improes performance by a factor of two oer unblocked ersions (ijk and jik) Cycles/iteration relatiely insensitie to array size. 6 5 4 3 2 25 5 75 25 5 75 2 225 25 275 3 Array size (n) 38 325 35 375 4 kji jki kij ikj jik ijk bijk (bsize = 25) bikj (bsize = 25) Concluding obserations Programmer can optimize for cache performance How data structures are organized How data accessed Nested loop structure Blocking (see text) is a general technique All machines like cache friendly code Getting absolute optimum performance ery platform specific Cache sizes, line sizes, associatiities, etc. Can get most of the adane with generic code Keep working set reasonably small (temporal locality) Use small strides (spatial locality) 39