CISC 360. Cache Memories Exercises Dec 3, 2009

Transcription

1 Topics ν CISC 36 Cache Memories Exercises Dec 3, 29 Review of cache memory mapping

2 Cache Memories Cache memories are small, fast SRAM-based memories managed automatically in hardware. ν Hold frequently accessed blocks of main memory CPU looks first for data in L1, then in L2, then in main memory. Typical bus structure: CPU chip register file L1 ALU cache cache bus system bus memory bus L2 cache bus interface I/O bridge main memory 2 CISC 36, Fa9

3 Inserting an L1 Cache Between the CPU and Main Memory The transfer unit between the CPU register file and the cache is a 4-byte block. line line 1 The transfer unit between the cache and main memory is a 4-word block (16 bytes). block 1 block 21 block 3 a b c d... p q r s... w x y z... The tiny, very fast CPU register file has room for four 4-byte words. The small fast L1 cache has room for two 4-word blocks. The big slow main memory has room for many 4-word blocks. 3 CISC 36, Fa9

4 General Org of a Cache Memory Cache is an array of sets. 1 bit per line bits per line B = 2 b bytes per Each set contains one or more lines. set : 1 1 B 1 B 1 E lines per set Each line holds a block of data. 1 B 1 S = 2 s sets set 1: 1 B 1 1 B 1 set S-1: 1 B 1 Cache size: C = B x E x S data bytes 4 CISC 36, Fa9

5 Direct-Mapped Cache Simplest kind of cache Characterized by exactly one line per set. set : E=1 lines per set set 1: set S-1: 5 CISC 36, Fa9

6 Accessing Direct-Mapped Caches Set selection ν Use the set index bits to determine the set of interest. set : selected set set 1: m-1 t bits s bits 1 b bits set index block offset set S-1: 6 CISC 36, Fa9

7 Accessing Direct-Mapped Caches Line matching and word selection ν ν Line matching: Find a line in the selected set with a matching Word selection: Then extract the word =1? (1) The bit must be set selected set (i): w w 1 w 2 w 3 (2) The bits in the cache line must match the bits in the address m-1 =? t bits 11 s bits b bits i 1 set index block offset (3) If (1) and (2), then cache hit, and block offset selects starting byte. 7 CISC 36, Fa9

8 Practical Exercise 1 - Direct-Mapped M = 64 byte addresses B = 1 bytes/block S = 16 sets E = 1 entry/set Address trace (reads): 1 [ [ [1 2 5 [ [ [ [ [ [ [ [ [ [ [1 1 2 ] Assuming a direct-mapped cache initially empty Label each reference in the list as a hit or a miss Show the final content of the cache Valid Tag Memory bit block 8 CISC 36, Fa9

9 Practical Exercise 2 - Direct-Mapped M = 64 byte addresses, B = 4 bytes/block, S = 4 sets (direct assoc.) E = 1 entry/set Address trace (reads): 1 [ [ [1 2 5 [ [ [ [ [ [ [ [ [ [ [1 1 2 ] Assume a direct-mapped cache initially empty Label each reference in the list as a hit or a miss Show the final contents of the cache Valid Tag Memory bit block 9 CISC 36, Fa9

10 Set Associative Caches Characterized by more than one line per set set : E=2 lines per set set 1: set S-1: 1 CISC 36, Fa9

11 Accessing Set Associative Caches Set selection ν identical to direct-mapped cache set : Selected set set 1: m-1 t bits s bits 1 b bits set index block offset set S-1: 11 CISC 36, Fa9

12 Accessing Set Associative Caches Line matching and word selection ν must compare the in each line in the selected set. =1? (1) The bit must be set selected set (i): w w 1 w 2 w 3 (2) The bits in one of the cache lines must match the bits in the address m-1 =? t bits 11 s bits b bits i 1 set index block offset (3) If (1) and (2), then cache hit, and block offset selects starting byte. 12 CISC 36, Fa9

13 Practical Exercise 3-2-way Set Assoc. M = 64 byte addresses, B = 1 bytes/block, S = 8 sets, E = 2 entry/set Address trace (reads): 1 [ [ [1 2 5 [ [ [ [ [ [ [ [ [ [ [1 1 2 ] Assume a direct-mapped cache initially empty Assume LRU replacement Label each reference in the list as a hit or a miss Show the final contents of the cache Valid Tag Memory bit block 13 CISC 36, Fa9

14 Practical Exercise 4 - Fully Assoc. M = 64 byte addresses, B = 1 bytes/block, S = 1 sets, E = 16 entry/set Address trace (reads): 1 [ [ [1 2 5 [ [ [ [ [ [ [ [ [ [ [1 1 2 ] Assume a direct-mapped cache initially empty Assume LRU replacement Label each reference in the list as a hit or a miss Show the final contents of the cache Valid Tag Memory bit block 14 CISC 36, Fa9

15 Practical Exercise 5 - Fully Assoc. M = 64 byte addresses B = 4 bytes/block S = 1 sets E = 4 entry/set Address trace (reads): 1 [ [ [1 2 5 [ [ [ [ [ [ [ [ [ [ [1 1 2 ] Assume a direct-mapped cache initially empty Assume LRU replacement Label each reference in the list as a hit or a miss Show the final contents of the cache Valid Tag Memory bit block 15 CISC 36, Fa9