Counters and Timers: The 8051 microcontroller has two 16-bit timers/counters called T0 and T1. As their names suggest, timer counts internal clock pulse i.e. machine cycle to provide delay. Counter counts external clock pulse i.e to count external events. Besides, they can be used for generating clock pulses to be used in serial communication, so called Baud Rate. Each timer consists of two 8-bit registers THX and TLX representing a low and a high byte of one 16-digit binary number. (X is 0 or 1)
8051 Microcontroller Timer : It counts internal clock pulses to provide delay Two Timer named To and T1 Both are 16- bit (count 2 16 =65536 clock pulses) T0 8-bit TH0 8-bit TL0 TR0 Control bit TF0 Overflow flag bit T1 8-bit TH1 8-bit TL1 TR1 Control bit TF1 Overflow flag bit
XTAL Oscillator Divide by 12 C/T=0 THX TLX TFX Ext i/p C/T=1 TRX Gate INTX Timer/Counter control logic
TMOD Register (Timer Mode) Lower nibble is for To timer and higher nibble is for T1 timer. GATE bit: enables and disables Timer TX When GATE=0,Timer start and stop is controlled by software using timer control bit TR0 and TR1. When GATE=1 Timer start and stop is controlled by hardware using external signal at pin 12(INT0) and pin 13 (INT1). C/T: as timer or counter If set to 1 - Timer counts pulses brought to the T1 pin (P3.5). Simply it works as counter. If reset (0) - Timer counts pulses from internal oscillator. It work as timer. TM1,TM0: These two bits select the operational mode of the Timer. TM1 TM0 Mode Description 0 0 Mode0 13- bit 0 1 Mode 1 16- bit 1 0 Mode 2 8-bit auto reload 1 1 Mode 3 spilt mode
Timer Control (TCON) Register TFx: bit is automatically set on the Timer TX overflow. TRX: bit enables the Timer TX. If bit is 1 - Timer TX is enabled. If bit is 0 - Timer TX is disabled. IEX: External Interrupt flag bit: This bit is set to 1 when a high to low level edge signal is received on EXT INT pins. And start execution of Interrupt Service Routine (ISR). After complete execution ISR, this bit is cleared automatically and indicate interrupt is finished. EXT INT 1 : port 3 pin 3.3(13) EXT INT 0 : port 3 pin 3.2(12) ITX: External Interrupt control bit: There are two activation level external Interrupt as level triggered and edge triggered. This bit determines mode of activation. When ITX is 0 then external INTX is level triggered. When ITX is 1 then external INTX is edge triggered means for high to low transition.
Timer Mode 1 programming : In mode 1, timer is 16-bit It count 65536 internal clock pulses
Timer Mode 1 programming Steps: Select timer (T0 or T1) Set the value of TMOD register Initialize TH and TL register If Count same no of clock pulses Start timer by TRx bit End program Wait untill overflow occured (TFX=1) Stop timer and clear Overflow flag
Step 1: Select timer: To or T1 (we use both at time or only one) Step 2: Set the value of TMOD register: Suppose, we use T0 as Timer in mode 1 and start and stop by software. 0 0 0 0 0 0 0 1 TMOD value is 01H The instruction is: MOV TMOD, #01H MOV TMOD, #0000001B
Step 3: Initialize TH and TL register: e.g. If we want to count 921 clock pulses. In mode 1 timer is 16 bit so it count 65536 clock pulses. => 65536-921=64615 => Start counting from 64615 to 65536 ( total clock pulses are 921) => To load THX and TLX, convert 64615 in hex. => FC67 in Hex => TLX -> 67H => THX -> FC H The instruction are: MOV TH0, #0FCH MOV TL0, #67H
Step 4: Start timer start and stop by hardware or software. When GATE=1 Timer start and stop is controlled by hardware using external signal at pin 12(INT0) and pin 13 (INT1). When GATE=0,Timer start and stop is controlled by software using timer control bit TR0 and TR1. instruction is SETB TR0 or SETB TR1 Step 5: Wait untill overflow occured (TFX=1) When FFFF to 0000 transition occurred in TH and TL then overflow flag set. instruction is WAIT: JNB TF0, WAIT
Step 6: Stop timer and clear Overflow flag When timer is overflow, it is necessary to stop the timer. When timer is overflow, it is also necessary to clear the overflow flag, to start counting again. instruction CLR TR0 and CLR TF0
e.g. Write a program for timer1 (in mode 1) to generate a square wave of 500Hz on pin P1.2. Assume that XTAL=11.0592MHz. Timer clock freq.=xtal freq /12 =11.0592MHz/12 =921 KHz Period of Timer clock freq. =1/921KHz=1.085micro sec. Period of square wave T=1/500Hz=2ms T=Ton+Toff=2ms Ton=Toff=1ms (50% duty cycle) To generate Ton= Toff= 1ms., require 1ms time delay.
To generate 1ms time delay., require to count timer clock pluses(1.085 micro sec). but how many? Number of clock pulse to count= time delay / Period of Timer clock freq = 1ms/ 1.085microsec =921 That means timer count 921 clock pulses of 1.085microsec. For this load THx-TLx by (65536-921)=64615 which is in hexfc67
Program is as follow: ORG 8100H MOV TMOD,#10H ;TIMER 1 IN MODE1 AGAIN: MOV TL1, #67H MOV TH1.#0FCH SETB TR1 ; START TIMER 1 BACK: JNB TF1, BACK ; CHECK TF1 BIT SET CLR TR1 ; STOP TIMER 1 CPL P1.2 ; FOR TOFF GENERATION CLR TF1 ;CLEAR FLAG BIT SJMP AGAIN END
Timer Mode 2 programming : In mode 2, timer is 8-bit autoreload It count 256 internal clock pulses. Mode 1 is same as mode2, only difference is it does not need to initialization when to count clock pluses again (i.e in second cycle). Timer clock TLX TLX THX