Chapter C2051 Architecture and Serial Communication Link

Transcription

1 Chapter- 2 89C2051 Architecture and Serial Communication Link

2 ABSTRACT This chapter provides the details of 89C2051 microcontroller and description on Serial Communication Facility presented by 89C2051

3 2.1 Introduction to 89C2051 Microcontroller Atmel family 89C2051 is a CMOS 8 bit microcontroller. This device is software compatible with the 8051 microcontroller family. Atmel 89C2051 has on-chip 2kB flash programmable and erasable read only memory (PEROM). Flash memory is a nonvolatile memory, which can be electrically erased for lines and blocks. The mechanism for erasing the memory is easier and faster than that needed for EEPROM. There is no waiting time for erasing the program memory. Typically, 1000 write/erase cycles are possible, which are more than sufficient for any application development. It must be noted here that while developing new products, it is necessary to modify the program frequently and flash memory devices such as 89C2051 almost completely eliminate the erasing time. 89C2051 microcontroller has 128 byte of on-chip RAM organized as shown in Figure 2.1. The first 32 memory locations (00H-1FH) are defined as register banks (RB0-RB3). Each register bank contains eight registers (R0-R7). Selection of register bank can be done by setting bank select flags RSO and RSI in the Program Status Word (PSW) register. The figure drawn below shows the eight bits of PSW register. Carry Flag (CY) Auxiliary Carry (AC) User flag FO RSI Register Bank Select Bit 1 RSO Register Bank Select Bit 0 Overflow Reserved Parity PSW.7 PSW.6 PSW.5 PSW.4 PSW.3 PSW.2 PSW.l PSW.O The CPU registers and other registers together are called as special function registers (SFRs). It occupies the address range of 80H to FFH. The memory map of SFR is shown in Figure 2.2. The Stack Pointer (SP) is an 8-bit register. Up on Reset, the SP starts in Bank 1. The starting of stack can be changed by the Register Bank Select Bits. Further, stack must be built within the internal RAM, if not initialized within the register bank. 12

4 Development tools like assemblers and simulators meant for 8051 may also be used for 89C2051. The instruction set of 89C2051 is same as that of Intel's MCS-5I family microcontrollers. Another feature of 89C2051, which is also there in 8051 microcontrollers, is that they support fully static operation. The operating frequency of 89C2051 could be from 0Hz to 24MHz. Two software selected power saving modes are supported by these device. For applications where pin count is important, 20-pin devices such as 89C2051 and 89C1051 are suitable. 89C1051 has only one timer and lk PEROM whereas 89C2051 has two timers and 2K flash PEROM. Atmel 89C2051 block diagram is shown in Figure 2.3. The architecture has almost all the blocks, which are present in MCS-51. There is a 2 kilobytes on-chip flash program memory in 89C2051. Registers and memory organization are the same as that of the MCS-51 products. There are two 16 bit timer/counters (TO and Tl), one full duplex serial port (UART), and 128 bytes of on-chip RAM, 15 I/O lines (PORT 1, PORT 3); on-chip oscillator and clock circuitry. It supports six interrupt sources. The salient feature of 89C2051 is that it has on-chip analog comparator. Pin 3.6 is the output of the precision analog comparator. It must be noted that pin3.6 is not^available as I/O pin, i.e., P3.0 to P3.5 and P3.7 are available to the user. The architecture does not support any external address/data bus and therefore RD, WR signals are absent in 89C205I. Similarly, ALE, PSEN, EA signals are also not present in 89C2051. This IC also supports serial communication and six interrupt sources. In reality, only five interrupts are available to the user in the 89C2051. The six interrupts in the 89C2051 are given in the Table 1.4. Two power saving modes: Idle mode and Power down mode" are possible in 89C C2051 provide cost effective, compact and flexible solutions in many industrial applications. 13

5 FF FF Upper F Lower Accessible by Indirect Addressing Only Accessible by Accessible by Direct Addressing i 128 Direct and Indirect Special Function Registers 00 Addressing (SFRs) Figure 2.1(a). Internal Data Memory Map General Purpose 7FH RAM 30H 2FH 20H 1FH Bit-Addressable Space Register Bank 3 Register Bank 2 Register Bank 00H Register Bank 0 Figure 2.1(b). The Lower 128 bytes of Internal RAM 14

6 Address Addres s F8 FF FO B F7 E8 EF EO ACC E7 D8 DF DO PSW D7 C8 CF CO C7 B8 IP BF BO P3 B7 A8 IE AF AO P2 A7 98 SCON SBUF 9F 90 PI TCON TMOD TLO TL1 THO TH1 8F 80 PO SP DPL DPH PCON 87 Figure 2.2 SFR Memory Map 15

7 2.2 Pin Description Atmel 89C2051 is a 20-pin device. Figure 2.4 shows the pin configuration of 89C2051. It has 15 digital I/O lines. In 89C2051, P3.6 is not seen externally. It is the output of a precision analog comparator and accessible through software. 89C2051 have two 16-bit timers. It must be noted that there is no external address/data bus, in 89C2051. There, no external memory connections are possible. Only Portl (PI.0...PI.7) and Port3 (P3.0...P3.7 except P 3.6) functions are available in 89C2051 as seen in Figure 2.4. The connections for external crystal and reset circuit for 89C2051 are same as that of MCS-51. The block diagram showing the external crystal connection and RESET button is shown in the discussion of interrupt feature (RESET). 2.3 Interrupt Features: Interrupts play a key role in the application of the microcontroller. The 89C2051 microcontroller supports six interrupts. Out of these six interrupts, five are available to the user. These are: * RESET */INT0 */!NTl *TF0 *TF1 *RI+T1 In the order of priority, the sequence is as follows: /INTO > TFO > /INTI > TF1 > RI (or) TI The interrupt polling is done by the internal hardware. When the microcontroller finds two interrupts with different priorities, higher priority interrupt is serviced first and then the lower one. Interrupt events set interrupt flags of the microcontroller. These set flags are sampled during the S5 state of the machine cycle. A brief description on these interrupts is as follows: 16

8 RESET Pin 1 of 89C2051 is RESET. When this pin is activated, the control jumps to the memory location 0000H. This condition is also known as Power-On-Reset. In order to make the RESET input to be effective, it must be high for a minimum duration of 2 machine cycles before the signal goes to low. The standard RESET signal is obtained by the following connection. The vector memory location for Timer 0 is 000BH. The bit ETO (IE.I) of Interrupt Enable register must be set to enable the Timer 0 interrupt. This is accomplished by the software instruction: SETB IE.l. The timer flag (TFO) is raised when the timer rolls over, and the control is transferred to 000BH. This interrupt is useful in the generation of square wave, frequency measurement etc. TIMER 1 INTERRUPT (TF1) The vector memory location for Timer 1 is 001BH. The bit ET1 (IE.3) of Interrupt Enable register must be set to enable the Timer 1 interrupt. This is accomplished by the software instruction: SETB IE.3. The timer flag (TF1) is raised when the timer rolls over, and the control is transferred to 001BH. This interrupt is also useful in the generation of square wave, frequency measurement etc. 17

9 EXTERNAL INTERRUPT INTO Pin 6 (P3.2) of 89C2051 works as the input for the external interrupt INTO. The bit IE.O facilitates to enable (SETB 1E.0) or disable (CLR IE.O) this interrupt. This is designated as EXO in the Interrupt Enable (IE) register. This interrupt can be activated either by level triggered or edge triggered. The default mode of activating this interrupt is level triggered, in which this pin will be normally 'Hr. and activated by a LO' level signal. To make the interrupt to respond to the edge of the trigger input, the TCON register must be programmed such that TCON.O must be HE. This can be done in the software by using the instruction: SETB TCON.O. A HI to LO transition will trigger the input. When this interrupt is enabled, the control is transferred to address location: 0003H. EXTERNAL INTERRUPT INTI Pin 7 (P3.3) of 89C2051 works as the input for the external interrupt INTI. The bit IE.2 facilitates to enable (SETB IE.2) or disable (CLR 1E.2) this interrupt. This is designated as EX1 in the Interrupt Enable (IE) register. This interrupt can be activated either by level triggered or edge triggered. The default mode of activating this interrupt is level triggered, in which this pin will be normally 'HE. and activated by a LO level signal. To make the interrupt to respond to the edge of the trigger input, the TCON register must be programmed such that TCON.2 must be HE. This can be done in the software by using the instruction: SETB TCON.2. A HI to LO transition will trigger the input. When this interrupt is enabled, the control is transferred to address location: 0013H. SERIAL COMMUNICATION INTERRUPT (RI or TI) In 89C2051 microcontroller there is only one interrupt set aside for serial communication. This interrupt is used to both send and receive data. This interrupt is active only when the bit IE.4 in the IE register is set. This can be 18

10 done by the instruction; SETB IE.4, In the majority of the cases, this interrupt is used during receiving the data from a peripheral. The internal arrangement is as shown below: RI Tr.0023 H RI+TI At the activation of RI or TI, the control jumps to the memory location: 0023H. It is essential to note that the RI or TI has to be cleared before leaving the interrupt routine by the RETI instruction. This can be accomplished in software by using either CLR TI or CLR RI instruction. The interrupt vector table for 89C2051 is shown in Table 2.1. As the present work focuses on the exploitation of serial communication using 89C2051, a brief description of serial communication is presented. 19

11 Table 2.1 Interrupt Vector Table for the 89C2051 Interrupt ROM Location (Hex) Pin Flag Clearing Reset Auto External hardware interrupt 0 (INTO) 0003 P3.2 (6) Auto Timer 0 interrupt (TO) 000B P3,4(8) Auto External hardware interrupt 1 (INTI) 0013 P3.3 (7) Auto Timer 1 interrupt (Tl) 001B P3.5(9) Auto Serial COM interrupt (RI and TI) 0023 Programmer clears it 20

12 2.4 Serial Communication Facilities (i). Serial Communication Presented By 89C2051 Serial data transmission is very commonly used for digital data communication. Its main advantage is that the number of wires needed for transmission/reception is reduced as compared to that of parallel communication. 89C2051 supports a full duplex serial port. Full duplex means, it can transmit and receive a byte simultaneously. 89C2051 has TXD and RXD pins for transmission and reception of serial data respectively. The 89C2051 serial communication lines can be made RS232 compatible by interfacing with MAX232. The term RS stands for Recommended Standard. In serial transmission, baud rate is one important factor. The baud rate is the reciprocal of the time to send 1 bit. Baud rate need not be equal to number of bits per second. This is because; each byte is preceded by a start bit and followed by one stop bit. The start and stop bits are used to synchronize the serial receivers. The data byte is always transmitted with least significant bit first. For error checking purpose, it is possible to include a parity bit as well, just prior to the stop bit. Thus, the bits are transmitted at specific time intervals determined by the baud rate. For error-free serial communication, it is necessary that the baud rate, the number of data bits, the number of stop bits, and the presence or absence of a parity bit along with its status is the same at the transmitter and receiver ends. The serial data stream format is shown below: Oil i 2 i 3 i4 i 5 6 t 7 1 Start bit 0 data bits The basic mechanism of serial transmission is that a data byte in parallel form is converted into serial data stream. As shown above, some more bits like start stop and parity bits are also sent along with eight data bits. This forms a data frame that is sent on 21

13 the transmission line. In order to establish serial communication link between 89C2051 and any other device the internal special function register called SCON (Serial CONtrol) is used. Brief explanation of this register is given below. SCON REGISTER: It is an 8-bit register having address: 98H, and is bit addressable. Different bits of the SCON register is shown below: D7 D6 D5 D4 D3 D2 D1 DO i i it i i + SMO SMI SM2 REN TBS RB8 TI RI SCON Register In the above register, bits: D7 and D6 determines the mode of operation, D5 is used to select uni/multi-processor environment (0/1), when D4 (Receive ENable, SCON.4) bit is set (SETB SCON.4), the controller receives data on RXD pin. Further when this bit is HI, the controller receives and transmits data. On the other hand if D4 bit (SCON.4) is LO (CLR SCON.4), the receiver is disabled. The D3 bit of SCON register is TB8 (Transfer Bit8). This bit is used in modes 2 and 3 of serial mode transmission. This bit is set to zero in the present application. The D2 bit of the SCON register is RB8 (Receive Bit 8). In mode 1, this bit gets a copy of the stop bit when data is received. The bit Di is an important flag called Transmit Interrupt (TI). When the controller transmits an 8-bit data, this flag goes HI (i.e., at the beginning of the stop bit) indicating that it is ready to send another byte. The least significant bit (DO) of SCON register is RI (Receive Interrupt), This bit when goes to HI, indicates that a byte is framed and placed in SBUF register. The controller removes the start and stop bits from the received data stream. The RI bit rises halfway through the received stop bit. Different modes of serial communication using 89C2051 are briefly explained in the following Table 2.2. Baud rate selection in the 89C2051: The 89C2051 transfers and receives data serially at different baud rates. The baud rate in the 89C2051 is programmable. This is done with the help of timer I (TI). It is 22

14 important to note that the baud rate depends on the crystal frequency of the microcontroller. Further, the serial data transmission is accomplished using the on-chip UART. The clock frequency supplied to the UART is equal to the crystal frequency divided by 12. To Timerl to set the baud rate * khz As mentioned in the architecture of 89C2051, there are two on-chip 16-bit timers TO and Tl. Out of these two timers, T1 is used for baud rate selection in serial programming. / Timer 1 register is shown below; D15 D14 D13 D12 Dll DIO D9 D8 D7 D6 D5 D4 D3 D2 D1 DO TH1 TL1 Selection of the working mode of timers is accomplished using the SFR TMOD (Timer MODe) register. A brief description of the TMOD register is given below; D7 D6 D5 D4 D3 D2 D1 DO GATE C/T Ml MO GATE C/T Ml MO M TIMER 1 TIMER 0 In the above TMOD register DO to D3 are similar to D4 to D7 in functionality, excepting that they belong to two different timers (TO, Tl respectively). The lower two bits of the each nibble are used to select the timer mode. The various timer modes are given in Table 2.3. When timer 1 is used to set the baud rate, it must be programmed in mode 2 that is 8-bit, auto-reload. To get baud rates compatible with the PC, we must load TH1 with the values as shown Table 2.4. The bit D7 (D3) selects gating control for timer 1 (timer 0). These bits are useful to enable/disable the timers by hardware means. 23

15 (i). If the GATE bit (D7/D3) is LO the timers are enabled under software control by TR0/TR1. (ii). If the GATE bit (D7/D3) is HI, then the timer(s) can be enabled/disabled by means of hardware using INTO/INTI pin. The following diagram clarifies this. The Timer 1 in Mode 2 configuration for serial programming is shown below: C/T =0 TR TF goes HI when The contents of TL1 Goes from FF to 00 (Overflows) 24

16 Table 2.2 Mode Selection in SCON Register SMO SMI Description 0 0 Serial Mode 0, 8-bit data, no start and start bits 0 1 Serial Mode 1, 8-bit data, 1 stop bit, 1 start it 1 0 Serial Mode Serial Mode 3 Table 2.3 Mode Selection for Timer/Counter in TMOD Register Ml MO Mode Description bit timer mode, 8-bit timer/counter THx with TLx as 5-bit Prescaler bit timer mode, 16-bit timer/counter THx and TLx are cascaded bit Auto Reload, 8-bit Auto Reload Timer/Counter THx----- TLx Split timer Mode Table 2.4 Baud Rates Compatible to PC Baud Rate TH1 (Decimal) TH1 (Hex) FD FA F E8 25

17 SBUF register: SBUF is one of the special function 8-bit register (SFR) used solely for serial communication. For a byte of data to be transferred via the TXD line (pin 3), it must be placed in the SBUF register. Similarly, SBUF holds the byte of data when it is received by the 805l s RXD line (pin 2). Like any other registers SBUF can be accessed by means of an instruction. The moment a byte is written into SBUF, it is framed with the start and stops bits and transferred serially via the TXD pin. Similarly, when the bits are received serially on RXD line, the 89C2051 frames it in to a byte by eliminating the start and stop bits, and then places it in the SBUF register. In the present work, the SCON register is used in Mode 1, which is a popular mode. A brief description on the serial programming in Mode 1 is as follows: Mode 1: In mode 1, ten bits are transmitted through TXD pin or received through RXD pin. There is a start bit (0) followed by 8 data bits (LSB first) and a stop bit (1). The figure shown below illustrates the serial transmission of ten bits in Mode 1. Stop bit 1 MSB T] LSB Start bit 0 On receiving a byte, the stop bit goes into RB8 of SCON register. The baud rate is variable and is determined by the timer 1 overflow rate. Therefore, before using this mode, one has to initialize timer 1. The baud rate is calculated using the formula: Baud rate = 2SMOD/32x (Timer 1 overflow rate) In the above equation, SMOD is the D7th bit of the power control register: PCON. This is an SFR (87H). This register is not bit addressable and normally is used to double the baud rate of the microcontroller when the crystal frequency is fixed one. On reset, the SMOD bit of PCON register receives a LO logic (2SMOD=2 =l). By setting this bit 26

18 through software, one can double the baud rate (2SMOD =2'=2, observe the above formula). (ii) Serial Link Between 89C2051 and PC The IBM PCs/compatible computers are so widely used to communicate with microcomputer-based systems [1]. A brief description on serial communication of the 89C2051 with the COM port of the PC is given below. To allow data transfer between the PC and 89C2051 microcontroller without any error, it is important to make sure that the baud rate of the 89C2051 system matches with that of the PC s COM port. The baud rates supported by PC BIOS are shown below: 110; 150; 300; 600; 1200; 2400; 4800; 9600; Going to the Windows terminal program (HyperTerminai) and clicking on the communications setting option can alter the baud rate presented by the PC. Hyper terminal supports baud rates much higher than the above mentioned ones. RS232 Standard The Figure 2.3 shows the RS232 standard voltages that will be met with MAX 232. In order to meet with the above requirements in establishing a serial link between 89C2051 and PC, MAX232 has to be interfaced with the PC. On the PC side, the 9-pin connector (DB-9) is used to establish the link. Figure 2.4 shows the DB-9 pin connector. The pin assignment of the DB-9 connector is given in Table 2.5. In the present work only data is transmitted from the microcontroller to the PC. Hence null modem connections shown in Figure 2.4 are made between 89C2051 and IBM compatible PC via MAX

19 Figure 2.4 Photograph of the DB-9 Connector

20 MAX232: Microprocessors/Microcontrollers are interfaced with PC/audio cassettes for data storage using RS232 standard [2]. In order to establish the bus compatibility in interfacing PCs with today s microprocessors and microcontrollers, we need a line driver (voltage converter) to convert the RS232 signals to TTL voltage levels and vice versa. That will be acceptable to the 89C2051 s TXD and RXD pins. One example of such a converter is MAX232 from Maxim Corporation [3], The MAX232 converts RS232 voltage levels to TTL voltage levels and vice-versa. One advantage of the MAX232 chip is that it uses a single +5V power source, which is the same as the source voltage for the 89C2051. In other words with a single +5V power supply we can power both the 89C2051 and MAX232, with no need for the dual power supplies. The MAX232 has two sets of line drivers for transferring and receiving data, as shown in the Figure 2.5. The line drivers used for TXD are called T1 and T2. While the line drivers for RXD are designated as R1 and R2. In many applications only one of each is used. For example, T1 and R1 are used together for TXD and RXD of the 8051, and the second set is left unused. In MAX232 the T1 line driver has a designation of T1IN and TIOUT on pin numbers 11 and 14, respectively. The T1 IN pin is the TTL side and is connected to TXD of the microcontroller, while TIOUT is the RS232 side that is connected to the RXD pin of the RS232 DB-9 connector. The RI line driver has a designation of RUN and RIOUT on pin numbers 13 and 12, respectively. The RUN (pin 13) is the RS232 side that is connected to the TXD pin of the RS232 DB-9 connector and RIOUT (pin 12) is the TTL side that is connected to the RXD pin of the microcontroller. MAX232 requires four capacitors ranging from 1 to 22 pf. The most widely used value for these capacitors is 22 pf. Standard RS232 cables are available on the market is used. Troubleshooting of this cable during communication between two devices can be accomplished easily [4], 29

21 +V TRANSMIT RECEIVE ii Space(0) Space(0) +5 Noise Margin Invalid +3 Transition Output -3 Region -5 Mark (1) -15 Mark (1) -V -25 Figure 2.3.Voltage Levels of RS232 Standard 30

22 Table 2.5 Pin Assignments of DB-9 Connector Pin No. of the DB9 Function Connector 1 Data Carrier Detect (DCD) 2 Received Data (RXD) 3 Transmitted Data (TXD) 4 Data Terminal Ready (DTR) 5 Signal Ground (GND) 6 Data Set Ready (DSR) 7 Request To Send (RTS) 8 Clear To Send (CTS) 9 Ring Indicator (Rl)

23 Figure 2.4 Null Modem Connections between 89C2051 and PC Figure 2.5 MAX232 Pin Configuration 32

24 (iii) Serial Communication Programming The steps to transmit and receive data byte serially on TXD and RXD lines, respectively are given below: Steps involved in transferring data serially on TXD line: Load TMOD register with 20H in order to set the baud rate, using timer 1 in Mode 2. Load TH1 with an 8-bit hex value depending on the baud rate. Load SCON register with 50H indicating serial transmission in Mode 1. Start timer 1 by making TR1 bit HI (TR 1 = 1) Clear TI bit in SCON register in order to know the transmission of a byte (T1 bit goes HI when a byte of data is transferred) Load SBUF register with data byte to be transmitted a Check TI flag for a HI logic in order to ensure a byte transmission. If further data bytes are to be transmitted, the program can go back to the fifth step. Steps involved in receiving data serially on RXD line: Load TMOD register with 20H in order to set the baud rate, using timer 1 in Mode 2. Load TH1 with an 8-bit hex value depending on the baud rate. Load SCON register with 50H indicating serial transmission in Mode 1. Start timer 1 by making TR1 bit HI (TR 1=1) Clear RI bit in SCON register in order to know whether a byte of data is received (RI bit goes HI when a byte of data is received) Check RI flag for a HI logic in order to ensure a byte reception As the received byte is framed in SBUF register, it can be saved in memory If further data bytes are to be received, the program can go back to the fifth step. Conclusion: This chapter in essence deals with the description of the microcontroller used in the present work and the serial communication features to interface 89C2051 with an IBM compatible PC. 33

25 REFERENCES: 1. W.A. Stapleton, 36th ASEE/IEEE Frontiers in Education Conference, P.J. Robertson and B. Campbell, Journal of Microcomputer Applications, Vol.8. PP , D.M. Vaidya, Microprocessors and Microsystems, Vol.9. No.5, PP , June