Using the Z8051 MCU s USI Peripheral as an SPI Interface

Using the Z8051 MCU s USI Peripheral as an SPI Interface AN035901-0513 Abstract This document describes how to configure Zilog s Z8051 Universal Serial Interface (USI) peripheral to operate as Serial Peripheral Interface (SPI). This application will demonstrate the SPI protocol by using two of Zilog s Z51F3220 MCUs configured as master and slave, respectively. Note: The source code file associated with this application note, AN0359-SC01.zip, is available free for download from the Zilog website. This source code was compiled using the Keil µvision4 and Small Device C Compiler (SDCC) v 3.1.0 tools. The Keil µvision4 development tool is available from Keil; the SDCC v3.1.0 tool is included in the Z8F3220 Development Kit. For this source code to work properly with other Z8051 MCUs, minor modifications to the source code may be required. An Overview of USI and SPI The Universal Serial Interface (USI) peripheral unit in Zilog s Z8051 family of MCUs provides the necessary hardware resources required for synchronous, asynchronous, and two-wire serial communication. Compared to other software-based serial communication solutions, Zilog s USI uses less code space and expedites higher transfer rates. In this application, this USI will be configured to work as a Serial Peripheral Interface (SPI). A Serial Peripheral Interface (SPI) is a hardware/firmware communications protocol originally developed by Motorola and later adopted by other industry companies. An SPI is also called a four wire serial bus. In effect, an SPI is a serial bus that operates in full duplex mode. Devices communicate using a master/slave relationship in which the master initiates a data frame. When the master generates a clock and selects a slave device, data may be transferred in either or both directions simultaneously, and can support transfer rates of 1 to 10 Mbps. Discussion The Z8051 USI peripheral, when correctly configured, can operate efficiently in Serial Peripheral Interface Mode. This section discusses the SPI signals, data transfer, and other details that are related to the SPI. Signals The SPI consists of the following four signals: AN035901-0513 Page 1 of 17

Master Out Slave In (MOSI). The MOSI signal is generated by the master, and the recipient is the slave. Master In Slave Out (MISO). Slaves generate MISO signals; the master is the recipient. Serial Clock (SCK). The SCK signal is generated by the master to synchronize data transfers between the master and the slave. Slave Select (SS). An SS signal is generated by the master to select individual slave/ peripheral devices. The SS or CS is an active Low signal. Data Transmission Communication is initiated by the master in all instances. The master first configures the clock, using a frequency that is less than or equal to the maximum frequency that the slave device supports. Such frequencies are commonly in the range of 1 100 MHz. The master then selects the appropriate slave for communication by pulling the chip select (SS) line of that particular slave-peripheral to a Low state. The master will next issue clock cycles. The slaves on the bus that has not been activated by the master using its slave select signal will disregard the input clock and MOSI signals from the master, and must not drive MISO. In essence, the master selects only one slave at a time. During each SPI clock cycle, a full duplex data transmission occurs; i.e., communication in both directions occurs simultaneously. Data are usually shifted out with the MSB first while shifting a new LSB into the same register. After this register has been shifted out, the master and slave will complete an exchange of their register values. If there are more data to be exchanged, the shift registers are loaded with new data and the process is repeated. When there are no more data to be transmitted, the master stops its clock and rejects any slave data. Baud Rate The USI s clock generation logic generates a clock for the Serial Peripheral Interface. Writing to the USIxBD Register sets this SPI clock. The following formula can be used to obtain a correct value for the baud rate register: USIxBD = (System Clock / ((Baud Rate * 2)) 1 Clock Polarity and Phase In addition to setting the clock frequency, the master must also configure the clock polarity (CPOL) and clock phase (CPHA) with respect to the data. Because the clock serves to synchronize data communication, there are four possible modes that can be used in an SPI protocol based on CPOL and CPHA. Table 1 lists these four CPOL and CPHA combinations for an SPI. AN035901-0513 Page 2 of 17

Table 1. Combinations of CPOL and CPHA SPI Mode CPOL CPHA Leading Edge Trailing Edge 0 0 0 Sample (Rising) Setup (Falling) 1 0 1 Setup (Rising) Sample (Falling) 2 1 0 Sample (Falling) Setup (Rising) 3 1 1 Setup (Falling) Sample (Rising) From Table 1, it can be determined that when CPOL = 0, the base value of the clock is zero. When CPHA = 0, data is sampled at the rising edge of the clock and propagated on a falling edge. For CPHA = 1, data is sampled on the clock s falling edge and propagated on the rising edge. When CPOL = 1, the base value of the clock is one. When CPHA = 0, data is sampled at the falling edge of the clock and propagated on a rising edge. When CPHA = 1, data is sampled on the clock s rising edge and propagated on a falling edge. This scenario is depicted in the SPI timing diagram shown in Figure 1. Figure 1. Timing Diagram Showing CPOL and CPHA AN035901-0513 Page 3 of 17

USI Registers USI Register USIxBD USIxDR Six registers are important for allowing the USI block to operate as a serial peripheral interface; these registers are briefly described in Table 2. Table 2. USI Registers Related to the SPI Block Description USI Baud Rate Generation Register The value of this register is used to generate the clock for the SPI. USI Data Register SPI data are written to this register. USIxCR1 USI Control Register 1 Controls or changes the behavior of USI. USIxCR2 USI Control Register 2 Configuring this register will enable or disable the TX, RX and USI. USIxCR3 USI Control Register 3 Configuring this register will set the SPI as master or slave. USIxSTI USI Status Register 1 Operation status of the SPI can be determined by reading this register. Hardware Implementation In this application, two Z51F3220 microcontrollers are configured; one as a master, and one as a slave. Figure 2 illustrates the connection interface between the master and the slave. Figure 2. Master and Slave SPI Interface Software Implementation The software for this application can be compiled using either Keil µvision v4.53.0.6 or SDCC v3.1.0. The source code file that is important in this application is the spi.c file, which contains the routines required to allow the SPI peripheral of the Z8051 MCU to operate. AN035901-0513 Page 4 of 17

SPI Macros The source code for this application is written with macros which act as switches that enable the application software to control either an SPI master or an SPI slave. These macros also determine which USI (0 or 1) will be used as the SPI during compilation. These switches can be found in the spi.h file along with the function prototypes of the routines. Examples of the SPI switches are: #define MASTER #define SPI0 // #define SPI1 The above macro examples indicate that USI0 will be used to operate as an SPI master. SPI Routines The SPI routines are contained in the spi.c file, and are used both for SPI master and SPI slave configuration. Table 3 lists all of the routines included in this file. Table 3. SPI Routines Function Name VOID Spi_Initialize( UINT32 ulfrequency, UINT32 ulbaudrate, UINT8 ucdataorder, UINT8 ucmode) VOID Spi_Putchar(INT8 cdata) INT8 Spi_GetChar(VOID) Description This routine initializes the USI function to operate in SPI Mode. It calculates the operating baud rate, sets the data order, and also sets CPOL and CPHA. Puts a character to the SPI Data Register. Gets the data from the SPI Data Register. SPI Initialization To set the USI block to function as an SPI, it must first be properly initialized. The SPI_Initialize routine is used in this application to set the USI to operate in SPI Mode. Additionally, this routine can be used by either the master or slave MCU configuration. Setting SPI Mode The SPI_Initialize routine starts by setting the USI to SPI Mode. The following code statement shows how to set the USI to work in SPI Mode. SPICR1 = SPI_MODE; // Set Control Register 1 to make the USI // work as an SPI. This code shows that SPICR1 is set equal to the value represented by SPI_MODE. SPICR1 is an identifier for the USI Control Register 1 (USIxCR1). Please refer to spi.h file to view additional identifiers. AN035901-0513 Page 5 of 17

Master/Slave Configuration After setting the USI to work as an SPI, the routine will configure the SPI to either a master or a slave by setting the MASTER1 bit of the USI Control Register 3 (USIxCR3). Table 4 lists the configuration of the SPI depending on this MASTER1 bit value. Table 4. USI Control Register 3 Bit 7 Setting USIxCR3 Bit 7 (MASTER1) Configuration SPI 0 Slave 1 Master Table 4 shows that setting the MASTER1 bit to 0 sets the MCU to function as an SPI slave; setting this bit to 1 sets the MCU to function as an SPI master. The routine next configures the Slave Select (SS) pin of the MCU to either input or output. If the MCU is set to work as a master, the SS pin is configured as an output. However, if the MCU is set to work as a slave, SS is configured as an input. The following code segment shows how the MCU is configured to either master or slave, and how the SS pin is configured. #ifdef MASTER // Configure MCU as master SPICR3 = MASTER; #ifdef SPI0 P4IO = (1<<3); #ifdef SPI1 P2IO = (1<<2); SS_HIGH; #else // Configure MCU as slave #ifdef SPI0 P4IO &= ~(1<<3); #ifdef SPI1 P2IO &= ~(1<<2); SPICR3 &= ~ (MASTER); SPICR3 = USISSEN; // Set SPI as master // If USI0/SPI0 is used // Set SS0 pin as Output // If USI1/SPI1 is used // Set SS1 pin as Output // Set SS to High // If USI0/SPI0 is used // Set SS0 pin as Input // If USI1/SPI1 is used // Set SS1 pin as Input // Set SPI as slave // Enable SS pin AN035901-0513 Page 6 of 17

Setting the GPIO Alternate Function The routine next enables the alternate functions of the GPIO pins used for SPI. The following code segment sets these alternate functions. // Set GPIO Alternate function for SPI. #ifdef SPI0 P4FSR = ((1<<5) (1<<3) (1<<1)); #ifdef SPI1 P1FSRL = ((1<<1) (1<<0)); P2FSRL = ((1<<3) (1<<2) (1<<1) (1<<0)); For this application, the user can choose between USI0 and USI1 as the SPI. For SPI0, bits 5, 3, and 1 of the Port 4 Function Select Register are set to 1 to enable SCK0, MOSI0, and MISO0 of the SPI0. For SPI1, bits 0 and 1 of the Port 1 Function Select Low Register are set to 1, and bits 0, 1, 2, and 3 of the Port 2 Function Select Low Register are also set to 1; these bit configurations enable SCK1, MOSI1 and MISO1 of the SPI1. Setting the Baud Rate The routine then sets the serial clock for this application, as indicated in the following line of code. SPIBD = ((ulfrequency / (ulbaudrate * 2)) - 1 The ulfrequency and ulbaudrate parameters are used to calculate the baud rate value for the USI Baud Rate Register (USIxBD). Setting the Data Transmission Sequence After setting the clock, the routine selects the data transmission sequence to either MSB first or LSB first. As shown in the following code segment, configuring bit 2 of the USI Control Register 1 (USIxCR1) determines which data transmission sequence will be used. if (ucdataorder == MSB_FIRST) // Data Transfer { SPICR1 = ORD; // MSB First data transfer else SPICR1 &= ~ (ORD); // LSB First data transfer Setting USIxCR1 Bit 2 to 0 will set the transmission sequence of the SPI to LSB first. Conversely, setting this bit to 1 sets the transmission sequence to MSB first. AN035901-0513 Page 7 of 17

Setting SPI Clock Polarity and Phase The routine continues by setting the Clock Polarity (CPOL) and Clock Phase (CPHA), configuring bits 0 and 1, respectively, of USI Control Register 1. The following code segment sets the CPOL and CPHA. // Set SPI Operation Mode Leading Edge, Trailing Edge if (ucmode == MODE0) { SPICR1 &= ~(CPHA CPOL); // Sample Rising, Setup Falling else if (ucmode == MODE1) { SPICR1 = CPHA; // Setup Rising, Sample Falling else if (ucmode == MODE2) { SPICR1 = CPOL; // Sample Falling, Setup Rising else if (ucmode == MODE3) { SPICR1 = (CPHA CPOL); // Setup Falling, Sample Rising else { // else Do nothing CPOL determines the serial clock s value during Idle Mode, while CPHA determines if data are sampled on the leading or trailing edge of the serial clock. Enabling the USI, MISO and MOSI The final part of the routine enables the MOSI and MISO lines as well as the USI, as shown in the following line of code. SPICR2 = (TXE RXE USIEN); // Enable TX (MOSI) RX (MISO) and USI SPI Data Transmission In SPI, data is being transmitted by the master thru the MOSI line, while for the slave; the MISO line is used for data transmission. The brief routine that follows shows the transmission of data on SPI. VOID Spi_PutChar (INT8 cdata) { ucdelay = 35; #ifdef MASTER SS_LOW; #else while (SS_IN_HIGH); // Pull Slave Select pin Low // Wait for the master to pull the AN035901-0513 Page 8 of 17

while (! (SPIST1 & DRE)); SPIDR = cdata; while (! (SPIST1 & TXC)); #ifdef MASTER while (--ucdelay); SS_HIGH; // putchar // SS pin Low // Check status reg if TX data reg // is empty // Send Byte // Check TX data reg is empty and // all data are // already shifted out // Allow all data to be shifted // Pull Slave Select pin High If the MCU is the master, the routine starts by pulling the SS line Low. However, if the MCU is the slave, the routine will start by waiting for the SS line to be pulled Low. Then, the routine will check if the transmit register of the USI is empty, and if it is empty, the routine will put 8 bits of data to the transmit register before pulling the SS line back to High. SPI Data Reception In SPI, data is being received by the master thru the MISO line, while for the slave, the MOSI line is used for data reception. The routine that follows shows the sequence for receiving data on SPI. INT8 Spi_GetChar(VOID) { INT8 cdata; // First Clean the RX Buffers while (((SPIST1 & DOR) == DOR) ((SPIST1 & RXC)==RXC)) { cdata = SPIDR; #ifdef MASTER Spi_PutChar(DUMMY); #else while(ss_in_high); // Send FFh as dummy byte // Wait for Slave Select Pin while ((SPIST1 & RXC)!= RXC); // Check if Data Register has data cdata = SPIDR; // Read Data Register return (cdata); AN035901-0513 Page 9 of 17

Equipment Used The routine starts by clearing the receive buffer of the USI to ensure that no irrelevant data will be processed. If the MCU is the master, the routine will send a dummy byte (0xFF) to the MOSI line to provide a clock pulse to the slave. However, if the MCU is the slave, the routine will wait for the SS line to be pulled Low. The routine will then continuously check to determine if the USI Data Register is not empty. If this register contains data, the routine will read the USI Data Register. This read data will be the return data. This section lists all hardware and software requirements for this application. Hardware Table 5 lists the hardware tools used in this application. Table 5. Required Hardware Description Quantity Z51F3220 Development Kit 2 PC with two available USB ports 1 Connecting wires 6 Software The software tools used to develop this application are: Keil µvision 4 SDCC v 3.1.0 AN0359-SC01.zip source code file containing the project and source code files for this application HyperTerminal or equivalent communications/terminal emulation program Testing Setup and Procedure This section discusses the steps for setting up this application and testing the software. Hardware Setup Observe the following procedure to prepare the hardware for this application. See Figure 3 for reference. AN035901-0513 Page 10 of 17

Figure 3. Master MCU and Slave MCU Connections 1. Identify which Development Board will be the master and which one will be the slave. 2. Using connecting wires, connect the data and control lines of the master to the slave. There should be five wires running between the master and the slave, as indicated in Figure 3. 3. Connect the master MISO0 (J3 pin 2) to the slave MISO0 (J3 pin 2). 4. Connect the master MOSI0 (J3 pin 3) to the slave MOSI0 (J3 pin 3). 5. Connect the master SCK0 (J3 pin 4) to the slave SCK0 (J3 pin 4). 6. Connect the master SS0 (J3 pin 5) to the slave SS0 (J3 pin 5). 7. Connect the GND (J13) of the master to the GND (J13) of the slave. 8. Check to determine that the jumpers for J16 pins 5 6 and 7 8 on both the master and slave are in place. 9. Connect the Z8051 On-Chip Debugger (OCD) to the host PC s USB port. AN035901-0513 Page 11 of 17

10. Connect one end of the 10-circuit cable to the Z8051 OCD. 11. Connect the other end of the 10-circuit cable connector to the Z51F3220 Board s J1 connector. Pin 1 of the cable connector is indicated by the a red stripe. 12. Using the USB-to-USB Mini cable, connect the standard USB end to the host PC's USB port. 13. Connect the other end of this USB-to-USB Mini cable to the Z51F3220 Board's P1 connector to apply power to the board. Note that the LED D5 is ON. Software Configuration To install, configure and test the software for this application, observe the following procedure. 1. Download and install the Z8051 Software and Documentation files if you haven t already done so. These files are available free for download from the Downloadable Software category of the Zilog Store. 2. After the Z8051 software is installed, download the AN0359-SC01.zip file from the Zilog website and unzip it into the following path, which was created during the installation process in Step 1: <Z8051 software installation folder>\samples Note: In the above paths, <Z8051 software installation folder>\samples represents the location of the unzipped AN0359-SC01 file. 3. Open the spi.h file, which is located in the <inc> folder. If the MCU will be the master, ensure that the MASTER macro switch is defined. However, if the MCU will be the slave, comment out the MASTER macro, then save the file. Zilog recommends configuring the master first. 4. The software created for this application is designed in a manner such that the source code must be compiled using either the Keil µvision4 tool or the Small Device C Compiler (SDCC) tool. Select one of these two tools as your compiler, and compile the application software. 5. If the preferred compiler is SDCC, run the build_sdcc.bat file which is contained in the <sdcc> folder. Ensure that the INSTALL_FOLDER variable in the build_sdcc.bat file identifies Z8051_2.1 as the installation path; see the following two examples. 32-bit systems: @set INSTALL_FOLDER= "C:\Program Files\Zilog\Z8051_2.1 64-bit systems: @set INSTALL_FOLDER= "C:\Program Files (x86)\zilog\z8051_2.1 AN035901-0513 Page 12 of 17

6. A hex file will be created at the conclusion of the build. Load this hex file to the Z8051 MCU using Zilog s Z8051 OCD 1.147 software tool. To learn more about the compiling and loading of hex files to the MCU, please refer to the Z8051 Tools Product User Guide (PUG0033). 7. Repeat steps 3 6 to load the application software to the slave MCU. Demonstration 1. After loading the software to the MCU, disconnect each 10-pin OCD connector and each USB-to-USB Mini cable from their respective development boards. Note: One 10-pin OCD connector and one USB-to-USB Mini cable are included in each Z51F3220 Development Kit. 2. Power up the development boards by reconnecting each board to the USB-to-USB mini-usb cable it was connected to earlier. 3. Open two terminal emulation programs such as HyperTerminal (or equivalent program). Configure one terminal as the display/user interface for the master, and configure the other one for the slave. Configure each program to reflect the following settings: 9600 baud 8 bits data frame No parity bit 1 stop bit 4. Reset both MCUs by pressing the reset switches on each Development Board. 5. Immediately after reset, the messages shown in Figure 4 should appear, one each for both master and slave. AN035901-0513 Page 13 of 17

Figure 4. HyperTerminal Display After Reset 6. Test whether the master MCU and slave MCU can communicate via the SPI function. Using your keyboard, enter any lower-case alphabetical (i.e., non-numeric) character in the terminal for the master. This character will be sent to the slave through the MOSI line of the SPI. If the transmission is successful, the slave terminal will display this character. The SPI slave will next convert the received character to its upper-case equivalent and transmit it to the SPI master. If this transmission is successful, the character displayed in the master terminal should be the upper-case equivalent of the character you entered earlier. See Figure 5. AN035901-0513 Page 14 of 17

Figure 5. HyperTerminal Display for Master and Slave Results In this application, the user is required to enter an alphabetic character in the terminal emulation console for a master. This character is used as a one-byte piece of data that the master will send to a slave. The slave displays the received data in its own terminal console and returns the uppercase equivalent of the received data. The master then displays this received data from the slave to its terminal. This demonstration shows that the Z51F3220 MCU s USI module can be configured to function as a Serial Peripheral Interface, or SPI. The demonstration also shows that the Z51F3220 MCU s SPI function can successfully send and received data as either a master or a slave. Summary References This document describes the implementation of Zilog s Z8051 USI peripherals as SPI master and slave. In this application, two Z51F3220 development boards are used one as an SPI master and the other one as an SPI slave. Two terminal emulation programs are used as both displays and a user interfaces in which the user must enter a keyboard character as input. The software projects included with this application demonstrate that the USI peripheral block can function effectively as an SPI peripheral. The following documents are each associated to the Z8051 MCU and are available free for download from the Zilog website. AN035901-0513 Page 15 of 17

Z51F3220 Product Specification (PS0299) Z51F3220 Development Kit User Manual (UM0243) Z8051 Tools Product User Guide (PUG0033) AN035901-0513 Page 16 of 17

Customer Support To share comments, get your technical questions answered, or report issues you may be experiencing with our products, please visit Zilog s Technical Support page at http://support.zilog.com. To learn more about this product, find additional documentation, or to discover other facets about Zilog product offerings, please visit the Zilog Knowledge Base at http:// zilog.com/kb or consider participating in the Zilog Forum at http://zilog.com/forum. This publication is subject to replacement by a later edition. To determine whether a later edition exists, please visit the Zilog website at http://www.zilog.com. Warning: DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS. LIFE SUPPORT POLICY ZILOG S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION. As used herein Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. Document Disclaimer 2013 Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Z8, Z8 Encore! and Z8 Encore! XP are trademarks or registered trademarks of Zilog, Inc. All other product or service names are the property of their respective owners. AN035901-0513 Page 17 of 17