Computer Logic II CCE 2010 Dr. Owen Casha Computer Logic II 1
The Processing Unit Computer Logic II 2
The Processing Unit In its simplest form, a computer has one unit that executes program instructions. Because of its central role, this unit is known as the central processing unit (CPU). The solution algorithm for any problem consists of a series of steps that must be carried out in a specific sequence. These steps, each of which represent one machine instruction. Each of these instructions is executed by carrying out a sequence of more rudimentary operations, known as micro instructions. Computer Logic II 3
Program Execution The instructions constituting a program to be executed by a computer are loaded in sequential locations in memory. To execute this program, the CPU fetches instructions, one at a time and performs the functions specified. Instructions are fetched from successive memory locations until a branch or jump instruction is executed. Computer Logic II 4
Program Counter The CPU keeps track of the address of the memory location containing the next instruction by using a dedicated CPU register called the program counter (PC) or instruction pointer (IP). After fetching an instruction, the contents of the PC are updated to point to the next instructions to be executed. Computer Logic II 5
Data Paths Computer Logic II 6
Processor Operations With a few exceptions, most of the operations needed to execute an instruction can be carried out by performing one or more of the following functions: Fetch the contents of a given memory location and load it into a CPU register. Store a word of data from a CPU register into a given memory location. Transfer a word of data from one CPU register to another or to the ALU. Perform an arithmetic or logic operation and store the result in a CPU register. Computer Logic II 7
Fetch a word from Memory Assuming, as an example, that the address of the memory location to be accessed is in register R1 and that the memory contents are to be loaded in R2: [ ] contains of Asynchronous memory (needs a reply) Computer Logic II 8
Synchronous and Asynchronous Transfers A data transfer in which one device initiates the transfer and waits until the other device responds is referred to as an asynchronous transfer. For example the CPU issues a Read request and waits for the MFC signal. In synchronous transfer, one of the control lines carries common timing signals from a central clock. The synchronous transfer scheme leads to simpler implementation, but however it cannot accommodate devices of widely varying speed, except by reducing the speed of all devices to that of the slowest one. Computer Logic II 9
Storing a word in Memory Assuming, as an example, that the address of the memory location to be accessed is in register R1 and that the contents of R2 is to be written to memory: Computer Logic II 10
Input and Output Gating CPU Bus Computer Logic II 11
Register Transfer For example let us consider the transfer of contents of register R1 to register R4: Enable the output of register R1 by setting R1 out to 1. This places the contents of R1 on the CPU bus. Enable the input of register R4 by setting R4 in to 1. This loads the data from the CPU bus into register R4. Computer Logic II 12
An ALU Operation Computer Logic II 13
A Complete Instruction As an example let us consider the instruction: Add (R3), R1 Add the contents of the memory location addressed by R3 (R3 contains the address of the memory location) to the contents of the register R1, storing the result in R1. Execution of this instruction the following actions: Fetch the instructions Fetch the memory operand Perform the addition to R1 Store the results into R1 Micro instructions 1. PC out, MAR in, Read, Clear Y, Set Carry-in, Add, Z in 2. Z out, PC in, WMFC 3. MDR out,ir in 4. R3 out, MAR in, Read 5. Clear Carry-in, R1 out, Y in, WMFC 6. MDR out, Add, Z in 7. Z out, R1 in, End Computer Logic II 14
Instruction fetch (Step 1) Computer Logic II 15
Instruction fetch (Step 2) Computer Logic II 16
Instruction fetch (Step 3) Computer Logic II 17
Operand 1 fetch (Step 4) Computer Logic II 18
Operand 2 load (Step 5) Computer Logic II 19
Perform addition (Step 6) Computer Logic II 20
Store Result (Step 7) Computer Logic II 21
Instruction Parallelism From the previous slides, it is to note that the instructions could be performed in parallel as long and they don t use the CPU bus simultaneously. Thus the CPU bus is used in mutual exclusion. Whilst waiting for memory to reply to request by the CPU, using the WMFC, other operations, which do not need the data from memory could be performed. The two factors decide the division of the instructions into steps. Computer Logic II 22
Branching (Jumps) Branching is accomplished by replacing the current contents of the PC with the branch address, i.e. the address of the instruction to which the program must branch. In relative addressing, the branch address is usually obtained by adding an offset X which is given in the branch instruction, to the current value of the PC. Computer Logic II 23
Get PC contents (Step 4a) Computer Logic II 24
Conditional? (Step 4b) Computer Logic II 25
Add Offset (Step 5) Computer Logic II 26
Restore PC (Step 6) Z in Computer Logic II 27
Hardwired Control One technique for the generating the control signal to perform the required operation steps is the Hardwired Control technique. Consider the sequence of operations needed for the ADD operation seven non-overlapping time slots are required for the execution of this instruction, each of which long enough to enable the CPU to perform all the required actions in the given step. If we assume a constant time is allotted to each step, the required control signals can be based on a counter driven by a clock signal. Computer Logic II 28
Control Unit Organization Computer Logic II 29
Encoder / Decoder * Macro-instructions Micro-instructions * Johnson Counter 100,010,001,100, Computer Logic II 30
Encoder Signal Example Considering the timing of Z in in the various operations considered: Occurs in T 1 of every operation since it makes part of the instruction fetch cycle. Occurs in T 6 of the ADD command. Occurs in T 5 of the JMP command. Z in = T1 + T6 ADD+ T5 JMP+... + Computer Logic II 31
Encoder Logic Computer Logic II 32
The End Case Computer Logic II 33
PLA Circuit Implementation PLA Computer Logic II 34
Micro-programmed Control In microprogrammed control, control signals are generated by a program similar to a machine language program. A control word CW is a word whose individual bits represent the various control signals. Each of the control steps in the control sequence of an instruction defines a unique combination of 1 s and 0 s in the CW. A sequence of CWs corresponding to the control sequence of a machine instruction constitutes the micro-routine for that instruction, and the individual control words in this micro-routine are referred to as micro-instructions. Computer Logic II 35
Micro-instruction Example (Add) Computer Logic II 36
Basic Microprogrammed Control Unit Computer Logic II 37
Conditional Execution Conditional branching cannot be implemented using this simple system. In this case, the microinstruction set is expanded to include some conditional branch microinstructions: In addition to the branch address, these microinstructions specify which of the status flags, condition codes, or, possibly, bits of the instruction register, should be checked as a condition for branching to take place. To support micro-program branching, the organization of the control unit should be modified in a such a way that the address generator could be modified during the execution of an instruction. Computer Logic II 38
JPN Microroutine Computer Logic II 39
Modified Control Unit Computer Logic II 40
Micro PC loading In this control unit, the micro-program-counter is incremented every time a new microinstruction is fetched from the micro-program memory, except: When the end microinstruction is encountered, the Micro- PC is loaded with the address of the first CW in the microroutine for the instruction fetch cycle (address 0). When a new instruction is loaded into IR, the micro-pc is loaded with the starting address of the micro-routine for that instruction. When a branch microinstruction is encountered and the branch condition is satisfied, the micro-pc is loaded with the branch address. Computer Logic II 41
Microinstruction Format In this basic scheme we require a bit for every control signal. Thus in the basic control unit described we need: Computer Logic II 42
Reduced Encoding Scheme Reduction of the scheme is possible by considering the following factors: Most signals are not needed simultaneously, and many signals are mutually exclusive. For example: Only one function of the ALU can be active at one time The source for data transfer is unique Read and write memory signals are mutually exclusive. Thus all mutually exclusive signals are placed in the same group. It is then possible to use a binary coding scheme to represent signals within a group by introducing additional decoding circuits. Most fields must include a non-active code if none of the members are needed to be active. Computer Logic II 43
Field-encoded Microinstructions Computer Logic II 44
Encoding Example ADD EXAMPLE Computer Logic II 45
Step 1 ADD Example Computer Logic II 46
Further Reading Computer System Architecture: M. Morris Mano, Prentice Hall. Computer Organization: V. Carl Hamacher, Zvonko G. Vranesic, Safwat G. Zaky, McGraw-Hill International Editions Chapter 3. Computer Logic II 47