J. Manikandan Research scholar, St. Peter s University, Chennai, Tamilnadu, India.

Design of Single Correction-Double -Triple -Tetra (Sec-Daed-Taed- Tetra Aed) Codes J. Manikandan Research scholar, St. Peter s University, Chennai, Tamilnadu, India. Dr. M. Manikandan Associate Professor, Dept of Electronics, MIT Campus, Anna University, Chennai, Tamilnadu, India. Abstract correction codes are used in semiconductor memories to protect information against soft and hard errors. Soft error is a major concern for memory reliability especially for memories that are used in space applications. Hamming codes are attractive as they are simple to construct for any word length and encoding / decoding can be done with low latency. In this paper, the design of Single Correction-Double -Triple -Tetra (SEC-DAED-TAED-Tetra AED) codes through bit placement algorithm is presented with less number of parity bits. In conventional ( detection and Correction) EDC mechanism, Single Correction and Double (SEC-DAED) are done by using Hamming Code. In order to detect the Triple adjacent error in SEC-TAED, it is required to add one parity bit, which consumes more amount of computational time for detecting the triple adjacent error. In Tetra adjacent error in SEC-Tetra AED is also required to add one more parity bit for detecting the error. To overcome this problem, SEC-DAED-TAED- Tetra AED method is proposed in this paper. In proposed, Tetra does not require the parity bits to detect the errors. In conventional SEC-Tetra adjacent error detection, it is performed by bit placement algorithm in our proposed work which offers more efficiency. The combined structure of SEC-DAED-TAED-Tetra AED is used to transfer the information for performing the space communication. It is more efficient and high speed compared to conventional method. Keywords: Single Correction-Double -Triple -Tetra (SEC-DAED-TAED-TetraAED), and Correction (EDC), Single Correction- Triple ( SEC-TAED), Single Correction-Double (SEC-DAED). avoid this data corruption issue, one option is to use Correction Codes (ECCs) which are already used in memories for reliability purposes. Single-error-correction (SEC) codes are utilized when low delay is required. Single-error-correction Double-error- (SEC-DED) codes, with a distance of four, so they are preferred in memory applications. A SEC-DED code can be created by extending a Hamming code with a parity bit covering all bits. SEC and SEC-DED codes would not be able to detect the error and could even incorrect the word into a different valid one producing Silent Data Corruption (SDC) which can lead to an incorrect system behavior and further data corruption. Hamming code scheme is used to protected the external memory, due to the parity memory having 8 bits width, (40,32) a hamming code is used, it is on the base of (39, 32) Hsiao code, adding a parity bit to minimize the probability of 3 bits fault corrected in error. In this paper, specific matrices for single-error-correction double adjacent error detection (SEC-DAED) Hamming codes are presented. They will provide a code capable of correcting single errors and detecting double adjacent errors. Additionally, Single Correction-Double -Triple (SEC-DED-TAED) codes are generated from an extended Hamming code. In this paper, we proposed Single Correction-Double -Triple - Tetra (SEC-DAED-TAED-Tetra AED). To maximize the probability for correct a single error and detect the tetra adjacent error, Bit placement algorithm is used. For the conventional Triple codes are required one more parity bit than the Double. In this proposed work, Tetra is detected without need of one more parity bit. The combined structure of SEC-DAED-TAED-Tetra AED is used to transfer the information for performing the space communication. Introduction Hamming codes are introduced more than 60 years ago and they are still used in many applications. Hamming Codes are widely used to detect and correct an error during the data transmission. One application is the protection against soft errors produced by a radiation particle hitting SRAM memory cells or a register and changing the value stored in them. To Related Work Enhanced of Double and Triple s in Hamming Codes Through Selective Bit Placement has been explained in[6].in this paper, a technique to increase the probability of detecting double and triple adjacent errors when hamming codes are used. The enhanced detection is achieved by placing the bits of the word such that adjacent errors result 4440

in a syndrome does not match that of any single error. Low- Power Compact Composite Field AES S-Box/Inv S-Box design in 65nm CMOS using Novel XOR Gate has been described in [1]. This paper presents a full custom CMOS design of S-Box/Inv S-Box with low power GF (28) Galois Field Inversions based on polynomial basis, using composite field arithmetic. The S-Box/Inv S-Box utilizes a novel low power 2-input XOR gate with only six devices to achieve a compact module implemented in 65 nm IBM CMOS technology. This design indicates a power dissipation of only around 0.09µW using a 0.8V supply voltage. Research and Implementation of SEC-DED Hamming Code Algorithm has been briefly explained in [5]. In this paper, the Hamming Code scheme is used to protected the external memory, due to the parity memory having 8 bits width, a(40,32) hamming code is used, it is on the base of (39,32) Hsiao code, adding a parity bit to minimize the probability of 3 bits faults corrected in error. Hamming SEC-DAED and Extended Hamming SEC-DED-TAED Codes through Selective shortening and Bit Placement has been described in [7]. In this paper, specific matrices for single-error-correction double adjacent error detection (SEC-DAED) hamming codes are presented. They will provide a code capable of correcting single errors and detecting double adjacent errors. Additionally, Single--Correction Double-- Triple (SEC-DED-TAED) codes are generated from an extended hamming code. Efficient Implementation of Hamming SEC-TAED Code Algorithm for Data Communication has been explained in [4]. In this paper, the design of Single Correction-Triple (SEC-TAED) codes through Bit Placement algorithm is presented with less number of parity bits. In the proposed method, the detection efficiency is increased when compared to conventional SEC-TAED. Design of a High Speed and Area Efficient Optimized Mixcolumn for AES has been designed in [3].In this paper, a novel optimized Mix-Column is designed for AES decryption through VLSI design environment. The proposed Mix- Column is incorporated into AES Decryption for improving the performance in terms of VLSI concerns (area, delay and power). Modified Hamming Codes with Double Correction along with Enhanced has been explained in[2].in this paper, modified hamming codes to enhance adjacent error detection along with double adjacent error correction is presented. The modified hamming codes can correct single and double adjacent errors and can detect double errors and triple adjacent errors. On Forward Correction with Hamming Code for Multipath Communications have been explained in [8]. In this paper, the performance bound in the high error-rate networks and integrated multipath communication and Hamming code (11-7). Using the Markov model, the performance of Multipath Hamming Code based Forward Correction (MHC- FEC) is analyzed and compared with Multi-Path Power Control (MPC). Bit-Level Soft-Decision Decoding of Double and Triple-Parity Reed-Solomon Codes Through Binary Hamming Code Constraints has been described in [9].This paper discussed bit-level soft-decision decoding of double and triple-parity Reed-Solomon (RS) codes through binary Hamming Code constraints. Based on the binary image of RS code, they first present the new expressions of the associated parity-check equations. These expressions indicate that each parity-check equation of RS code with roots α i (0 < i < 3) over GF(2 q ) can be viewed as parity-check equations of a compound Hamming code over GF(2). Hamming Codes Hamming codes are a family of linear block error correcting codes that generalize the rate codes invented by Ritchard Hamming in 1950 [Alfonso sanchez,2013]. The following are two obvious properties of Hamming single error correcting codes. Property 1: The 2 m -1 column of the m by 2 m -1H matrix are exactly all the 2 m -1 binary non zero m-tuples. Property 2: For every pair of column positions, there is exactly one other column that is the sum of the given pair and thus is the only weight 3 code word that includes the given pair. Hamming codes are perfect codes, they can achieve highest possible rate for codes with their block length and minimum distance. In mathematically Hamming codes are characterized for m 3 by the following parameters, n = 2 m -1 (1) k = n-m (2) d min = 3 (3) Where n is the block size, k is the number of information bits, d min is the minimum distance of the code and m is the parity check bits. An algorithm to generate Hamming Codeword s from information bits are as follows a) Number of all position of bits starting from 1 to n, where n is the last position of the bit. b) All the positions are written in their binary form as 1,10,11,100,101,110 etc. c) All bit positions that are powers of two ( have only one bit in the binary form of their positions) are considered as a parity bits. 1) Position 1: To verify 1 bit and bound 1 bit steps are followed such as 1, 3,5,7,9 2) Position 2: To verify 2 bits and bound 2 bit steps are followed such as 2, 3 6, 7, 10, 11. 3) Position 3: To verify 4 bits and bound 4 bits steps are followed such as 4, 5, 6,7,12,13,14,15 4) Position 4: To verify 8 bits and bound 8 bits steps are followed such as 8-15, 24-31, 40-47 Finally, set a parity bit to 1 if the total number of ones in the position is odd. Set a parity bit to 0 if the total number of ones in the position is even. In this way we get the codeword by using hamming. We can detect the single bit error by using syndrome values. Parity bits are calculated as follows: c1 =c3 + c5 + c7 or p1 = d1 + d2 + d4 (4) c2 =c3 + c6 + c7 or p2 = d1 + d3 + d4 (5) c4 =c5 + c6 + c7 or p3 = d2 + d3 + d4 (6) In order to check the codeword, the parity bits are recalculated again from the information bits and compared to 4441

the original set of parity bits. If they match, then no error was detected, otherwise an error is detected and the non-matching parity bits can provide us with the information bit that was flipped so that the error can be corrected. For Examples, parity check matrices for (7,4) is 1 0 0 0 1 1 1 H = 0 1 0 1 0 1 1 (7) 0 0 1 1 1 0 1 This H matrix is called as a lexicographic check matrix. If generated codeword is 1011010, then the multiplication of parity check matrix H and resulted codeword is 000, called as a syndrome vector. It is a null vector value gives the result of actual code that means no error has been generated, and therefore, the current value of the word is an actual code word. If generated codeword is (1011011), then the multiplication of parity check matrix H and resulted codeword is (111). So, it can generate value 7, that mean error can generate in a seventh bit. we can easily detect and correct single bit error in this way. But it is not suitable for double bit error. For detecting double bit error, we need another parity bit and therefore minimum hamming distance become as four. But we cannot correct the detecting double bit error and could take a incorrect word into a different valid one producing Silent Data Corruption (SDC). SEC-DAED Hamming Codes A single error should be corrected using hamming code. However, when a double error occurs, an algorithm incorrect the codeword. To overcome this problem, A Extended versions of Hamming code used, that is a additional parity bits used to detect the double error. Unfortunately, this algorithm can be used for even detect the triple adjacent error. In order to detect the double bit error, we can use two techniques, (1) Bit Replacement or reordering the codeword, when lexicographic matrix used. (2) Shortening technique. The lexicographic matrix for the shortened hamming code (12,8) is shown in, 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 H = ( ) (8) 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 When a single bit error occurs in the codeword, the syndrome vector that results from the product of the lexicographic matrix with the error code word gives the binary representation of the position where the error was inserted. Using as an example Hamming code (12,8), data bits (01010100) are coded as (000010110100). When an error occurs and, for instance, the fifth bit is changed the codeword turns into (00000110100). The product of this vector by the lexicographic check matrix results in the syndrome vector (1010) corresponding to the binary representation is five and therefore we can easily detect and correct the error. Coming back to the previous example, if there is a double bit error in original word in position 5 and 6, we get the vector (000001110100). Now product of this vector by lexicographic check matrix results in the syndrome vector is (0011) corresponding to binary representation is 3. In this case, codeword is miscorrect instead of correcting right word. Extended Hamming code is the solution of above problem, we can insert additional parity bits and therefore minimum distance is four. The H-matrix of the extended Hamming code is formed by adding a row with all 1 s, and also by adding a 1- weight column with upper r-1 0 s to the H-matrix of the hamming code. This solution allows the single error corrections and double error detections simultaneously. In the other hand, it can also be used to detect the triple error. The extended hamming code (13, 8) encodes (10110100) into (0000101101000). The double error in position 7, 11 and 2 turns into codeword (0100100101100). This produces (1110) corresponding bit representation is 14, zero valid syndromes with no error in the parity bit. It cannot be corrected as it does not match a valid code bit position. An Extended Hamming Code can also be used for detect the triple adjacent error error but even it could incorrect the codeword. In order to detect the Triple adjacent error in SEC- TAED, it is required to add one parity bit, which consumes more amount of computational time for detecting the triple adjacent error. In Tetra adjacent error in SEC-Tetra AED is also required to add one more parity bit for detecting the error. To overcome this problem, SEC-DAED-TAED-Tetra AED method is proposed in this paper. In proposed, Tetra does not require the parity bits to detect the errors. Proposed SEC-DAED-TAED-TETRA AED Using Hamming Code In this paper, a special hamming code has been developed which can detect and correct a single error effectively. As well as detect the maximum combination of double adjacent error and triple adjacent error. Selective Bit Replacement algorithm is used for designing the SEC-DAED-TAED-Tetra AED hamming codes. This hamming codes use only 12 bits for performing all the needful. Hence, this hamming code is named as Extended SEC-DAED-TAED-Tetra AED Hamming Codes. The flow chart of Selective Bit- Replacement Strategy has been illustrated in Fig 1. In extended SEC-DAED-TAED-Tetra AED hamming code, 6 combinations of Tetra adjacent error and 5 combination of Double- and Triple- have been detected successfully. The maximum number of combination in 12-bit codeword is 11 number of Double- combination and 9 number of triple adjacent error combination. Table 1 shows the proposed SEC-DAED-TAED hamming codes. Proposed Extended SEC-DAED-TAED-Tetra AED hamming code has been detected 36.36% of Double (DAED) and 30% of Triple (TAED) and 66% of Tetra (Tetra AED) than traditional Hamming model. Further table II illustrates the possible combination of detecting double and triple adjacent error in both traditional and proposed system. 4442

In each and every figure, status is displayed for the corresponding detection errors. For single bit error, it must be able to correct an error. But double, triple and tetra adjacent error, the proposed system can able to detect only not corrected. If trying to correct the double or triple or tetra adjacent error, it is possible to occurring SDC effects. Hence, detecting property only is enough for double, triple and tetra adjacent errors. Figure 1: Flow chart of Bit Re-placement Strategy Figure 2: Simulation result of SEC-DAED-TAED-TETRA AED hamming codes-status shows as SEC Table I: sec-daed-taed-tetra aed hamming code Bit Placement Double Triple Tetra 1 2 3 4 5 6 7 8 9 10 11 12 2/11 18% 3/10 30% 0/9 0% 5 6 8 4 1 2 10 7 9 11 12 3 4/11 36.36% 3/10 30% 6/9 66% Figure 3: Simulation result of SEC-DAED-TAED-TETRA AED hamming codes-status shows as DAED Table II: possible combination of detecting double and triple adjacent error combination in both traditional and proposed system Traditional Hamming Code Proposed Extended Number System Hamming SEC-DAED- TAED Number System Double Triple Tetra Double Triple Tetra (4, 5) (7, 8) (3, 4, 5) (1, 2, 3) (8, 9, 10) ~ (6,8) (7,10) (7,9) (3,12) (1,4,8) (2,7,10) (9,11,12) (1,2,4,8) (7,9,10,11) (4,5,6,8) (3,9,11,12) (1,2,7,10) (1,2,4,10) Figure 4: Simulation result of SEC-DAED-TAED-TETRA AED hamming codes-status shows as TAED Results and Discussions Simulation results of Proposed Extended SEC-DAED-TAED- TETRA AED Hamming Codes have been evaluated by using ModelSim 6.3C. When correcting SEC or detecting DAED, TAED and Tetra AED, it shows the appropriate status indication. Simulation result of proposed hamming SEC- DAED-TAED-TETRA AED hamming codes for detect and correcting a single error, detecting the double adjacent error, detecting the triple adjacent error and detecting the tetra adjacent errors are shown in figure 2, 3, 4 and 5 respectively. Figure 5: Simulation result of SEC-DAED-TAED-TETRA AED hamming codes-status shows as TETRA AED Conclusion In this paper, extended hamming codes are used to maximize the probability of detecting a SEC-DAED-TAED-TETRA 4443

AED. The Proposed Extended Hamming Single Correction-Double -Triple -Tetra has been designed through Very Large Scale Integration System (VLSI) design environment. Verilog Hardware Description Language (Verilog HDL) is used to design the proposed Hamming code. The proposed SEC-DAED-TAED-Tetra AED Hamming codes are used to avoid the wrong information passes through the space communication. For the space or terrestrial applications, proposed codes gives a control message to earth pilot when transformation of messages have in bit flipping. The SEC-DAED-TAED is required to add one parity bit, which consumes more amount of computational time for detecting the error. Similarly, Tetra also required one more parity bit to detect the error. To overcome this problem, we proposed Tetra AED, which does not require parity bit in this paper. In future, the proposed technique will be enhanced to reduce the parity bits for detecting the five and six errors. [9] Wang, X., & Tang, S. (2015). Bit-Level Soft- Decision Decoding of Double and Triple-Parity Reed-Solomon Codes Through Binary Hamming Code Constraints. Communications Letters, IEEE, 19(2), 135-138. References [1] Ahmad, N., & Hasan, S. R. (2013). Low-power compact composite field AES S-Box/Inv S-Box design in 65nm CMOS using Novel XOR Gate. Integration, the VLSI journal, 46(4), 333-344. [2] Arlat, J., & Carter, W. C. (1984). Implementation and evaluation of a (b, k)-adjacent errorcorrecting/detecting scheme for supercomputer systems. IBM journal of research and development, 28(2), 159-169. [3] Hodjat, A., & Verbauwhede, I. (2006). Areathroughput trade-offs for fully pipelined 30 to 70 Gbits/s AES processors. Computers, IEEE Transactions on, 55(4), 366-372. [4] Chandrika, S., and R. Rani Hema Malini. "Efficient Implementation Of Hamming SEC-TAED Code Algorithm For Data Communication." [5] Cui, Y., Lou, M., Xiao, J., Zhang, X., Shi, S., & Lu, P. (2013). Research and implementation of SEC- DED Hamming code algorithm. InTENCON 2013-2013 IEEE Region 10 Conference (31194) (pp. 1-5). IEEE. [6] Sánchez-Macián, A., Reviriego, P., & Maestro, J. A. (2012). Enhanced detection of double and triple adjacent errors in hamming codes through selective bit placement. Device and Materials Reliability, IEEE Transactions on,12(2), 357-362. [7] Sanchez-Macian, A., Reviriego, P., & Maestro, J. A. (2014). Hamming SEC-DAED and extended hamming SEC-DED-TAED codes through selective shortening and bit placement. Device and Materials Reliability, IEEE Transactions on, 14(1), 574-576. [8] Xu, J., Zhang, T., & Dong, Z. (2012). On Forward Correction with Hamming Code for multi-path communications. In Wireless Communications & Signal Processing (WCSP), 2012 International Conference on (pp. 1-5). IEEE. 4444