TSK3000A - Generic Instructions Frozen Content Modified by Admin on Sep 13, 2017 Using the core set of assembly language instructions for the TSK3000A as building blocks, a number of generic instructions (also referred to as pseudo instructions or macros) are defined and supported by the Assembler for the TSK3000A. Each of these generic instructions, as listed in Table 1, translate into one or more separate assembly language instructions (from the core set) in order to fulfill their task. Note: In Table 1 the following operands are used: ra register index of source operand A rb register index of source operand B rc register index of destination IMM5 5-bit immediate value IMM16 16-bit immediate value IMM32 32-bit immediate value target absolute offset or symbolic address label (ra) address specified by contents of a base register (GPR ra) target(ra) based address (can also be represented as offset(base)). The target address is added to the contents of the base register (GPR ra) to obtain the actual address. Table 1. Generic Instructions. Mnemonic ABS rc, ra ABS ra ADD rc, rb ADD rc, ra, IMM32 ADD rc, IMM32 ADDI rc, IMM16 ADDIU rc, IMM16 ADDU rc, rb ADDU rc, ra, IMM32 ADDU rc, IMM32 Instruction Absolute Value Add Add Immediate Add Immediate Unsigned Add Unsigned
AND rc, rb AND rc, ra, IMM32 AND rc, IMM32 ANDI rc, IMM16 B target BAL target BEQ ra, IMM32, target BEQZ ra, target BGE ra, rb, target BGE ra, IMM32, target BGEU ra, rb, target BGEU ra, IMM32, target BGT ra, rb, target BGT ra, IMM32, target BGTU ra, rb, target BGTU ra, IMM32, target BLE ra, rb, target BLE ra, IMM32, target BLEU ra, rb, target BLEU ra, IMM32, target BLT ra, rb, target BLT ra, IMM32, target BLTU ra, rb, target BLTU ra, IMM32, target BNE ra, IMM32, target BNEZ ra, target BREAK DIV ra, rb DIV ra, IMM32 DIV rc, ra, IMM32 DIVU ra, rb DIVU ra, IMM32 DIVU rc, ra, IMM32 J ra JAL ra JAL rc, target Bitwise Logical AND Bitwise Logical AND Immediate Branch Branch And Link Branch On Equal Branch On Equal To Zero Branch On Greater Than Or Equal Branch On Greater Than Or Equal Unsigned Branch On Greater Than Branch On Greater Than Unsigned Branch On Less Than Or Equal To Branch On Less Than Or Equal To Unsigned Branch On Less Than Branch On Less Than Unsigned Branch On Not Equal Branch On Not Equal To Zero Breakpoint Divide Divide Unsigned Jump Jump And Link
JALR target JALR ra JALR rc, target JR target LA rc, target LA rc, target(ra) LI rc, IMM32 LB rc, (ra) LB rc, target LB rc, target(ra) LBU rc, (ra) LBU rc, target LBU rc, target(ra) LH rc, (ra) LH rc, target LH rc, target(ra) LHU rc, (ra) LHU rc, target LHU rc, target(ra) LW rc, (ra) LW rc, target LW rc, target(ra) MOVE rc, ra MULT ra, rb MULT ra, IMM32 MULT rc, ra, IMM32 MULTU ra, rb MULTU ra, IMM32 MULTU rc, ra, IMM32 NEG rc, ra NEG ra NEGU rc, ra NEGU ra NOP Jump And Link Register Jump Register Load Address Load Immediate Load Byte Load Byte Unsigned Load Halfword Load Halfword Unsigned Load Word Move Multiply Multiply Unsigned Negate Negate Unsigned No Operation
NOR rc, rb NOR rc, ra, IMM32 NOR rc, IMM32 NOT rc, ra NOT ra OR rc, rb OR rc, ra, IMM32 OR rc, IMM32 ORI rc, IMM16 ROL rc, ra, IMM5 ROL rc, ra, rb ROL rc, IMM5 ROL rc, rb ROR rc, ra, IMM5 ROR rc, ra, rb ROR rc, IMM5 ROR rc, rb SB rc, (ra) SB rc, target SB rc, target(ra) SEQ rc, ra, rb SEQ rc, ra, IMM32 SGE rc, ra, rb SGE rc, ra, IMM32 SGEU rc, ra, rb SGEU rc, ra, IMM32 SGT rc, ra, rb SGT rc, ra, IMM32 SGTU rc, ra, rb SGTU rc, ra, IMM32 SH rc, (ra) SH rc, target SH rc, target(ra) Bitwise Logical NOR Bitwise Logical NOT Bitwise Logical OR Bitwise Logical OR Immediate Rotate Left Rotate Right Store Byte Set On Equal To Set On Greater Than Or Equal To Set On Greater Than Or Equal To Unsigned Set On Greater Than Set On greater Than Unsigned Store Halfword
SLA rc, ra, IMM5 SLA rc, ra, rb SLA rc, IMM5 SLA rc, rb SLAV rc, ra, rb SLAV rc, rb SLE rc, ra, rb SLE rc, ra, IMM32 SLEU rc, ra, rb SLEU rc, ra, IMM32 SLL rc, ra, rb SLL rc, IMM5 SLL rc, rb SLLV rc, rb SLT rc, rb SLT rc, ra, IMM32 SLT rc, IMM32 SLTI rc, IMM16 SLTU rc, rb SLTU rc, ra, IMM32 SLTU rc, IMM32 SLTIU rc, IMM16 SNE rc, ra, rb SNE rc, ra, IMM32 SRA rc, ra, rb SRA rc, IMM5 SRA rc, rb SRAV rc, rb SRL rc, ra, rb SRL rc, IMM5 SRL rc, rb SRLV rc, rb SUB rc, rb SUB rc, ra, IMM32 SUB rc, IMM32 Shift Left Arithmetic Shift Left Arithmetic Variable Set On Less Than Or Equal To Set On Less Than Or Equal To Unsigned Shift Left Logical Shift Left Logical Variable Set On Less Than Set On Less Than Immediate Set On Less Than Unsigned Set On Less Than Immediate Unsigned Set On Not Equal To Shift Right Arithmetic Shift Right Arithmetic Variable Shift Right Logical Shift Right Logical Variable Subtract
SUBU rc, rb SUBU rc, ra, IMM32 SUBU rc, IMM32 SW rc, (ra) SW rc, target SW rc, target(ra) XOR rc, rb XOR rc, ra, IMM32 XOR rc, IMM32 XORI rc, IMM16 Subtract Unsigned Store Word Bitwise Logical Exclusive OR Bitwise Logical Exclusive OR Immediate Source URL: https://techdocs.altium.com/display/fpga/tsk3000a+-+generic+instructions