Status of Trigger Server electronics Trigger boards TB Server board SB Topics: Trigger Server Status TSS screening TSM and SB pre-production tests LVDS Jitter tolerance measures
Trigger Server Status update LVDS to Sector Collector backplane bus Link board Server Board Chamber Minicrate TSS (1200 ASIC, Alcatel 0.5 µm): - full production already delivered - currently: screening of 1200 working devices ready to start Server Board : -pre-production delivered in March. 03 (5 SB) -2 SB succesfully tested! -Pre-series production will start soon (beginning of May) -> to provide 35 SB for 03 minicrate production - tender for full production going on Control serial line TSM (250 TSMS + 500 TSMD pasic, Actel, 0.35 µm): - 1000 device (to be fused) in hands - Final Prototype succesfully tested! - 1 month to fuse all chips (ext firm already contacted): wait for pre-production tests of the Server Board (End Apr.)
TSS Screening HW system Screening will be performed in Bologna with the test jig setup for prototypes Piggy board mounted on a Pattern unit emulating Traco input and receiving output TSS Asic Alcatel 0.5 µm CMOS Product by Europractice
TSS Screening SW system SW developed in Visual C++, fully automatic 4 x 10 bit I/O TRACO pads previews *) interfaces Power supply and clock generator through GPIB protocol *) interfaces mysql database for bookeeping Parallel Interface R E G R E G Carry JTAG controller Input mask Quality Filter Priority Encoder Configuration Registers 4 x 9 bit Ghost2 Buster Ghost1 Buster SNAP regs 9 bit TEST regs 2 word comp x 10 Θ filter FBT SBT R E G R E G Reset control I/O pads I/O pads 8 5 bit TRACO select 11 bit TSM preview Full test: Bonding check Running test (different conf, Clock frequency and Voltage supply) Monitor and control logic check (Jtag and Parallel access) Spying and Test features (snap and test reg.s) Power consumption continuously monitored Program mode JTAG serial line FBT = First Best Track SBT = Second Best Track
TSS Screening System performance Performances of the test system: Bonding check ( < 1 s) Test sorting in different setups with 10 6 patterns (~16 s @ 60 Kevt/s) Test monitoring and control logic ( ~ 5 s) 2 min/chip Delivery consists of 2700 chips Process yield 70% Package yield 90% (conservative estimate) To have 1200 TSS working We need to test ~ 2000 chip Bookeeping into the database 4 weeks! With a working time of 4 hour/day
Server Board Pre-production Front side 20.6 cm PCB 16 layers! 9.5 cm TSM side TSMS TSMDs National serializer 10-to-1 DS92LV1021 Reminder: TSM is implemented with 3 pasic Actel A54SX32 0.35 µm CMOS NB: Backside contains most of the control logic electronics for the minicrate
Server Board Test System Crate VME Pattern Units Vme board with CPU Pentium II 80 bits @ 40 MHz Rs232 PC serial port 232 bits @ 40 MHz Server Board Trigger Link Rx 232 bits @ 40 MHz LVDS link Adapter Board data serialized @ 480 MHz 2 copper cables FTP class 6 40 m
Server Board Test Setup Server Board Trigger Link Rx Adapter Board
Server Board Software for tests Developed under WinNT with Visual C++ SW controls all test options: Generates, transmits and receives pattern Checks output with emulation Finds better setup conditions Provides monitoring and configuring Clock phase (input) Good working condition! Clock phase (output) SW to use for full SB production test.
TSM design a reminder TSM system is the bottleneck of the trigger electronics on chamber. It is segmented on 3 pasics with partially redundant functionalities: Two main working modes: Normal mode (all pasics work properly) Backup mode (one or two pasics in failure)
TSM algorithm another reminder.. Remember: TRACO sends 2 tracks belonging to the same trigger events in 2 consecutive BXs TS task : to sort two best tracks in two consecutive BXs Normal mode: implemented by sorting 1 track out of 6 for BX Backup mode: each half chamber sorts 2 tracks independently in two BXs, by means of a quick sorting (quality bits are involved) Main features (enabled in default, can be switched off): Recovery of good track eventually found at the previous BX (called carry ) Ghost rejection Recovery of good tracks in overlapped events (i.e.pile-up between tracks from events in consecutive BXs)
TSM and SB Test Status Server Board Tests Summary (2 boards fully tested): Board layout was checked and approved for production. Signals transmission from Pattern Units has been successfully checked! (N.B: it has the same characteristics of transmission from Trigger Boards) TSM monitoring and configuring works fine! TSM output tests with LVDS transmission through 40 m cables has been performed. TSM Algorithm Tests Summary: First test: About 1000 surgical input patterns have been initially used. These surgical patterns, developed during the chip design and simulation, thoroughly check all functionalities, in different configurations also. Second test: About 10 9 random input patterns have been submitted with different configurations in long tests periods (3-4 days) to find bugs and check stability and performances Results: -TSM and SB work as expected up to 44 MHz of clock frequency and transmitting output through cables long up to 40 m.
LVDS Trigger Link Sector Collector Board Opto-Link DTTF ( in USC55 ) Balcony Sector Collector VME Crate TSM MB 4 TSM MB 3 Ethernet cables ( up to ~40m ) CLASS 6 FTP Z 0 = 100 Ω TSM TSM MB 1 MB 2
Jitter Measurements Jitter Tolerance measured in Bologna Stand-alone LVDS transmission system equipped as the final trigger link system Clock Jitter generator Maximum Jitter tolerated from National Serializer LVDS in worst conditions with Cable of 40 m lengths => RMS = 80 ps Jitter Tolerance measured in Legnaro TTCex driven by TTCvi TTCoc inserted (Optical input power = -20dBm) TTCrx in MC sends clock on LVDS ser. No Broadcast command Measured : RMS = 26 ps