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Transcription:

Norm

Midterm Grading Finished Stats on course homepage Pickup after this lab lec. Regrade requests within 1wk of posted solution Homework deadline extended to next friday

Description Design Conception Implementation Verification (Debugging)

Description Design Conception Implementation Verification (Debugging)

Classification of Elements in a Digital Circuits Datapath Storage(Sequential) Flipflops, Counter, Shift-reg Combinational Arith: Add, Sub, Mult, Comp Logic: And, Or, Xor Routing?: Shifter, Mux, Tri-st Control States for FSM (flipflops) Random logic (FSM,next state,output) *Memory is an exception to the above chart. They can operate with or without clock and can store values

Sequential, or Storage These are the only things* that can store values. they are controlled by a clock and their output value can only change on a clock-edge. Combinational These cannot hold state, output is purely a function of input.

IS a Hardware Description Laguage Is NOT a programing language Design your circuit first then write the code. Was initially designed for simulating hardware Was NOT initially designed for generating hardware Not all valid verilog turns into hardware. Some verilog turns into inefficient hardware implementation (too many CLBs )

always @ (posedge CLK or posedge a) if (a) Q <= R; Optional else if (b) Q <= R; else if (c) Q <= D; a = asynchronous set-reset line b = synchronous set-reset line R = set-reset value (should be constant) D = next value for Q (could be expression) Express any sequential logic buy substituting different values, variables for a, b, R, D rst en Counter Q a = rst, c = en, d = Q + 1; Note: it is okay to write Q <= Q, in this case because Q is a storage element. This is not always the case.

Can be written in two ways 1 2 assign O = Y; always @ (all inputs) begin end Example: Case (A) 1 : begin if (B) O <= C; end Be careful! A, B, C are all inputs! E I O Assign O = E? I : 1 bz Always @ (E or I) if (E) O <= I; else O <= 1 bz; Notice: O must be of type wire for assign statement and type reg for always statement. However after synthesis O will physically be a wire in the circuit.

always @(posedge clk) begin c <= a+1; b <= c+1; end always @(posedge clk) begin c = a+1; b = c+1; end 1 1 1 A + C + B A + C 1 + B

1. Not assigning a wire outputs. (incomplete truth table therefore variable must remember previous values) 2. Assigning a variable to itself. (same as not assigning since reg types remembers it s value if it is not assigned 1 always to) @(A or B) Template for begin A latch begin if (A) (look familiar?) if (GATE) 2 D = B; End always @(A or B) begin if (A) D = B; else End D = D; B A D always @(GATE or DIN) DOUT = DIN; End This circuit is not combinational! Output is not just a function of inputs

Desired functionality To read one of many results depending on come control information A B? C O R A B Mux C[0] C Notice the tri state Has 2 control lines where as the mux has only one O A B Tri-state C[1] O

4-LUT CLB 3-LUT FF LUTs cannot output high-impedence Z therefore each CLB also has a pair of 4-LUT FF Tri-states

I[0] I[1] I[2] I[3] I[0] C[1:0] O I[0] I[1] C[0] C[1] I[2] I[3] C[0] 4-LUT 4-LUT CLB 3-LUT O I[1] I[2] O CLB CLB I[3] C[3:0] CLB CLB

Pros Saves LUTS so you can use them for other things Drives Long lines (Might be faster than other types of routing) If you don t use them then is just a wasted resource Cons Decoded select signal (make sure only one select line is high at anytime!!!) Using up fast transmission long lines

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