Mixed Signal Design Simulation Manual

CADENCE Mixed Signal Design Simulation Manual Version 1.0 By Zheng Huan Qun February 2005 Department of Electrical and Computer Engineering National University of Singapore

ACKNOWLEDGMENTS The author would like to thank Mr Chen Jian Zhong who provided the sample database, and she would also wish to thank Dr Xu Yong Ping who gave support during the whole process. Zheng Huan Qun 18 February 2005 1

Table of Contents 1. Introduction... 3 1.1. Prerequisites... 3 1.2. Environment Setup... 3 1.3. Interface Elements for Mixed Signal Simulation... 4 1.3.1. Changing the property of a2d... 4 1.3.2. Changing the property of d2a... 5 2. A Mixed-Signal Schematic Simulation... 7 2.1. Creating a Configuration... 9 2.2. Setting up the Simulation Environment... 11 2.3. Viewing Options for Hierarchical Netlisting... 14 2.4. Displaying Partitions... 16 2.5. Starting Simulation... 17 3. A Mixed-Signal Pre-Layout Simulation... 19 3.1 Extracting Analog Parasitics... 19 3.1.1. Extracting parasitics... 19 3.1.2. Running LVS... 21 3.1.3. Creating an analog extracted view... 24 3.2. Setting Partitions... 25 3.2.1. Modifying the configuration file... 25 3.2.2. Setting up for simulation... 28 3.2.3. View the design partitions... 28 3.3. Estimated Digital Delays... 29 3.3.1. Loading the simulation state... 29 3.3.2. Setting up pre-layout estimation and the pearl timing analyzer... 30 3.4. Simulating the Design... 32 3.4.1. Simulation... 32 3.4.2. Comparing results... 33 4. A Mixed-Signal Post-Layout Simulation... 36 4.1. Creating a Mixed Extracted View... 36 4.1.1. Extraction... 36 4.1.2. Creating a config view... 38 4.1.3. Comparing views... 40 4.1.4. Building a mixed extracted view... 42 4.2. Block Level Approach to a Mixed-Signal Post-Layout Simulation... 44 4.2.1. Creating mixed extracted view for digital or mixed block(s)... 44 4.2.2. Modifying the configuration file... 45 4.2.3. Simulating the design... 47 4.3. Whole Design Approach to a Mixed-Signal Post-Layout Simulation... 50 2

1. Introduction The mixed signal schematic, pre-layout and post-layout simulations with the simulator of spectreverilog are described in this manual. The manual is especially edited for using AMS (austriamicrosystems) design kits. If you are using other design kits and it doesn t provide Verilog code and msps view for a digital primitive cell, you should know how to create verilog code and create a msps view for a digital primitive cell. 1.1. Prerequisites The prerequisites to use this manual are knowing how to use spectre and analog design environment, basic knowledge of verilog language, both the schematic and layout of design are ready, and the layout passes LVS checking. 1.2. Environment Setup To setup environment, do as follows on UNIX system. mkdir project_directory cd project_directory ams_cds tech c35b4 1 mode fb to start cadence (at 1 st time) ams_cds or ams_cds mode fb to start cadence (afterwards) open the file`.simrc` and locate the lines with change it as follows. 1 c35b4 is the type of technology used. 3

1.3. Interface Elements for Mixed Signal Simulation Cadence partitioning algorithm scans the entire design and determines if primitive instances are analog or digital. It then identifies signals connecting analog and digital primitives as mixed signals. Translation from the analog to digital domain or vice verse is required for mixed signal simulation. Therefore, mixed signals are described by translation devices called Interface Elements (IEs) during the netlisting process. The IEs translate signals between the analog and digital domains. Digital pins attached to mixed signals must be unidirectional to imply the direction of translation. A digital input pin implies translation from the analog to the digital domain (a2d), and a digital output pin implies translation from the digital to the analog domain (d2a), referring to figure 1. Analog Block N1 Input Digital Block N2 Output Analog Block a2d d2a Analog Block Digital Block Analog Block Figure 1 The IEs do not appear in the schematic and they use macromodels defined by a combination of CDF and the IE macromodel file. The IE cell macros are automatically inserted into the final siumulation netlist where needed. Users don t need to define the IE macromodel file as the design kits already provide. To simulate a mixed-signal design more accurately, users might want to change some parameters of the IE macromodel file. 1.3.1. Changing the property of a2d Referring to figure 2, an a2d conversion is defined by three parameters: v1, v0 and tx. To change them, open the IE Model Property Editor form by select Mixed-Signal Interface Elements Library in the configured schematic 2 window and set Model IO to input as shown below. Click Ok in the IE Model Property Editor form after changing. 2 It is opened through a config file. Please refer to sections 2.1 and 2.2 for details. 4

Figure 2 a2d conversion 1.3.2. Changing the property of d2a Referring to figure 3, a d2a conversion is defined by four parameters: VL, VH, TR and TF. To change them, open the IE Model Property Editor form by select Mixed-Signal Interface Elements Library in the configured schematic window and set Model IO to output as shown below. Click Ok in the IE Model Property Editor form after changing. 5

Figure 3 d2a conversion 6

2. A Mixed-Signal Schematic Simulation In this section, a mixed signal schematic simulation is described. The sample used is a one bit A-to-D converter. Referring to figures below, figure 4 shows the project library and there are four cells where mix_test is the top cell with analog blocks (Pre_amp1 and latch1) and digital block (mix_testdig). Figure 5 to figure 8 are the schematics of those cells. Figure 4 Project library: mix_sim Figure 5 Schematic of mix_test 7

Figure 6 Schematic of Pre-amp1 Figure 7 Schematic of latch1 Figure 8 Schematic of mix_testdig 8

Following the steps to do the mix-signal schematic simulation, details of the each step are described in sections 2.1 ~ 2.5. Creating a configuration Setting up the simulation environment Viewing options for Hierarchical Netlisting Displaying partitions Starting simulation 2.1. Creating a Configuration 1. Start cadence with ams_cds under project directory. 2. In the Library Manager, select File New Cell View. 3. Select Hierarchy-Editor as the tool, and complete the Create New File form as shown: The Library Name is the project library name and the Cell Name must be as same as that of top cell. 4. Click Ok. The Hierarchy Editor opens as well as a New Configuration form in front of it. 5. Type schematic in the View field of the New Configuration form. Click Use Template button. The Use Template form opens. 9

6. Choose spectreverilog as the name of template. Click Ok. 7. Change the Library List filed to the one you use mix_sim in the New Configuration form. Now, the New Configuration form should be as follows. 8. Click Ok. The Hierarchy Editor now displays the hierarchy for this design as shown below. 10

9. Click Save button in the Hierarchy Editor form to save the configuration. The config view appears in the Library Manager. 2.2. Setting up the Simulation Environment 1. In the Hierarchy Editor window, click Open. The mix_test schematic window appears. Note the additional phrase, Config: mix_sim mix_test config in the window title bar. This is the one so called the configured schematic window. 11

2. In the mix_test configured schematic window that you opened through the config view, select Tools Analog Environment. The Analog Design Environment window appears. 3. Use the Setup Simulator/Directory/Host function and set the simulator to spectreverilog. Click Ok in the Choosing Simulator/Directory/Host form. 12

4. Select Setup Model Libraries and ensure that the analog models are as same as follows. Click Ok in the Model Library Setup form. 5. Select Simulation Options Digital and ensure that the digital model is as same as below. Click Ok. 6. Choose an analysis in the way of using spectre. Here choose a Transient Analysis, and set the stop time to 400ns. 7. Execute Outputs To Be Plotted Select On Schematic to bring the schematic to the foreground for signal selection, which is as same as running spectre. Select the signals to plot after simulation, hitting the Esc key when done. Now, the simulation window is as follows. 13

8. To save state, click on Session Save State. The Saving State form appears. 9. Click Ok in the Saving State form. 2.3. Viewing Options for Hierarchical Netlisting 1. In the Analog Design Environment window, select Setup Environment. The Environment Options form appears. 14

2. Click the lone Verilog Netlist Option button. The Verilog HNL Netlisting Options form appears. 3. In the Verilog HNL Netlisting Options form, verify that the following settings appear. 4. Make sure that the Generate Pin Map option is on. 5. Note that the Generate Test Fixture Template field is set to Verimix. 6. Click Ok in the Verilog HNL Netlisting Options form. 7. Click Ok in the Environment Options form. 15

2.4. Displaying Partitions 1. In the mix_test configured schematic window, select Mixed Signal Display Partition Interactive. The Partition Display form appears. Make sure that the Show View Found option is active. Note the colors for analog, digital, and mixed. 2. Click Apply in the Partition Display form. 3. The schematic is partitioned as follows. Note the colors for analog, digital, and mixed again. 4. Click Cancel in the Partition Display form to remove the partitioning display. If you accidentally removed the Partition Display form, select Mixed Signal Display Partition Remove All to clear the partitioning display. Note: if your schematic is not partitioned successfully, you will not able to simulate your design. Check your Hierarchy Editor form and manage to let it partitioned successfully. 16

2.5. Starting Simulation 1. In the Analog Design Environment window, select Simulation Netlist Create. The Hierarchical Netlister begins to netlist the design. The following information appears in the CIW: Two separate windows appear which contain the complete analog and digital netlists. 2. In both the ~/Sim/mix_test/spectreVerilog/config/analog/input.scs and ~/Sim/mix_test/spectreVerilog/config/digital/input.scs windows, note the Interface Elements (IEs) 3 inserted as shown below. From the Analog Netlist: From the Digital Netlist: These allow the spectre and Verilog simulators to exchange information during simulation. 3. Choose File Close Window to close the netlist windows. 3 Please refer to section 1.3 if you want to change the property of IEs. 17

4. Select Simulation Run to start simulation. As the simulation starts, messages appear in the CIW, and two separate windows, spectre.out and verilog.out, appear too. 5. At the end of a successful simulation, the following appears in the CIW: If the simulation is not successful, you need to check the messages in the spectre.out and verilog.out. 6. Output waveforms appear as follows. 7. Close all windows and exit cadence. 18

3. A Mixed-Signal Pre-Layout Simulation In this section, a mixed-signal simulation with extracted analog parasitics and estimated prelayout digital parasitics is described. The sample used is as same as that of section 2. In addition, the layout of analog block is needed. The tasks to perform are summarized here, and the steps to complete them follow: Extracting analog parasitics, Setting partitions, Estimated digital delays, Simulating the design. 3.1 Extracting Analog Parasitics The analog parasitic extraction process consists of extracting parasitics, running LVS (layout versus schematic comparison for terminal mapping), and creating an analog extracted view. This process should be repeated for every analog block in your design where you want parasitics extracted. As there are two analog blocks in the sample, we shall create analog extracted view for both Pre-amp1 and latch1. 3.1.1. Extracting parasitics 1. Start cadence with ams_cds mode fb under the project directory. 2. Start the Library Manager from CIW by selecting Tools Library Manager. 3. From the Library Manager window, open the schematic and layout view of Pre-amp1 (or latch1). 19

4. From the menu bar in the layout window, select Verify Extract. The diva Extractor form appears. 5. On the Extractor form, turn on Join Nets With Same Name to ensure that nets with same name are automatically joined. 6. To select the parasitics to be extracted, click on Set Switches. The Set Switches form appears. 20

7. Choose capall and click Ok to close the Set Switches window. 8. Ensure that the Extractor form is filled in as shown. 9. Clock Ok to start the extraction process. When the extraction completes successfully, the following message appears in the CIW. 10. Close the Pre-amp1 (or latch1) layout window. Do not save changes. 3.1.2. Running LVS 1. In the Library Manager window, open the extracted view of Pre-amp1 (or latch1). 21

2. In the extracted view window, select Verify LVS. The LVS form appears, and the LVS Form Contents Different form may also appear. 3. Turn on the Form Contents in the LVS Form Contents Different form and click Ok. 4. Ensure that the fields of LVS form are filled in as shown below: Create Netlist schematic extracted Library 4 mix_sim mix_sim Cell 5 Pre-amp1(or latch1) Pre-amp1(or latch1) View schematic extracted The LVS form should appear as follows. 4 The library is the project library. 5 The Cell is the cell which you want to extract. 22

If the Create Netlist section of the form is not filled in as shown, do as follows to update. Click Sel by Cursor on the schematic side and click again on the schematic window. Click Sel by Cursor on the extracted side, and then click again on the layout extracted view window. 5. Click Run in the LVS form. The LVS program begins. 6. When the LVS process completes, click Ok in the Analysis Job Succeeded dialog box. 7. Click on the Info button in the LVS form. The Display Run Information form appears. 8. Click Log File in the Display Run Information form. A text window displays the log file and updates as the job runs. After successful completion of the LVS run, the log file displays information about the netlist comparison: 23

9. Select File Close Window to close the log file. 10. Click Cancel in the Display Run Information window. 3.1.3. Creating an analog extracted view To include the analog parasitics for simulation, you must first create an analog_extracted view. It can contain all or some of the parasitics that are found in an analog block. 1. In the LVS form, click Build Analog. The Build Analog Extracted View form appears. 2. In the Build Analog Extracted View form, turn on Include All as above. 3. Click Ok in the Build Analog Extracted View form. The analog_extracted view is built and contains all of the parasitics extracted for the analog block Pre-amp1 (or latch1). The CIW displays the information: 4. To close the LVS window, select Commands Close Window. The anlog_extracted view for the Pre-amp1 (or latch1) now appears in the Library Manager. With this view you will be able to run parasitic analysis simulation. 24

3.2. Setting Partitions In this section, you will modify the configuration file created in the mixed-signal schematic simulation, run simulation with analog_extracted view for analog block(s). 3.2.1. Modifying the configuration file 1. Open the Library Manager, and locate the top cell: mix_test and its config view. 2. Click the word config with your middle mouse button, and select Copy. The Copy View form appears. 3. Copy 6 the config view to a new view named config_fe 7. Set up your form like this. 6 This aims to keep the original configuration file and its simulation results. 7 You can use a unique name for the new view that also identifies it as a configuration file. 25

4. Click Ok in the Copy View form. 5. In the Library Manager, open the config_fe view of the mix_test cell. The Open Configuration or Top CellView form appears. 6. Select yes to open both the configuration and the Top CellView. 7. Click Ok. The configured schematic of mix_test opens, and the Hierarchy Editor window opens. 8. In the Hierarchy Editor window, put you cursor in the View Found section for the analog blocks (Pre-amp1 and latch1). Press and hold your right mouse to choose Set Cell View analog_extracted. 26

9. Choose View Update or click update icon in the Hierarchy Editor window. An Update Sync-up form might appear. Read it and click Ok. The configuration is updated. 10. The Hierarchy Editor window should be as follows. 27

3.2.2. Setting up for simulation 1. In the configured schematic window, select Tools Analog Environment. The Analog Design Environment window appears. 2. Make sure the simulator is set to spectreverilog. 3.2.3. View the design partitions 1. From the configured mix_test schematic window, select Mix-Signal Display Partition Interactive. 2. In the Partition Display form, turn on Show View Found and click Apply. The partitioning display appears. 28

3. Zoom in to view the configured schematic: the analog blocks are used with analog_extracted view and the digital blocks are used with schematic view. 4. Click Cancel in the Partition Display form to remove the partitioning display. 3.3. Estimated Digital Delays In this section, you prepare to simulate the design with pre-layout digital delay estimates. You need to load the state file of previous simulation, and then set up Pearl 8 to generate pre-layout digital delay estimates for simulation. 3.3.1. Loading the simulation state 1. In the Analog Design Environment simulation window, choose Session Load State. The Loading State form appears. 2. Verify that the simulator is set to spectreverilog. 3. In the State Name field, select state1. 4. Click Ok. The Analog Design Environment simulation window is as follows. 8 Pearl also generates post-layout digital delays. Refer to the Pearl User Guide for more information about using the Pearl analyzer. 29

5. Verify that the Verilog HNL Netlisting Options form is as below, referring to section 2.3. 3.3.2. Setting up pre-layout estimation and the pearl timing analyzer 9 1. From the Analog Design Environment window, select Simulation Options Mixed Signal. The Mixed Signal Options form appears. 9 Pearl requires two initialization files to run: pearl.cmd and gcfconstrains.gcf. 30

2. In the Digital Delays section, choose Estimate (Pre-Layout). The form expends to show additional buttons. 3. In the Mixed Signal Options form, click Command. The Command Options form appears. The information in this form is used in the pearl.cmd file. 4. Click Ok in the Command Options form. 31

5. In the Mixed Signal Options form, click Constraints. An editor window appears and it is used as gcfconstraints.gcf file. 6. Close the editor window. 7. In the Mixed Signal Options form, click Config. The SDF Annotator Config File form appears. 8. Click Ok in the SDF Annotator Config File form. 9. Click Ok in the Mixed Signal Options form. 3.4. Simulating the Design 3.4.1. Simulation 1. In the Analog Design Environment window, select Simulation Netlist Recreate. In a few moments, the analog and digital netlist appears. 2. In the Analog Design Environment window, select Simulation Run or click the Run Simulation icon. Upon successful completion of the simulation, the waveforms plot automatically. 32

3.4.2. Comparing results You can compare the mixed signal schematic simulation results with the current results. 1. In the Analog Design Environment window, select Results Printing/Plotting Options. 2. In the Setting Plotting Options form that appears, turn on the Overlay Plots as follows. 33

3. Click Ok in the Setting Plotting Options form. This setting maintains existing plots in the waveform window when new waveform appears from the current simulation. 4. In the Analog Design Environment window, select Results Select. A Select Results form appears 5. Select config which is saved in the mixed signal schematic simulation, and then click Ok. 6. Click the Plot Outputs icon in the Analog Design Environment window and watch the waveform window update to display results from both simulation. 34

7. Close all windows and exit cadence. 35

4. A Mixed-Signal Post-Layout Simulation In this section, the simulation of mixed-signal with both analog and digital parasitics is described. To fully experience mixed-signal parasitic simulation (MSPS), two simulations will be run. One is the block level approach and the other is whole design approach. For a mixed-signal post-layout simulation, the tasks to perform are summarized here, creating mixed extracted view (block-level), modifying the configuration file (top-level), and simulating the design (top-level). As modifying the configuration file and simulation design are described in section 3, in this section creating mixed extracted view is emphasized and users can follow the two simulations, block level approach and whole design approach, to experience the flow. 4.1. Creating a Mixed Extracted View To simulate a digital block or a mixed analog and digital block with parasitics, a mixed extracted view must be created. The steps to create a mixed extracted view are as follows. Extraction Creating a config view Comparing views Build a mixed extracted view To illustrate the procedure, the block of mix_testdig is used as an example. 4.1.1. Extraction 1. Start cadence with ams_cds mode fb under the project directory. 2. In the Library Manager, open the layout and schematic views of mix_testdig. 3. In the mix_testdig layout view window, select Verify MSPS Check Pins. The MSPS Check Pins form appears. 4. Click Ok in the MSPS Check Pins form. This runs a pin direction check between the layout and schematic views of a digital or a mixed analog and digital block. The following appears in the CIW. 36

5. In the layout view window, choose Verify Extract. The Extractor form appears. 6. Set up the Extractor form as follows. Set up the Extractor Method to macro cell. This stops extraction of digital cells below the top level of hierarchy. Click Join Nets With Same Name. Click the Set Switches button and choose capall. 7. Click Ok in the Extractor form. The extracted view is created. 37

4.1.2. Creating a config view Before running LVS on a digital block or a mixed analog and digital block, a config view must be created because a config view is used instead of schematic view when creating mixed_extracted view. 1. In the Library Manager, select File New Cell View... The Create New File form appears. 2. Set the form up as follows: Library Name: mix_sim 10 Cell Name: mix_testdig 11 View Name: config Tool: Hierarchy-Editor 3. Click Ok in the Create New File form. The Hierarchy Editor window opens as well as a New Configuration form in front of it. 10 This should be your project library. 11 This is the digital or the mixed analog and digital cell name. 38

4. Fill in the New Configuration form as follows. 5. Click Ok in the New Configuration form. The Hierarchy Editor now displays the hierarchy. 6. In the Hierarchy Editor form, select File Save or click the Save button to save the configuration. 39

4.1.3. Comparing views 1. Open the extracted view of mix_testdig. 2. From the extracted view window, choose Verify LVS. The LVS form appears. In addition, the LVS Form Contents Different form might appear as well. 3. Select Form Contents in the LVS Form Contents Different form, and click Ok. 4. Set up the LVS form as follows. Make sure that you use the config view under the schematic side of the LVS form. 40

5. In the LVS form, click Run to start LVS. When the process completes, click Ok in the Analysis Job Completed form. 6. Click Info to display the Display Run Information form. 7. Click Log File in the form. A log file of the LVS run appears. 41

8. To verify that the program succeeds, look for: the net-lists match. If it fails, read the message in the log file for information. 9. Close the log file. 10. In the Display Run Information box, click Cancel. 4.1.4. Building a mixed extracted view The build mixed extracted view process removes all digital parasitics and places them in an SPF file. Pearl used the SPF file to calculate digital delays and generate an SDF file which provides that digital delay information used during mixed-signal parasitics simulation. 1. On the LVS form, click Build Mixed. The Build Mixed Extracted View form appears. 42

2. Click Command in the Build Mixed Extracted View form. The Command Options form appears. 3. Click Ok in the Command Options form. 4. Click Constrains in the Build Mixed Extracted View form. An editor window appears. 5. Close the editor window. 43

6. Make sure that the Calculate button under Digital Delays is on, and the Include All button under Analog Parasitics is on. 7. Click Ok in the Build Mixed Extracted View form. The pearl analyzer runs in the background, and it completes when the following information appears in CIW. 8. The mixed_extracted view appears in the Library Manager window as follows. 9. Close all windows except the CIW and Library Manager windows. 4.2. Block Level Approach to a Mixed-Signal Post-Layout Simulation In this section, the mixed-signal post-layout simulation is described, where the mixed_extracted view of digital or mixed block(s) is used and the analog_extracted view of analog block(s) is used. The sample used is as same as previous one but the layout of both analog and digital block is needed. 4.2.1. Creating mixed extracted view for digital or mixed block(s) If you haven t got the mixed_extracted view of digital or mixed block(s) for your design, please follow the steps of section 4.1 to finish them. 44

4.2.2. Modifying the configuration file To keep the previous simulation results, we will copy the config_fe view of mix_test to config_msps, and then modify it. If you forgot how to do, please refer to section 3.2.1. 1. In the Library Manager, copy the config_fe view of the top cell: mix_test to a view called config_msps. 2. Go back to Library Manager and verify that the config_msps view exists in the View field. 3. In the Library Manager, open the config_msps view of the top cell: mix_test. The Open Configuration or Top CellView form appears. 4. Select yes to open both the Configuration and Top CellView. 45

5. Click Ok in the Open Configuration or Top CellView form 6. In the Hierarchy Editor window, do the following changes: View list: Stop list: Digital or Mixed blocks: Add in msps aulvs in front Change to msps aulvs Change to mixed_extracted view Keep in mind that the analog blocks must be analog_extracted view. 7. The Hierarchy Editor window should be look like this: 8. Click the Update icon to save changes. If an Update Sync-up form appears, read it and click Ok. 46

4.2.3. Simulating the design 1. In the configured mix_test schematic window, select Tool Analog Environment to start the simulation environment. 2. Verify that the simulator is set to spectreverilog. 3. Use the Load State function to load the state 1. The Analog Design Environment window looks like this. 4. Verify that the Verilog HNL Netlisting Options form is as below, referring to section 2.3. 47

5. In the Analog Design Environment window, select Simulation Options Mixed Signal. The Mixed Signal Options form appears. 6. In the Digital Delays section, select Use Existing (Layout). The form expands to include additional controls. 7. Verify that SDF From Mixed Extracted View is selected. This takes the SDF data from the mixed_extracted view. 8. Click Config that is next to the Edit SDF Annotator File. The SDF Annotator Config File form appears. 48

9. Set the MTM (delay) value to TYPICAL and click Ok. 10. Click Ok in the Mixed Signal Options form. 11. In the Analog Design Environment window, select Simulation Netlist and Run or click the Netlist and Run icon. Note the messages in the CIW which indicate that the SDF file is included in the digital netlist. 12. Upon successful completion of the simulation, the waveforms plot automatically. 13. To compare the results with the results of pre-layout simulation, select the results of config_fe, referring to section 3.4.2. 49

4.3. Whole Design Approach to a Mixed-Signal Post-Layout Simulation In the following simulation, a mixed_extracted view for the entire design is used. Before starting MSPS, the following lists should be ready entire design schematic, entire design layout, a testing cell or top cell for the entire design. Figure 9 to figure 11 show the example used in this section. Figure 9 Schematic of entire design: mix_test_whole 50

Figure 10 Layout of entire design: mix_test_whole Figure 11 Testing cell or top cell for the entire design: mix_test_whole_top 51

The steps to simulate the whole design are below. 1. Build a mixed_extracted view for the entire design: mix_test_whole, referring to section 4.1. 2. In the Library Manager, create a config view for the testing cell: mix_test_whole_top, referring to section 2.1. 3. Open both the config_msps2 and the configured schematic mix_test_whole_top windows. 4. Verify that the Hierarchy Editor is as follows. 52

Note: the stop list and view list should be as same as above. If not, change them and save the changes. 5. In the configured mix_test_whole_top schematic window, open the Analog Design Environment window. 6. Verify that the simulator is set to spectreverilog. 7. Use the Load State function to load state1 of cell mix_test or follow the steps of section 2.2 to set up the simulation environment. 53

8. Verify that the Verilog HNL Netlisting Options form is as below, referring to section 2.3. 9. In the Analog Design Environment window, select Simulation Options Mixed Signal. 10. In the Digital Delays section of the Mixed Signal Options form, click on Use Existing (Layout). The form expands. 54

11. Verify that the SDF From Mixed Extracted View is selected. 12. Click Config button that is next to the Edit SDF Annotator File. The SDF Annotator Config File form appears. 13. Verify that MTM is set to TYPICAL, and click Ok in the SDF Annotator Config File form, and click Ok in the Mixed Signal Options form. 14. In the Analog Design Environment window, click the Netlist and Run icon. The simulation starts and the waveforms appear after successful simulation. Note the message in the CIW which indicate that the SDF file is included in the digital netlist. 55

15. To comparing the results with that of block level approach, load the results of config_msps of cell: mix_test. 16. Close all windows and exit cadence. ------END------ 56