UNIT - V MEMORY P.VIDYA SAGAR ( ASSOCIATE PROFESSOR)
contents Memory: Introduction, Random-Access memory, Memory decoding, ROM, Programmable Logic Array, Programmable Array Logic, Sequential programmable devices. Register Transfer and Micro operations - Register Transfer Language, Register Transfer, Bus and Memory Transfers, Arithmetic Micro operations, Logic Micro operations, Shift Micro operations, Arithmetic Logic Shift Unit. 2
Introduction There are two types of memories that are used in digital systems: Random-access memory(ram): perform both the write and read operations. Read-only memory(rom): perform only the read operation. The read-only memory is a programmable logic device. Other such units are the programmable logic array(pla), the programmable array logic(pal), and the field-programmable gate array(fpga). 3
Array logic A typical programmable logic device may have hundreds to millions of gates interconnected through hundreds to thousands of internal paths. In order to show the internal logic diagram in a concise form, it is necessary to employ a special gate symbology applicable to array logic. 4
Random-Access Memory A memory unit stores binary information in groups of bits called words. 1 byte = 8 bits 1 word = 2 bytes The communication between a memory and its environment is achieved through data input and output lines, address selection lines, and control lines that specify the direction of transfer. 5
Content of a memory Each word in memory is assigned an identification number, called an address, starting from 0 up to 2k-1, where k is the number of address lines. The number of words in a memory with one of the letters K=210, M=220, or G=230. 64K = 216 2M = 221 4G = 232 6
Write and Read operations Transferring a stored word out of memory: Apply the binary address of the desired word to the address lines. Activate the read input. Commercial memory sometimes provide the two control inputs for reading and writing in a somewhat different configuration in table 7-1. 7
Static RAM SRAM consists essentially of internal latches that store the binary information. The stored information remains valid as long as power is applied to the unit. SRAM is easier to use and has shorter read and write cycles. Low density, low capacity, high cost, high speed, high power consumption. Dynamic RAM DRAM stores the binary information in the form of electric charges on capacitors. The capacitors are provided inside the chip by MOS transistors. The capacitors tends to discharge with time and must be periodically recharged by refreshing the dynamic memory. DRAM offers reduced power consumption and larger storage capacity in a single memory chip. 8 High density, high capacity, low cost, low speed, low power consumption.
Memory decoding The equivalent logic of a binary cell that stores one bit of information is shown below. Read/Write = 0, select = 1, input data to S-R latch Read/Write = 1, select = 1, output data from S-R latch 9
4X4 RAM There is a need for decoding circuits to select the memory word specified by the input address. During the read operation, the four bits of the selected word go through OR gates to the output terminals. During the write operation, the data available in the input lines are transferred into the four binary cells of the selected word. A memory with 2 k words of n bits per word requires k address lines that go into kx2 k decoder. 10
Coincident decoding A decoder with k inputs and 2k outputs requires 2k AND gates with k inputs per gate. Two decoding in a two-dimensional selection scheme can reduce the number of inputs per gate. 1K-word memory, instead of using a single 10X1024 decoder, we use two 5X32 decoders. address 11
Read-Only Memory A block diagram of a ROM is shown below. It consists of k address inputs and n data outputs. The number of words in a ROM is determined from the fact that k address input lines are needed to specify 2k words. 12
Construction of ROM Each output of the decoder represents a memory address. Each OR gate must be considered as having 32 inputs. A 2k X n ROM will have an internal k X 2k decoder and n OR gates. 13
Truth table of ROM A programmable connection between to lines is logically equivalent to a switch that can be altered to either be close or open. Intersection between two lines is sometimes called a cross-point. 14
Programming the ROM In Table 7-3, 0 no connection 1 connection Address 3 = 10110010 is permanent storage using fuse link 1 0 1 1 0 0 1 0 X : means connection 15
Example Design a combinational circuit using a ROM. The circuit accepts a 3-bit number and generates an output binary number equal to the square of the input number. Derive truth table first 16
Example 17
Types of ROMs The required paths in a ROM may be programmed in four different ways. Mask programming: fabrication process Read-only memory or PROM: blown fuse /fuse intact Erasable PROM or EPROM: placed under a special ultraviolet light for a given period of time will erase the pattern in ROM. Electrically-erasable PROM(EEPROM): erased with an electrical signal instead of ultraviolet light. 18
Combinational PLDs A combinational PLD is an integrated circuit with programmable gates divided into an AND array and an OR array to provide an AND-OR sum of product implementation. PROM: fixed AND array constructed as a decoder and programmable OR array. PAL: programmable AND array and fixed OR array. PLA: both the AND and OR arrays can be programmed. 19
Combinational PLDs 20
PLA F1 = AB +AC+A BC F2 = (AC+BC) 21
Example 7-2 Implement the following two Boolean functions with a PLA: F1(A, B, C) = (0, 1, 2, 4) F2(A, B, C) = (0, 5, 6, 7) The two functions are simplified in the maps of Fig.7-15 22
PLA table by simplifying the function Both the true and complement of the functions are simplified in sum of products. We can find the same terms from the group terms of the functions of F1, F1,F2 and F2 which will make the minimum terms. F1 = (AB + AC + BC) F2 = AB + AC + A B C 23
PLA implementation AB AC BC A B C 24
Programmable Array Logic The PAL is a programmable logic device with a fixed OR array and a programmable AND array. 25
Example w(a, B, C, D) = (2, 12, 13) x(a, B, C, D) = (7, 8, 9, 10, 11, 12, 13, 14, 15) y(a, B, C, D) = (0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15) z(a, B, C, D) = (1, 2, 8, 12, 13) Simplifying the four functions as following Boolean functions: w = ABC + A B CD x = A + BCD w = A B + CD + B D w = ABC + A B CD + AC D + A B C D = w + AC D + A B C D 26
PAL Table z has four product terms, and we can replace by w with two product terms, this will reduce the number of terms for z from four to three. 27
PAL implementation w A x B y C z D 28
Fuse map for example 29
Sequential Programmable Devices Sequential (or simple) Programmable Logic Device (SPLD) Complex Programmable Logic Device (CPLD) Field Programmable Gate Array (FPGA) 30
Macrocell Fig.7-19 shows the logic of a basic macrocell. The AND-OR array is the same as in the combinational PAL shown in Fig.7-16. 31
CPLD Fig.7-20 shows a general configuration of a CPLD. It consists of multiple PLDs interconnected through a programmable switch matrix. 8 to 16 macrocell per PLD. 32
FPGA FPGA is a VLSI circuit that can be programmed in the user s location. A typical FPGA logic block consists of look-up tables, multiplexers, gates, and flip-flops. Look-up table is a truth table stored in a SRAM and provides the combinational circuit functions for the logic block. 33
REGISTER TRANSFER AND MICROOPERATIONS Register Transfer Language Register Transfer Bus and Memory Transfers Arithmetic Microoperations Logic Microoperations Shift Microoperations Arithmetic Logic Shift Unit
SIMPLE DIGITAL SYSTEMS Combinational and sequential circuits can be used to create simple digital systems. These are the low-level building blocks of a digital computer. Simple digital systems are frequently characterized in terms of the registers they contain, and the operations that they perform. Typically, What operations are performed on the data in the registers What information is passed between registers
BASIC COMPUTER REGISTERS Registers in the Basic Computer 11 0 PC 15 0 IR 15 0 TR 7 0 7 0 OUTR 11 0 AR INPR Memory 4096 x 16 15 0 DR 15 0 AC CPU List of BC Registers DR 16 Data Register Holds memory operand AR 12 Address Register Holds address for memory AC 16 Accumulator Processor register IR 16 Instruction Register Holds instruction code PC 12 Program Counter Holds address of instruction TR 16 Temporary Register Holds temporary data INPR 8 Input Register Holds input character OUTR 8 Output Register Holds output character
MICROOPERATIONS (1) The operations on the data in registers are called microoperations. The functions built into registers are examples of microoperations Shift Load Clear Increment
MICROOPERATIONS (2) An elementary operation performed (during one clock pulse), on the information stored in one or more registers Registers (R) ALU (f) 1 clock cycle R f (R, R) f: shift, load, clear, increment, add, subtract, complement,and, or, xor,
REGISTER TRANSFER LEVEL Viewing a computer, or any digital system, in terms of Set of registers and their functions is called as the register transfer level. This is because we re focusing on The system s registers The data transformations in them, and The data transfers between them. Registers + Operations performed on the data stored in them = Digital Module
REGISTER TRANSFER Copying the contents of one register to another is a register transfer A register transfer is indicated as R2 R1 In this case, the contents of register R1 are copied (loaded) into register R2 A simultaneous transfer of all bits from the source R1 to the destination register R2, during one clock pulse Note that this is non-destructive; i.e. the contents of R1 are not altered by copying (loading) them to R2 A register transfer such as R3 R5 Implies that the digital system has the data lines from the source register (R5) to the destination register (R3) Parallel load in the destination register (R3) Control lines to perform the action
SIMULTANEOUS OPERATIONS If two or more operations are to occur simultaneously, they are separated with commas P: R3 R5, MAR IR Here, if the control function P = 1, load the contents of R5 into R3, and at the same time (clock), load the contents of register IR into register MAR
REGISTER TRANSFER LANGUAGE Rather than specifying a digital system in words, a specific notation is used, register transfer language For any function of the computer, the register transfer language can be used to describe the (sequence of) microoperations Register transfer language A symbolic language A convenient tool for describing the internal organization of digital computers Can also be used to facilitate the design process of digital systems.
Register Transfer Language cont. The internal hardware organization of a digital computer is defined by specifying: The set of registers it contains and their function The sequence of microoperations performed on the binary information stored in the registers The control that initiates the sequence of microoperations Registers + Microoperations Hardware + Control Functions = Digital Computer Register Transfer Language (RTL) : a symbolic notation to describe the microoperation transfers among registers Next steps: Define symbols for various types of microoperations, Describe the hardware that implements these microoperations 43
DESIGNATION OF REGISTERS Registers are designated by capital letters, sometimes followed by numbers (e.g., A, R13, IR) Often the names indicate function: MAR PC IR - memory address register - program counter - instruction register R1: processor register SR: Status Register Registers and their contents can be viewed and represented in various ways A register can be viewed as a single entity: MAR Registers may also be represented showing the bits of data they contain
BLOCK DIAGRAM OF A REGISTER The individual flip-flops in an n-bit register are numbered in sequence from 0 to n-1 (from the right position toward the left position) R1 7 6 5 4 3 2 1 0 Register R1 Showing individual bits A block diagram of a register Other ways of drawing the block diagram of a register: 15 0 PC Numbering of bits Upper byte 15 PC(H) 8 7 PC(L) 0 Lower byte 45 Partitioned into two parts
Register Transfer cont. Information transfer from one register to another is described by a replacement operator: R2 R1 This statement denotes a transfer of the content of register R1 into register R2 The transfer happens in one clock cycle The content of the R1 (source) does not change The content of the R2 (destination) will be lost and replaced by the new data transferred from R1 We are assuming that the circuits are available from the outputs of the source register to the inputs of the destination register, and that the destination register has a parallel load capability Conditional transfer occurs only under a control condition Representation of a (conditional) transfer P : R2 R1 A binary condition (P equals to 0 or 1) determines when the transfer occurs The content of R1 is transferred into R2 only if P is 1 46
CONTROL FUNCTIONS Often actions need to only occur if a certain condition is true This is similar to an if statement in a programming language In digital systems, this is often done via a control signal, called a control function If the signal is 1, the action takes place This is represented as: P: R2 R1 Which means if P = 1, then load the contents of register R1 into register R2, i.e., if (P = 1) then (R2 R1)
Register Transfer cont. Hardware implementation of a controlled transfer: P : R2 R1 Block diagram: Control Circuit P Load R2 Clock n R1 t t+1 Timing diagram Clock Load Transfer occurs here Synchronized with the clock 48
Register Transfer cont. Basic Symbols for Register Transfers Symbol Description Examples Letters & numerals Denotes a register MAR, R2 Parenthesis ( ) Denotes a part of a register R2(0-7), R2(L) Arrow Denotes transfer of information R2 R1 Comma, Separates two microoperations R2 R1, R1 R2 Colon : Denotes termination of control function P: 49
Bus and Memory Transfers Paths must be provided to transfer information from one register to another A Common Bus System is a scheme for transferring information between registers in a multiple-register configuration A bus: set of common lines, one for each bit of a register, through which binary information is transferred one at a time Control signals determine which register is selected by the bus during each particular register transfer 50
Bus and Memory Transfers Register A Register B Register C Register D Bus lines Register D 3 2 1 0 Register C 3 2 1 0 Register B 3 2 1 0 Register A 3 2 1 0 D 3 D 2 D 1 D 0 C 3 C 2 C 1 C 0 B 3 B 2 B 1 B 0 A 3 A 2 A 1 A 0 D 3 C 3 B 3 A 3 D 2 C 2 B 2 A 2 D 1 C 1 B 1 A 1 D 0 C 0 B 0 A 0 3 2 1 0 MUX3 S 0 S 1 3 2 1 0 MUX2 S 0 S 1 3 2 1 0 MUX1 S 0 S 1 3 2 1 0 MUX0 S 0 S 1 4-Line Common Bus 51
Bus and Memory Transfers The transfer of information from a bus into one of many destination registers is done: By connecting the bus lines to the inputs of all destination registers and then: activating the load control of the particular destination register selected We write: R2 C to symbolize that the content of register C is loaded into the register R2 using the common system bus It is equivalent to: BUS C, (select C) R2 BUS (Load R2) 52
Bus and Memory Transfers: Three-State Bus Buffers A bus system can be constructed with three-state buffer gates instead of multiplexers A three-state buffer is a digital circuit that exhibits three states: logic-0, logic-1, and highimpedance (Hi-Z) Three-State Buffer Control input C C=1 Normal input A Output B Buffer A B A B C=0 A Open Circuit B A B 53
Bus and Memory Transfers: Three-State Bus Buffers cont. Select Enable S 1 S 0 2 4 Decoder 0 1 2 3 A 0 E Bus line for bit 0 B 0 C 0 Bus line with three-state buffer (replaces MUX0 in the previous diagram) D 0 54
Bus and Memory Transfers: Memory Transfer Memory read : Transfer from memory Memory write : Transfer to memory Data being read or wrote is called a memory word (called M)- (refer to section 2-7) It is necessary to specify the address of M when writing /reading memory This is done by enclosing the address in square brackets following the letter M Example: M[0016] : the memory contents at address 0x0016 Assume that the address of a memory unit is stored in a register called the Address Register AR Lets represent a Data Register with DR, then: Read: DR M[AR] Write: M[AR] DR 55
MEMORY TRANSFERS Bus and Memory Transfers AR Memory unit Read Write DR Memory read micro-op: DR M ( DR M[AR] ) Memory write micro-op: M DR ( M[AR] DR ) Summary of Register Transfer Microoperations A B Transfer content of reg. B into reg. A AR DR(N) A constant ABUS R1, R2 ABUS AR DR M[AR] DR M[AR] M[AR] DR Transfer content of N bits portion of reg. DR into reg. AR Transfer a binary constant into reg. A Transfer content of R1 into bus A and, at the same time, Transfer content of bus A into R2 Address register Data register Memory word specified by reg. AR Memory read operation: transfers content of memory word specified by AR into DR Memory write operation: transfers content of DR into memory word specified by AR
Arithmetic Microoperations ARITHMETIC MICROOPERATIONS Four types of microoperations - Register transfer microoperations - Arithmetic microoperations - Logic microoperations - Shift microoperations * Summary of Arithmetic Micro-Operations R3 R1 + R2 R3 R1 - R2 R2 R2 R2 R2 + 1 R3 R1 + R2 + 1 R1 R1 + 1 R1 R1-1 Contents of R1 plus R2 transferred to R3 Contents of R1 minus R2 transferred to R3 Complement the contents of R2 2's complement the contents of R2 (negate) subtraction Increment Decrement
BINARY ADDER / SUBTRACTOR / INCREMENTER B3 A3 B2 A2 B1 A1 B0 A0 Binary Adder FA C3 FA C2 FA C1 FA C0 C4 S3 S2 S1 S0 Binary Adder-Subtractor B3 A3 B2 A2 B1 A1 B0 A0 M FA C3 FA C2 FA C1 FA C0 C4 S3 Binary Incrementer A3 S2 A2 S1 A1 S0 A0 1 x HA y x HA y x HA y x HA y C S C S C S C S 58 C4 S3 S2 S1 S0
Half Adder/Full Adder Half Adder x y c s 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0 Full Adder x y c n-1 c n s 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 x 0 0 1 0 c = xy c n y 0 1 1 1 c n-1 s = xy + x y = x y x 0 1 0 1 c n = xy + xc n-1 + yc n-1 = xy + (x y)c n-1 s y 1 0 1 0 c n-1 x y c s x y S s = x y c n-1 +x yc n-1 +xy c n-1 +xyc n-1 = x y c n-1 = (x y) c n-1 c n-1 c n 59
Arithmetic Microoperations Binary Adder B 3 A 3 B 2 A 2 B 1 A 1 B 0 A 0 C 3 C 2 FA FA FA FA C 0 C 1 C 4 S 3 S 2 S 1 S 0 4-bit binary adder (connection of FAs) 60
Arithmetic Microoperations Binary Adder-Subtractor B 3 A 3 B 2 A 2 B 1 A 1 B 0 A 0 M FA C 3 FA C 2 FA C 1 FA C 0 C 4 S 3 S 2 S 1 S 0 4-bit adder-subtractor 61
Arithmetic Microoperations Binary Adder-Subtractor For unsigned numbers, this gives A B if A B or the 2 s complement of (B A) if A < B (example: 3 5 = -2= 1110) For signed numbers, the result is A B provided that there is no overflow. (example : -3 5= -8) 1101 1011 + 1000 C 3 C 4 V = 1, if overflow 0, if no overflow Overflow detector for signed numbers 62
Arithmetic Microoperations Binary Incrementer A 3 A 2 A 1 A 0 1 x y x y x y x y HA HA HA HA C S C S C S C S C 4 S 3 S 2 S 1 S 0 4-bit Binary Incrementer Binary Incrementer can also be implemented using a counter A binary decrementer can be implemented by adding 1111 to the desired register each time! 63
Arithmetic Microoperations Arithmetic Circuit This circuit performs seven distinct arithmetic operations and the basic component of it is the parallel adder The output of the binary adder is calculated from the following arithmetic sum: D = A + Y + Cin A 0 1 0 S 1 S 0 1 0 S 1 S 0 1 0 S 1 S 0 1 0 S 1 S 0 B 3 B 3 A 3 B 2 B 2 A 2 B 1 B 1 A 1 B 0 B 0 3 2 1 0 S 1 S 0 4 1 MUX 3 2 1 0 S 1 S 0 4 1 MUX 3 2 1 0 S 1 S 0 4 1 MUX 3 2 1 0 S 1 S 0 4 1 MUX Figure A Y 3 FA X 3 C 3 Y 2 FA X 2 C 2 Y 1 FA X 1 C 1 Y 0 FA X 0 C in C out D 3 D 2 D 1 D 0 64 4-bit Arithmetic Circuit
ARITHMETIC CIRCUIT Cin S1 S0 A0 B0 A1 B1 A2 B2 A3 B3 0 1 S1 S0 0 4x1 1 2 MUX 3 S1 S0 0 1 2 3 S1 S0 0 1 2 3 4x1 MUX 4x1 MUX S1 S0 0 4x1 1 2 MUX 3 X0 C0 FA Y0 C1 X1 C1 FA Y1 C2 X2 C2 FA Y2 C3 X3 C3 FA Y3 C4 D0 D1 D2 D3 Cout 65 S1 S0 Cin Y Output Microoperation 0 0 0 B D = A + B Add 0 0 1 B D = A + B + 1 Add with carry 0 1 0 B D = A + B Subtract with borrow 0 1 1 B D = A + B + 1 Subtract 1 0 0 0 D = A Transfer A 1 0 1 0 D = A + 1 Increment A 1 1 0 1 D = A - 1 Decrement A 1 1 1 1 D = A Transfer A
LIST OF LOGIC MICROOPERATIONS List of Logic Microoperations - 16 different logic operations with 2 binary vars. - n binary vars functions 2 2 n Truth tables for 16 functions of 2 variables and the corresponding 16 logic micro-operations However, most systems only implement four of these AND ( ), OR ( ) XOR ( ), Complement/NOT x 0 0 1 1 y 0 1 0 1 Boolean Function Micro- Operations Name 0 0 0 0 F0 = 0 F 0 Clear 0 0 0 1 F1 = xy F A B AND 0 0 1 0 F2 = xy' F A B 0 0 1 1 F3 = x F A Transfer A 0 1 0 0 F4 = x'y F A B 0 1 0 1 F5 = y F B Transfer B 0 1 1 0 F6 = x y F A B Exclusive-OR 0 1 1 1 F7 = x + y F A B OR 1 0 0 0 F8 = (x + y)' F A B) NOR 1 0 0 1 F9 = (x y)' F (A B) Exclusive-NOR 1 0 1 0 F10 = y' F B Complement B 1 0 1 1 F11 = x + y' F A B 1 1 0 0 F12 = x' F A Complement A 1 1 0 1 F13 = x' + y F A B 1 1 1 0 F14 = (xy)' F (A B) NAND 1 1 1 1 F15 = 1 F all 1's Set to all 1's 66
APPLICATIONS OF LOGIC MICROOPERATIONS Logic microoperations can be used to manipulate individual bits or a portions of a word in a register Consider the data in a register A. In another register, B, is bit data that will be used to modify the contents of A Selective-set Selective-complement A A + B A A B Selective-clear A A B Mask (Delete) Clear Insert Compare... A A B A A B A (A B) + C A A B 67
Logic Microoperations HARDWARE IMPLEMENTATION OF LOGIC MICROOPERATIONS Question: Draw the digital circuit that performs the following logical operations between reg. A and reg. B(draw the circuit for one bit), then list the circuit function table: (AND, OR, XOR and Complement). 0
Logic Microoperations Hardware Implementation cont. A i S 1 S 0 4 1 MUX S 1 S 0 Output Operation 0 0 E = A B XOR B i 0 0 1 E = A B OR 1 E i 1 0 E = A B AND 1 1 E = A Complement 2 3 This is for one bit i 69
SHIFT MICROOPERATIONS Shifts - Logical shift : shift in a 0 into the extreme flip-flop - Circular shift : circulates the bits of the register around the two ends - Arithmetic shift : shifts a signed number (shift with sign extension) Left shift -> multiplied by 2 Right shift -> divided by 2 Arithmetic shifts for signed binary numbers - Arithmetic shift-right Sign bit R n-1 R n-2 R 1 R 0 - Arithmetic shift-left Overflow V = R n-1 R n-2 Shift Micro-Operations Symbol R shl R R shr R R cil R R cir R R ashl R R ashr R Description Shift-left register R Shift-right register R Circular shift-left register R Circular right-shift register R Arithmetic shift-left register R Arithmetic shift-right register R
Shift Microoperations cont. Example: Assume R1=11001110, then: Arithmetic shift right once : R1 = 11100111 Arithmetic shift right twice : R1 = 11110011 Arithmetic shift left once : R1 = 10011100 Arithmetic shift left twice : R1 = 00111000 Logical shift right once : R1 = 01100111 Logical shift left once : R1 = 10011100 Circular shift right once : R1 = 01100111 Circular shift left once : R1 = 10011101 An 8-bits register R ahs the following value: 11001010, find the value of R after performing the following shifts: 71
Shift Microoperations Hardware Implementation cont. Serial Input I R A 3 A 2 A 1 A 0 Serial Input I L S 1 0 S 1 0 S 1 0 S 1 0 MUX MUX MUX MUX Select 0 for shift right 1 for shift left H 3 H 2 H 1 H 0 4-bit Combinational Circuit Shifter 72
Arithmetic Logic Shift Unit Instead of having individual registers performing the microoperations directly, computer systems employ a number of storage registers connected to a common operational unit called an Arithmetic Logic Unit (ALU) S 3 S 2 S 1 S 0 C i S3 S2 S1 S0 0 0 0 0 Cin 0 Operation F = A Function Transfer A 0 0 0 0 1 F = A + 1 Increment A 0 0 0 1 0 F = A + B Addition 0 0 0 1 1 F = A + B + 1 Add with carry 0 0 1 0 0 F = A + B Subtract with borrow 0 0 1 0 1 F = A + B + 1 Subtraction 0 0 1 1 0 F = A - 1 Decrement A 0 0 1 1 1 F = A Transfer A 0 1 0 0 X F = A Λ B AND 0 1 0 1 X F = A V B OR 0 1 1 0 X F = A B XOR 0 1 1 1 X F = A Complement A 1 0 X X X F = shr A Shift right A into F 1 1 X X X F = shl A Shift left A into F B i A i One stage of arithmetic circuit (Fig.A) C i+1 One stage of logic circuit (Fig.B) D i E i Select 0 1 2 3 4 1 MUX F i A i+1 A i-1 shr shl One stage of ALU 73