HOW TECHNOLOGY R&D LEADERSHIP BRINGS A COMPETITIVE ADVANTAGE FOR MULTIMEDIA CONVERGENCE Technology Platform Segmentation HP LP 2 1
Technology Platform KPIs Performance Design simplicity Power leakage Cost of ownership Area scaling 3 Technology R&D/MFG Leadership Brings 2
ST Business Segment Overview Automotive, Consumer, Computer & Communication Infrastructure ( ACCI ) Wireless 50/50 JV with Ericsson Major Product Lines Home Entertainment & Displays Computer & Communication Infrastructure Industrial and Multisegment Sector ( IMS ) Automotive Products Group Analog, Power and MEMS Microcontrollers, Memories and Smartcards Products Major Customers 5 Wireless: multi-purpose Products 616May -11 3
Phones : High Performance @ Low Power Nova A9600 (28 nm) dual core Eagle A15 at 2.5 GHz + 20X graphics improvement * sampling 2011. Nova A9500 (45 nm) dual-core A9 @ 1.2 GHz + 20% graphics improvement* Available Nova A9540 (32 nm) dual-core A9 @ 1.85 GHz + 4X graphics improvement* Sampling 2011. 7 ST/Consumer relentless integration 8 4
ST/ Networking ASICs A growing SOC integration / Power Challenge 50+ Mgate 400-500 mm² >1GHz 20-40 Mgate 200-400 mm² 5-20 Mgate 100-200 mm² 5 Mgate 50-100 mm² 90nm 100-250MHz 5-10W 2007-0808 3-6GBps 65nm LP & LPGP 200-500MHz 15-70W 2009-10 6-10Gbps 32nm LPH 300-600MHz 10-80W 2011 10-14Gbps14Gbps 28nm LPG 400-900MHz 10-90W 2012 14-25Gbps 20nm 2013+ 25+ Gbps 9 The ST Technology R&D Model 10 5
Value-Chain Management : Technology Innovation 1/3 11 Value-Chain Management : Technology Operations 2/3 6
ISDA MANUFACTURING SYNC 3/3 Electrical Synchronization of partner fabs to IBM Parametrical equivalence, GDS2-level JDA between IBM and partners on 32LP Bulk and 28LP. Program started 2H09 (28LP), end DEC2011. IP circuits Equivalence Direct validation between ST & foundry, not in Fabsync Parametrical Equivalence Equivalence to model Model to silicon correlation In line Cp/Cpk Equivalence Metrology (SEMCD, Overlay, thin films, material composition) matching Test vehicle Common modeling macros Common electrical monitoring Process FEOL & BEOL critical process steps, Construction Analysis 13 Yield Learning D 0 Trend ST/Crolles 2.5 2 D0 90nm D0 65nm D0 45nm D0 Poisson (Def/cm²) 1.5 1 0.5 0 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 05 05 06 06 06 06 07 07 07 07 08 08 08 08 09 09 09 09 10 10 10 10 11 11 7
28nm ST Proprietary Process Options 28LP/G process embedded DRAM option Nitride Elec2 metal Cu Elec1-2 metal MIM High-K Low-K High-K SiO2 integrated decoupling capacitors for power integrity 40nm/28nm SOC Design flow: high speed, low power Chip RTL Top level Prototyping & Floorplan OA db System In Package Physical Units Implementation complex SoC example with high speed core and low power features Chip Level Assembly Sign--Off Sign GDS2 Subsystem Packaging infrastructure 16 8
28nm ASIC Design flow: Million Gates Capacity Hierarchical Flow for Complex Devices Specialized Clock Distribution Strategy Full Chip Hierarchical Analysis 17 Enabling performance race on products : STE 32nm 1.5GHz Low Power A9 Core L1 Cache designed to reach 1.8Ghz High Density L2 cache designed for 0.6 V Retention Faster pipelined Memory BIST Architecture High Performance Clock Generator Fast FF library designed for improving R2R performance in critical paths Dedicated algorithms for Memory Test in 32/28nm Several IP/Lib Patents Pending Power Switches: Peripheral Switches and Distributed Switches for best Vdrop. 18 9
Enabling High speed cores in 28LP @1.5GHz dual A9 experience >>1.5GHz quad A15 19 V dd Scaling and energy efficiency Scaling driven by process technology (T ox ) Energy Efficient Design for +/- nominal V DD 10
V dd Scaling and energy efficiency Keeping leakage under control 28nm FDSOI: Speed Projection the next speed booster 11
Lithography Scaling Reducing k 1 does not come for free! Transistor Architecture Trends 24 12
Main candidates after bulk are FinFET and FDSOI: FDSOI FinFET Strengths Risk - 2D (planar) process -Electrostaticcontrol - Compatibility with conventional «performance boosters» -Double gate : Electrostatic control -Process complexity (3D) -Compatibility with conventional «performanceboosters» 25 3D/Heterogeneous Integration of Wide-IO DRAM Benefits: Low-Power DRAM/SOC data connexion Challenges: cost, thermal management, Test, Supply Chain Photonics on Silicon Copper wire technology not able to sustain such data rates Photonics on silicon technology allows die to die and within die optical communication CMOS wafer P F A C D In P so ur ce M o d u l a t o r transistors A W G G e P D metal interconnects 26 13
ST Technology Leadership ST R&D cooperative model allows leveraged capture of technology innovation and risk mitigation ST leadership in technology enables differentiated / competitive product positioning through: Device Integration Device add-on for Derivatives / Analog Design Enablement Specific process modules for best device performance Fast yield learning cycle time techniques and a full multi sourcing supply-chain efficiency. 27 SOC CMOS Application Trends : Summary SOC Applications require high-performance energy-efficient Processing Units (CPUs, GPUs, ) : Wireless Consumer Automotive Computer Peripherals ST s 32/28nm LP / Design Platform at state-of-the-art Process optimizations, above industry leading ISDA HKMG 32nm Library/IP design CAD Flow/ Sign-off optimization Application-driven Partnerships are key to optimize R&D investment Process, IP, SOC Design, EDA 28 14