CompE 270 Digital Systems - 5 Programmable Logic Ken Arnold Objective Application Specific ICs Introduce User Programmable Logic Common Architectures Programmable Array Logic Address Decoding Example Development Process and Tools Copyright 2010 Ken Arnold 1 Copyright Ken Arnold 2 Application Specific Chips An ASIC is a user defined chip Application Specific Integrated Circuit Design Fixed at Time of Manufacture Full Custom - designed from scratch High Volume Standard Products like ups Standard Cell - building blocks are cells Gate Arrays waiting for interconnect layer Field Programmable Blank Slate Design Programmable AFTER manufacture PLDs, CPLDs, FPGAs Copyright Ken Arnold 3 User Programmable Logic User Programmable Logic Devices PLD (Programmable Logic Devices) Fabricated Blank - Programmed before use Use non-volatile memory technologies like Flash, EE PLA - Programmable Logic Array PAL - Programmable Array Logic (TM of AMD) CPLD (Complex PLDs) have multiple SOP Blocks FPGA (Field Programmable Gate Array) Array of Logic Modules or Blocks Larger than CPLDs More flexible than CPLDs Copyright Ken Arnold 4 Copyright 1998 Ken Arnold 1
Programmable Logic Intro PLD/CPLD implements SOP Implements Logic Equations: ex: F =AB + CDE + /C Storage Technologies Used: Fuse Link (original PLA, PAL) EPROM (Flash PLDs, Complex PLDs) EEPROM (GALs) SRAM used in some FPGAs Copyright Ken Arnold 5 PLD/CPLD Architectures PLA Two levels of logic AND/OR 2 Arrays - One each for AND and OR Both Arrays User Programmable PAL AND/OR only 1 programmable array Programmable AND gate input connections Fixed OR gate input connections PROM - Programmable OR Array Fixed AND array (address decode) Copyright Ken Arnold 6 Logic Shorthand Notation Simplified PAL Diagram Copyright Ken Arnold 7 Copyright Ken Arnold 8 Copyright 1998 Ken Arnold 2
Using PROM as PLD PLA Organization 2 n Product Lines Copyright Ken Arnold 9 Copyright Ken Arnold 10 PAL Organization PLD "Fuse" Programming Copyright Ken Arnold 11 Copyright Ken Arnold 12 Copyright 1998 Ken Arnold 3
PAL Device Numbering PAL Part Number example: 16L8 Number of Inputs to Array - 16 Type of output - Active Low Number of outputs - 8 Other Output Types: Hi, Registered, XOR, Versatile Outputs often fed back to inputs for sequential logic fundtions Copyright Ken Arnold 13 FPGA Architectures Arrays of logic blocks Logic Blocks, LUTs (Look Up Tables), F-Fs I/O Pad Blocks Interconnects (Programmable Wires ) Optional: Memory: SRAM, FIFO, ROM DSP blocks like Multiplier-Accumulators CPU IP (Intellectual Property) Cores Copyright 2010 Ken Arnold 14 PLD Development Tools Schematic Entry Assemblers (PALASM, ABEL, CUPL) Low Level or Boolean Equation Input Convert Logic Equations to Fuse Maps Fuse map is used to program the PLD Compilers (Verilog, VHDL, System C) High Level Design Definition Language Generates the Equations and Fuse Maps Other PLD Tools Test Vectors Provides Functional Verification Test Vector = Test Pattern Predetermined Inputs to Device Compared with Expected Outputs May Be Generated Automatically, using: Test Vector Generator Software Maximizes Probability of Detecting Faults Copyright Ken Arnold 15 Copyright Ken Arnold 16 Copyright 1998 Ken Arnold 4
Applications Glue Logic Address Decoding Logic Enable Memory or I/O Devices I/O Interface Can Incorporate Tri-state Buffer/Latch High Speed Sequential Logic Preprocess Signals that are too fast for CPU Sort of a fast Nano-controller Summary User Programmable Logic PROM, PLA, PAL Survey of Architectures Address Decoding Application Example Development Tools and Process Other Applications Copyright Ken Arnold 17 Copyright Ken Arnold 18 Questions Which type of programmable logic device has: Programmable AND array, Fixed OR array? Fixed AND, programmable OR array? Both Programmable AND and OR arrays? What type of the three can implement *any* function of its inputs? How does an FPGA differ from a CPLD? What does a logic assembler or compiler do? Copyright Ken Arnold 19 Copyright 1998 Ken Arnold 5