LSN 1 Digital Design Flow for PLDs
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1 LSN 1 Digital Design Flow for PLDs ECT357 Microprocessors I Department of Engineering Technology
2 LSN 1 Programmable Logic Devices Functionless devices in base form Require programming to operate The logic function of the device is programmed by the user Replaces fixed function ICs and associated hard wiring High density of logic circuits
3 LSN 1 PLD Uses PLDs are used because Reduced system costs In-circuit programmability Reliability / time-to-market Less susceptible to EMI Design security
4 LSN 1 PLD Organization Program volatility Typically, volatile PLDs provide higher density, more features and lower cost compared to non-volatile PLDs Volatile PLDs lose configuration when powered off Utilize SRAM data storage technology External memory is required to store the configuration, which creates security risks Non-volatile PLDs retain programming data when the power is off Utilize EPROM, EEPROM, or FLASH data storage technologies Do not need an external memory device
5 LSN 1 PLD Types SPLD (simple programmable logic devices) Replaces several fixed function logic ICs CPLD (complex programmable logic devices) Replaces 2-64 SPLDs FPGA (field programmable gate arrays) Different internal architecture than SPLD/CPLD Highest logic capacity with arrays from 64 to thousands of logic gate groups Gate groups called blocks
6 LSN 1 SPLD Architecture
7 LSN 1 CPLD Architecture
8 LSN 1 FPGA Architecture
9 LSN 1 Digital Design Tools Design tools developed to support HDL Design entry Verification High-level synthesis Automatic hardware generation Device programming
10 LSN 1 Digital Design Flow module design (...); assign... always... compi (...) endmodule Comp1 U1 (...); Comp2 U2 (...);... Compn Un (...); Design Specification always (posedge clk) begin... end if ( ) bus = w; else... Analysis Intermediate Format Target Hardware Specification Generic Hardware Generation Logic Optimization Binding Synthesis T = ; T =... Pd Su Routing and Placement Timing Analysis Operating Condition Chip Manufacturing or Device Programming
11 LSN 1 Design Entry Design described by schematic Design described by state diagram Design described in Verilog At register level (RTL) Behavioral level
12 LSN 1 Functional Verification Presynthesis verification Using a verlog module called a testbench Graphically through waveform editor Simulation Model Hierachical Design Description Testbench Simulation Model Simulator Waveform Text, VCD Other forms Waveform Hierachical Design Description Simulator Text, VCD Waveform Other forms Stimuli OUTPUTS INPUTS
13 LSN 1 Functional Verification Testbenches Used to verify the design and later for verifying the synthesis output `timescale 1 ns / 100 ps module Chap1CounterTester (); reg Clk=0, Reset=0; wire [3:0] Count; initial begin Reset = 0; #5 Reset = 1; #115 Reset = 0; #760 $stop; end always #26.5 Clk = ~ Clk; Chap1Counter U1 (Clk, Reset, Count); endmodule module Chap1Counter (Clk, Reset, Count); input Clk, Reset; output [3:0] Count; reg [3:0] Count; Clk) begin if (Reset) Count = 0; else Count = Count + 1; end endmodule Simulator Testbench Design to Simulate
14 LSN 1 Synthesis & Implementation Synthesis: The process of automatic hardware generation from a design description that has an unambiguous hardware correspondence Routing and placement phase
15 LSN 1 TimingVerification Postsynthesis simulation Testing the behavioral model of the design and its hardware model by using presynthesis test data Timing issues checked Determination of a proper clock frequency Determination of race, and hazard considerations
16 LSN 1 Automatic Hardware Generation Last stage in the CAD process to digital system development Generates a netlist for ASIC manufacturing, a program for programming PLDs, or layout of custom IC cells
17 LSN 1 Homework Assignment Reading Chapter 11.1, 11.5, and 11.8 from Digital Fundamentals References Ciletti, M., Advanced Digital Design with Verilog HDL, 1st Ed., Prentice Hall, 2002 Navabi, Z., Verilog Digital System Design, 2 nd Ed., McGraw-Hill 2006 Floyd, T., Digital Fundementals, 10 th Ed., Prentice Hall, 2010
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