Smart Transducer Networks. Embedded Systems Engineering Armin Wasicek

Similar documents
Smart Transducer Networks

A Comparison of LIN and TTP/A

arxiv: v1 [cs.ni] 15 Jul 2015

Modeling Distributed Embedded Applications on an Interface File System

A Universal Smart Transducer Interface: TTP/A

A Standardized Smart Transducer Interface

Applying CORBA to embedded time-triggered real-time systems. S. Aslam-Mir (Sam) Principal CORBA Architect Vertel USA

Distributed Embedded Systems and realtime networks

Field buses (part 2): time triggered protocols

A Simulation Architecture for Time-Triggered Transducer Networks

Basic Components of Digital Computer

AVR XMEGA Product Line Introduction AVR XMEGA TM. Product Introduction.

Systems. Roland Kammerer. 10. November Institute of Computer Engineering Vienna University of Technology. Communication Protocols for Embedded

16 Time Triggered Protocol

Microcontroller basics

Automatic Generation of Schedules for Time-Triggered Embedded Transducer Networks

The I2C BUS Interface

USER GUIDE EDBG. Description

Renesas LIN Overview. White paper REU05B Introduction

Application Note, V1.0, Jul AP XC16x. Interfacing the XC16x Microcontroller to a Serial SPI EEPROM. Microcontrollers

Integrate the Fieldbus into your device without much development effort involved! All-in-one single bus node for:

Digital Circuits Part 2 - Communication

HART Protocol User Manual Rev. 1.0 December, 2014

CN310 Microprocessor Systems Design

Introduction to Arduino. Wilson Wingston Sharon

The Time-Triggered Architecture

Health monitoring of an power amplifier using an ethernet controller

Network Embedded Systems Sensor Networks Fall Hardware. Marcus Chang,

UNIT II PROCESSOR AND MEMORY ORGANIZATION

EDBG. Description. Programmers and Debuggers USER GUIDE

M3-61B DeviceNet Slave Module. M3-61B DeviceNet Slave Module CONTROL TECHNOLOGY CORPORATION

AVR XMEGA TM. A New Reference for 8/16-bit Microcontrollers. Ingar Fredriksen AVR Product Marketing Director

17. I 2 C communication channel

AW Flow Meters HART Summary for RT-Ex15

Developing deterministic networking technology for railway applications using TTEthernet software-based end systems

XMEGA Series Of AVR Processor. Presented by: Manisha Biyani ( ) Shashank Bolia (

The possibility of combining interface modules allows various bus and network systems to be integrated into the B&R SYSTEM 2005.

Real-Time (Paradigms) (47)

Design of a Gigabit Distributed Data Multiplexer and Recorder System

Additional Slides (informative)

CONTENTION BASED PROTOCOLS WITH RESERVATION MECHANISMS

Operating Systems, Concurrency and Time. real-time communication and CAN. Johan Lukkien

Doc: page 1 of 6

Doc: page 1 of 6

(Embedded) Systems Programming Overview

Embedded Systems Lab Lab 1 Introduction to Microcontrollers Eng. Dalia A. Awad

Raspberry Pi - I/O Interfaces

Wireless Sensor Networks: Clustering, Routing, Localization, Time Synchronization

Integrating IO-Link Devices into CIP Networks

Doc: page 1 of 8

Assembly Language for Intel-Based Computers, 4 th Edition. Kip R. Irvine. Chapter 2: IA-32 Processor Architecture

PROFIBUS Technology Products

Lesson 5 Arduino Prototype Development Platforms. Chapter-8 L05: "Internet of Things ", Raj Kamal, Publs.: McGraw-Hill Education

Presented by: Murad Kaplan

MICROPROCESSOR BASED SYSTEM DESIGN

ARDUINO MEGA INTRODUCTION

Contents General Data Data Exchange Mode Block Model

Lecture 9: Bridging. CSE 123: Computer Networks Alex C. Snoeren

An Introduction to FlexRay as an Industrial Network

8051 Microcontroller

Profibus DP/V1 Interface for Bayard-Alpert / Pirani Gauge and High Pressure / Pirani Gauge

Infineon C167CR microcontroller, 256 kb external. RAM and 256 kb external (Flash) EEPROM. - Small single-board computer (SBC) with an

BIG8051. Development system. User manual

Compositional Design of RT Systems: A Conceptual Basis for Specification of Linking Interfaces

Data sheet SLIO CPU 015PN (015-CEFPR01)

Vertex Detector Electronics: ODE to ECS Interface

EtherCAT Introduction

3.3V regulator. JA H-bridge. Doc: page 1 of 7

Using Time Division Multiplexing to support Real-time Networking on Ethernet

Computer-System Organization (cont.)

BLED112 Bluetooth Smart USB Dongle 9/16/2013 1

Cerebot Nano Reference Manual. Overview. Revised April 15, 2016 This manual applies to the Cerebot Nano rev. A

Data sheet CPU 015PN (015-CEFPR00)

DQDB. Distributed Queue Dual Bus (DQDB) DQDB is a MAN. Unlike FDDI, DQDB is an IEEE standard: 802.6

Temperature Sensor TMP2 PMOD Part 1

SR5 Serial Protocol - Issue 1.6

Data sheet CPU 015PN (015-CEFPR01)

Embedded Workshop 10/28/15 Rusty Cain

COMP3221: Microprocessors and. and Embedded Systems. Instruction Set Architecture (ISA) What makes an ISA? #1: Memory Models. What makes an ISA?

Lecture 6 The Data Link Layer. Antonio Cianfrani DIET Department Networking Group netlab.uniroma1.it

A Reliable Gateway for In-vehicle Networks

Series SD6 Limit with DeviceNet

Lecture 5 The Data Link Layer. Antonio Cianfrani DIET Department Networking Group netlab.uniroma1.it

Hercules ARM Cortex -R4 System Architecture. Processor Overview

ECE 551 System on Chip Design

The Development of CompoNet Gateway with Common Network Interface

Unlocking the Potential of Your Microcontroller

Esbus A sensor bus based on the SPI serial interface

Mercury System SB310

VIII. DSP Processors. Digital Signal Processing 8 December 24, 2009

PRACTICAL DESIGN TECHNIQUES FOR SENSOR SIGNAL CONDITIONING

Embedded programming, AVR intro

An Encapsulated Communication System for Integrated Architectures

SINAMICS S120. Communication. Communication 2/7. Overview

Development and research of different architectures of I 2 C bus controller. E. Vasiliev, MIET

Data sheet CPU 315SB/DPM (315-2AG12)

COMMUNICATION MODBUS PROTOCOL

Profibus DP/V1 Interface for Bayard-Alpert Pirani Capacitance Diaphragm Gauge

Assembly Language. Lecture 2 - x86 Processor Architecture. Ahmed Sallam

300S. The high speed control system powered by SPEED7.

Transcription:

Smart Transducer Networks Embedded Systems Engineering Armin Wasicek

Overview Motivation & Design Principles TTP/A Fieldbus Protocol Implementation Requirements Smart Transducer Interface Standard Conclusion TTP/A Smart Transducer Networks 2

Definition A smart transducer is the integration of an analog or digital sensor or actuator element, a processing unit, and a communication interface. Physical Transducer Smart Transducer MCU Network Interface Digital Communication System TTP/A Smart Transducer Networks 3

Motivation Sensor/Actuators become more complex (e.g. providing various modes of interfacing, operation...) Requirement for fault-tolerant and distributed systems -> networked sensors and actuators Embedded microcontrollers can handle complexity at a fair price Cheap mass-production of flexible general purpose smart transducers TTP/A Smart Transducer Networks 4

Design Principles for ST (1) Two-Level Design Approach Node level: Transducer developer handles sensor- and actuator-specific details Functionality of transducer is exported via well-specified interface System level: System integrator can handle node as black boxes and build on exported services Composability principle guarantees that services, which are established at node level are maintained at system level TTP/A Smart Transducer Networks 5

Three Interfaces of a Node SPLIF Service Providing Linking Interface SRLIF Service Requesting Linking Interface TTP/A Smart Transducer Networks 6

Design Principles for ST (2) Real-Time Service Knowledge about the exact instant of an event Predictable timing with low jitter (control loops) Guaranteed timing behavior under load and fault hypotheses TTP/A Smart Transducer Networks 7

Design Principles for ST (3) Diagnosis & Management Support Diagnosis access to ST internals Not necessarily real-time capable Monitoring support without a probe effect on real-time service TTP/A Smart Transducer Networks 8

Design Principles for ST (4) Configuration & Planning Support Machine-readable description of ST properties Automated configuration saves time Required qualification of personal can be lower Fewer configuration faults, since monotone and errorprone tasks are done by computer TTP/A Smart Transducer Networks 9

Overview Motivation & Design Principles TTP/A Fieldbus Protocol Implementation Requirements Smart Transducer Interface Standard Conclusion TTP/A Smart Transducer Networks 10

TTP/A Protocol (1) One active master per cluster Up to 250 slaves Communication organized in rounds TDMA bus allocation For details see: TTP/A Smart Transducer Programming A Beginner s Guide Available at: (http://www.vmars.tuwien.ac.at/) Publication & Research Reports TTP/A Smart Transducer Networks 11

TTP/A Protocol (2) Time Division Multiple Access TTP/A Smart Transducers 12

Interface File System (IFS) (1) Hierarchical distributed data structure Source and sink of each communication Unique addressing scheme: Cluster (0..255) Node (0..255) File (0..63) Record (0..255) Byte (0..3) IFS maps all relevant properties (sensor and actuator data, calibration parameters, configuration data, serial number, ) TTP/A Smart Transducer Networks 13

Interface File System (IFS) (2) Header Record First record of each file contains status information (access permissions, file length, etc) Special Files Documentation file: physical name of node (similar to MAC address) Configuration file: logical name of the node, current fireworks-byte, epoch-counter etc. Round Descriptor List (RODL): holds information about actions performed by a node for a particular round Round Sequence file (ROSE): specifies sequence of rounds, only implemented in the TTP/A master TTP/A Smart Transducer Networks 14

Round Types Master-slave round: Master accesses a record by broadcasting its IFS address and a tag indicating operation (read, write, ) Master-slave address (MSA) and master-slave data (MSD) part Multipartner round: TDMA communication is predefined by RODL Up to 6 different modes (predefined schedules) TTP/A Smart Transducer Networks 15

Round Description List (RODL) For each slot in each round: Operation (receive, send, receive and synchronize clock, execute) Data source/sink (IFS address + message length) Each node has its own RODL (part of a big picture ) RODL must be consistently defined over all nodes RODL itself is accessible via IFS TTP/A Smart Transducer Networks 16

Common Communication and Action Schedule node slot 1 2 3 4 A Send Receive Receive Execute B Receive Send Receive Send C Receive Receive Send Receive D Receive Receive Execute Receive t TTP/A Smart Transducer Networks 17

Realization of Three Interfaces (1) Real-Time Service (RS): Multipartner rounds Configuration and Planning (CP) Interface Master-Slave rounds accessing RODL Diagnostic and Maintenance (DM) Interface Master-Slave Rounds during operation TTP/A Smart Transducer Networks 18

Realization of Three Interface (2) Local Interfaces RT Input SRLIF Service CP DM SPLIF RT Output RS Interface: IFS realizes Service Requesting Linking Interface (SRLIF) and Service Providing Linking Interface (SPLIF) CP Interface: access via RODL DM Interface: local data of individual TTP/A tasks (stored in service file) TTP/A Smart Transducer Networks 19

TTP/A Example Three TTP/A nodes Node 0 is the TTP/A master (synchronization of slaves via fireworks byte) Node 3 executes in slot 0x03 a counter and broadcasts the actual value in slot 0x01 Node 2 receives the counter value in slot 0x01 and displays the new value in slot 0x03 (also by executing a TTP/A task) Inter-round gap (end of round) in slot 0x07 In the following the code of node 3 is illustrated The example is available on the Lab homepage TTP/A Smart Transducer Networks 20

TTP/A Example: IFS Layout TTP/A specific include files e.g. IFS access macros name of the IFS file for the application (suggested range 0x30 to 0x3d) memory section for IFS storage (ifs_int_eep EEPROM) (ifs_int_0 zero initialized SRAM) layout of the application file IFS address signed 8-bit int value for incr. value unsigned 8-bit value for error code declaration of TTP/A task TTP/A Smart Transducer Networks 21

TTP/A Example: RODL Layout TTP/A specific include files e.g. IFS access macros layout of the RODL (for node 3 only) RODL filename (0x00 to 0x07); length of RODL; memory section for storage (EEPROM) operation: send slot: 0x01 IFS addr: I/O file record 0x01, byte 0 length: 1 (len 1 is stored) operation: execute slot: 0x03 IFS addr: specifies the task to execute end of round: slot 0x07 TTP/A Smart Transducer Networks 22

TTP/A Example: Node Source-Code application file with initialization pointer to I/O file = I/O file increment value = 1; error flag = 0 I/O file parameters for file definition: file number, variable name, TTPA/task, file length, memory section, and access mode code for TTP/A task code for initialization function adding an initialization function: task handle, function pointer to task, order, execution states adding a background task is similar TTP/A Smart Transducer Networks 23

Overview Motivation & Design Principles TTP/A Fieldbus Protocol TTP/A Implementation / Case Study Smart Transducer Interface Standard Conclusion TTP/A Smart Transducer Networks 24

Architectural Requirements Standard UART (may be also a software UART) About 2KB ROM for protocol code About 32 byte RAM for protocol-specific variables (e.g., RODL memory) Supports any serial bus TTP/A Smart Transducer Networks 25

Case Study Hardware PCMCIA Master/Gateway Atmel AVR TTP/A nodes TTP/A Smart Transducer Networks 26

Case Study Software RODL design tool Written in Java => Platform-independent Connects to cluster via CORBA interface Monitoring tool Displays contents of node s IFS Refreshes data periodically Connects directly via RS232 Important for lab course TTP/A Smart Transducer Networks 27

Overview Motivation & Design Principles TTP/A Fieldbus Protocol TTP/A Implementation / Case Study Smart Transducer Interface Standard Conclusion TTP/A Smart Transducer Networks 28

OMG Smart Transducer Standard Specifies a CORBA interface for accessing the IFS contents of a TTP/A cluster remotely Specifies IFS addressing scheme Specifies real-time communication CORBA can be used for configuration and monitoring Access to real-time service interface possible, when a RT- CORBA is used TTP/A Smart Transducer Networks 29

Example Architecture TTP/A Smart Transducer Networks 30

Overview Design Principles TTP/A Fieldbus Protocol Implementation Requirements Smart Transducer Interface Standard Conclusion TTP/A Smart Transducer Networks 31

Conclusion Two-level design for ST applications Node level: transducer details System level: integration to overall system TTP/A: Master/Slave protocol supporting periodic real-time traffic and sporadic diagnostic and management communication Low-cost, highly-efficient (no addressing overhead) Standardized CORBA interface supports remote tool access TTP/A Smart Transducer Networks 32

Vielen Dank für Ihre Aufmerksamkeit! Fragen? TTP/A Smart Transducer Networks 33