CN310 Microprocessor Systems Design Simple Computer Nawin Somyat Department of Electrical and Computer Engineering Thammasat University
Outline Course Contents 1 Introduction 2 Simple Computer 3 Microprocessor Architecture 4 Memory 5 Peripherals 6 Applications Outline 1 Architecture Components 2 Registers Register Output Register B Register A Instruction Register Program Counter 3 ALU 1-bit Adder 4-bit ALU 4 Memory 5 Instruction Instruction Set Instruction Decoder CN310 Microprocessor Systems Design 2 / 25
Components Registers Register A Register B Register Output Program Counter (PC) Instruction Register (IR) Processing Unit (ALU) Memory Instruction Instruction Set Instruction Decoder CN310 Microprocessor Systems Design 3 / 25
Block Diagram CN310 Microprocessor Systems Design 4 / 25
1-bit Register CN310 Microprocessor Systems Design 5 / 25
1-bit Register - Symbol and Truth Table Reset CLK Load D Q 0 X X X 0 1 0 X X Q 0 1 1 0 X Q 0 1 1 1 d d If Reset = 0, Q = 0 If Reset = 1 and clock signal (CLK) is asserted/active if Load = 0, Q remains previous value (Q 0 ) if Load = 1, Q becomes d (d is either 0 or 1) CN310 Microprocessor Systems Design 6 / 25
4-bit Register If /CLR = 0, Q 3 Q 2 Q 1 Q 0 = 0000 If /CLR = 1 and clock signal (CLK) is asserted/active if Load = 0, Q 3 Q 2 Q 1 Q 0 will remain previous values if Load = 1, Q 3 Q 2 Q 1 Q 0 becomes D 3D 2D 1D 0 CN310 Microprocessor Systems Design 7 / 25
Register Output The output from 4-bit register is connected to a 4-bit buffer. The resulting register is used as Register Output. CN310 Microprocessor Systems Design 8 / 25
Register B Similar to Register Output, use 4-bit buffer register as Register B CN310 Microprocessor Systems Design 9 / 25
Bidirectional 4-bit Register Using tri-state buffer with 4-bit buffer register to create bidirectional 4-bit register. CN310 Microprocessor Systems Design 10 / 25
Bidirectional 4-bit Register If /EN = 1, D 3 D 2 D 1 D 0 will be in High Impedance (High-Z) state, used for receiving input data where: if LD = 0, D 3 D 2 D 1 D 0 will remain previous values if LD = 1, D 3 D 2 D 1 D 0 will be read into the register If /EN = 0, data kept in the register will be output to D 3 D 2 D 1 D 0 CN310 Microprocessor Systems Design 11 / 25
Register A D0-3 are bidirectional signals. Y0-3 are unidirection signals. CN310 Microprocessor Systems Design 12 / 25
Instruction Register Instruction Register simply stores the instruction to be executed. CN310 Microprocessor Systems Design 13 / 25
Program Counter if CP = 0 Q will remain previous value if CP = 1 Q will count up CN310 Microprocessor Systems Design 14 / 25
1-bit Full Adder C out A B + C in + S CN310 Microprocessor Systems Design 15 / 25
4-bit ALU if /EN = 0 S will give result if /EN = 1 S will be in high-z When /EN = 0 if Sub = 0 S = A + B if Sub = 1 S = A - B CN310 Microprocessor Systems Design 16 / 25
Connecting Registers and ALU to Bus CN310 Microprocessor Systems Design 17 / 25
Memory For limited operation in this simple computer, memory is used for storing fixed program only. Program will be preloaded into the memory. We will use ROM in this case. CN310 Microprocessor Systems Design 18 / 25
Instruction Set In this simple computer, we will have 5 simple instructions. Code Opeartion Description 1 A n load register A with n 2 A A + n add A with n and store result in A 3 A A - n subtract n from A and store resultin A 4 Output A store data in A to register Output F Stop stop operation CN310 Microprocessor Systems Design 19 / 25
Instruction Decoder Only one instruction will be active at any one time. CN310 Microprocessor Systems Design 20 / 25
Operation This simple computer will take 5 clock cycles (at most) to execute one instruction. Code Mneumonic Operation T0 T1 T2 T3 T4 1 MOV A, #n A n IR memory PC PC + 1 A Memory PC PC + 1 2 ADD A, #n A A + n IR memory PC PC + 1 B Memory PC PC + 1 A A + B 3 SUB A, #n A A - n IR memory PC PC + 1 B Memory PC PC + 1 A A B 4 OUT Output A IR memory PC PC + 1 Output A F HALT Stop IR memory PC PC + 1 STOP CN310 Microprocessor Systems Design 21 / 25
Ring Counter Ring counter provides synchronised clock cycles for instruction cycles. CN310 Microprocessor Systems Design 22 / 25
Control Unit CN310 Microprocessor Systems Design 23 / 25
Example Program Address Data Opcode Operand Comment ORG 0 0 1 5 MOV A, #5 ; set A = 5 2 2 4 ADD A, #4 ; add A with 4 4 4 OUT A ; display output 5 F HALT ; stop Memory Address Data 0 1 1 5 2 2 3 4 4 4 5 F CN310 Microprocessor Systems Design 24 / 25
Simple Computer Circuit Diagram CN310 Microprocessor Systems Design 25 / 25