Chapter 5. Computer Architecture Organization and Design Computer System Architecture Database Lab, SANGJI University
Computer Architecture Organization and Design Instruction Codes Computer Registers Computer Instructions Timing and Control Instruction Cycle Memory Reference Instructions Input-Output and Interrupt Complete Computer Description Design of Basic Computer Design of Accumulator Logic
5.1 Instruction Code A process is controlled by a program A program is a set of instructions that specify the operations, data, and the control sequence An instruction is stored in binary code that specifies a sequence of microoperations Instruction codes together with data are stored in memory (Stored Program Concept)
5.1 Instruction Codes A computer instruction is a binary code that specifies a sequence of micro-operations for the computer. Each computer has its unique instruction set Instruction codes and data are stored in memory The computer reads each instruction from memory and places it in a control register The control unit interprets the binary code of the instruction and proceeds to execute it by issuing a sequence of microoperations
5.1 Instruction Codes Instructions can be formatted to fit in one or more memory words. An instruction may contain An opcode + data (immediate operand) An opcode + the address of data (direct addressing) An opcode + an address where the address of the data is found (indirect addressing) Data only (location has no instructions) An opcode only (register-reference or input/output instruction)
5.1 Instruction Codes The Basic Computer has two components, a processor and memory The memory has 4096 words in it 4096 = 2 12, so it takes 12 bits to select a word in memory Each word is 16 bits long Program A sequence of (machine) instructions CPU RAM 0 (Machine) Instruction A group of bits that tell the computer to perform a specific operation (a sequence of micro-operation) The instructions of a program, along with any needed data are stored in memory 15 0 The CPU reads the next instruction from memory 4095 It is placed in an Instruction Register (IR)
5.1 Instruction Codes 1. Memory address contents 0000000000000001 0101010101010101 0000000000000010 1010101010101010 PC 2. Program Counter 000000000001 0000000000000011 0000000000000100 0000000000000101 1100110011001100 0011001100110011 0101010101010011 0000000000000110 1010101010101010 3. Instruction Register 0000000000000111 0000000000001000 1100110011001100 0011001100110011 IR 0101 010101010101
5.1 Instruction Codes An Instruction code is a group of bits that instructs the computer to perform a specific operation (sequence of microoperations). It is divided into parts (basic part is the operation part) The operation code of an instruction is a group of bits that defines certain operations such as add, subtract, shift, and complement The number of bits required for the operation code depends on the total number of operations available in the computer 2 n (or little less) distinct operations n bit operation code 15 12 11 0 Op. Code Address Instruction format
5.1 Instruction Codes An operation must be performed on some data stored in processor registers or in memory An instruction code must therefore specify not only the operation, but also the location of the operands (in registers or in the memory), and where the result will be stored (registers/memory) 15 12 11 0 Op. Code Address Instruction format
5.1 Instruction Codes Stored Program Organization An instruction code is usually divided into operation code, operand address, addressing mode, etc. The simplest way to organize a computer is to have one processor register (accumulator AC) and an instruction code format with two parts (op code, address)
5.1 Instruction Codes Stored Program Organization 15 12 11 0 Opcode Address Instruction Format Binary Operand 4096 words = 12bits address 15 0 Instructions (program) 15 Memory 4096x16 0 15 0 Processor register (Accumulator AC) Operands (data)
5.1 Instruction Codes Addressing Mode Immediate: the operand is given in the address portion (constant) Direct: the address points to the operand stored in the memory Indirect: the address points to the pointer (another address) stored in the memory that references the operand in memory Effective address: Address where an operand is physically located One bit of the instruction code can be used to distinguish between direct & indirect addresses
5.1 Instruction Codes Addressing Mode Instruction Format 15 14 12 11 0 I Opcode Address Effective address Direct Address Indirect address 22 0 ADD 457 35 1 ADD 300 300 1350 457 Operand 1350 Operand + + AC AC
5.2 Computer Registers A processor has many registers to hold instructions, addresses, data, etc The processor has a register, the Program Counter (PC) that holds the memory address of the next instruction to get Since the memory in the Basic Computer only has 4096 locations, the PC only needs 12 bits In a direct or indirect addressing, the processor needs to keep track of what locations in memory it is addressing: The Address Register (AR) is used for this The AR is a 12 bit register in the Basic Computer When an operand is found, using either direct or indirect addressing, it is placed in the Data Register (DR). The processor then uses this value as data for its operation The Basic Computer has a single general purpose register the Accumulator (AC)
5.2 Computer Registers Often a processor will need a scratch register to store intermediate results or other temporary data; in the Basic Computer this is the Temporary Register (TR) The Basic Computer uses a very simple model of input/output (I/O) operations Input devices are considered to send 8 bits of character data to the processor The processor can send 8 bits of character data to output devices The Input Register (INPR) holds an 8 bit character gotten from an input device The Output Register (OUTR) holds an 8 bit character to be send to an output device
5.2 Computer Registers Registers in the Basic Computer 11 0 PC 11 0 AR 15 0 IR Memory 4096 x 16 15 0 TR 7 0 7 0 OUTR INPR 15 0 DR 15 0 AC List of BC Registers DR 16 Data Register Holds memory operand AR 12 Address Register Holds address for memory AC 16 Accumulator Processor register IR 16 Instruction Register Holds instruction code PC 12 Program Counter Holds address of instruction TR 16 Temporary Register Holds temporary data INPR 8 Input Register Holds input character OUTR 8 Output Register Holds output character
5.2 Computer Registers Common Bus System The basic computer has eight registers, a memory unit, and a control unit. Paths must be provided to transfer information from one register to another and between memory and registers A more efficient scheme for transferring information in a system with many registers is to use a common bus.
5.2 Computer Registers Common Bus System Memory unit 4096 x 16 Write AR Read S2 S1 S0 Address Bus 7 1 LD INR CLR PC 2 LD INR CLR DR 3 LD INR CLR ALU E AC 4 LD INR CLR INPR IR LD TR LD INR CLR OUTR LD 16-bit common bus Clock 5 6
5.2 Computer Registers Common Bus System Memory 4096 x 16 Read Write Address E ALU INPR AC L I C L I C L L I C DR IR L I C PC TR AR L I C 7 1 2 3 4 5 6 16-bit Common Bus OUTR LD S 0 S 1 S 2
5.2 Computer System Common Bus System The connection of the registers and memory of the basic computer to a common bus system : The outputs of seven registers and memory are connected to the common bus The specific output is selected by mux(s0, S1, S2) : Memory(7), AR(1), PC(2), DR(3), AC(4), IR(5), TR(6) When LD(Load Input) is enable, the particular register receives the data from the bus Control Input : LD, INC, CLR, Write, Read
5.2 Computer System Common Bus System
5.3 Computer Instruction
5.3 Computer Instructions The set of instructions are said to be complete if the computer includes a sufficient number of instructions in each of the following categories: Arithmetic, logical, and shift instructions Instructions for moving information to and from memory and processor registers Program control instructions together with instructions that check status conditions Input & output instructions
5.4 Timing and Control Control unit (CU) of a processor translates from machine instructions to the control signals for the microoperations that implement them Control units are implemented in one of two ways Hardwired Control CU is made up of sequential and combinational circuits to generate the control signals Microprogrammed Control A control memory on the processor contains microprograms that activate the necessary control signals We will consider a hardwired implementation of the control unit for the Basic Computer
5.4 Timing and Control Control unit of Basic Computer Instruction register (IR) 15 14 13 12 11-0 Other inputs 3 x 8 decoder 7 6 5 4 3 2 1 0 I D 0 D7 Combinational Control logic Control signals T15 T0 15 14.... 2 1 0 4 x 16 decoder 4-bit sequence counter (SC) Increment (INR) Clear (CLR) Clock
5.4 Timing and Control - Generated by 4-bit sequence counter and 4 16 decoder - The SC can be incremented or cleared. - Example: T 0, T 1, T 2, T 3, T 4, T 0, T 1,... Assume: At time T 4, SC is cleared to 0 if decoder output D3 is active. D 3 T 4 : SC 0 Clock T0 T1 T2 T3 T4 T0 T0 T1 T2 T3 T4 D3 CLR SC
5.4 Timing and Control
5.5 Instruction Cycle In Basic Computer, a machine instruction is executed in the following cycle: 1. Fetch an instruction from memory 2. Decode the instruction 3. Read the effective address from memory if the instruction has an indirect address 4. Execute the instruction After an instruction is executed, the cycle starts again at step 1, for the next instruction [ PC +1]
5.5 Instruction Cycle Fetch and Decode Fetch and Decode T0: AR PC (S 0 S 1 S 2 =010, T0=1) T1: IR M [AR], PC PC + 1 (S0S1S2=111, T1=1) T2: D0,..., D7 Decode IR(12-14), AR IR(0-11), I IR(15) T1 S 2 T0 S 1 Bus Memory unit Read Address S 0 7 AR 1 LD PC 2 INR IR 5 LD Common bus Clock
5.5 Instruction Cycle
5.5 Instruction Cycle
5.5 Instruction Cycle Register Reference Instruction Register Reference Instructions are identified when - D 7 = 1, I = 0 - Register Ref. Instr. is specified in B 0 ~ B 11 of IR - Execution starts with timing signal T 3 r = D 7 I T 3 => Register Reference Instruction B i = IR(i), i=0,1,2,...,11, the ith bit of IR. r: SC 0 CLA rb 11 : AC 0 CLE rb 10 : E 0 CMA rb 9 : AC AC CME rb 8 : E E CIR rb 7 : AC shr AC, AC(15) E, E AC(0) CIL rb 6 : AC shl AC, AC(0) E, E AC(15) INC rb 5 : AC AC + 1 SPA rb 4 : if (AC(15) = 0) then (PC PC+1) SNA rb 3 : if (AC(15) = 1) then (PC PC+1) SZA rb 2 : if (AC = 0) then (PC PC+1) SZE rb 1 : if (E = 0) then (PC PC+1) HLT rb 0 : S 0 (S is a start-stop flip-flop)
5.6 Memory Reference Instruction Opcode (000-110) or the decoded output Di (i = 0,..., 6) are use d to select one memory-reference operation out of 7.
5.6 Memory Reference Instruction - The effective address of the instruction is in AR and was placed there during timing signal T 2 when I = 0, or during timing signal T3 when I = 1 Memory cycle is assumed to be short enough to be completed in a CPU cycle The execution of MR Instruction starts with T 4 AND to AC D 0 T 4 : DR M[AR] Read operand D 0 T 5 : AC AC DR, SC 0 AND with AC ADD to AC D 1 T 4 : DR M[AR] Read operand D 1 T 5 : AC AC + DR, E C out, SC 0 Add to AC and store carry in E
5.6 Memory Reference Instruction LDA: Load to AC D 2 T 4 : DR M[AR] D 2 T 5 : AC DR, SC 0 STA: Store AC D 3 T 4 : M[AR] AC, SC 0 BUN: Branch Unconditionally D 4 T 4 : PC AR, SC 0 BSA: Branch and Save Return Address M[AR] PC, PC AR + 1 Memory, PC, AR at time T4 20 0 BSA 135 Return address: PC = 21 Next instruction Memory, PC after execution 20 0 BSA 135 21 Next instruction AR = 135 135 21 136 Subroutine PC = 136 Subroutine 1 BUN 135 1 BUN 135 Memory Memory
5.6 Memory Reference Instruction BSA: executed in a sequence of two micro-operations: D 5 T 4 : M[AR] PC, AR AR + 1 D 5 T 5 : PC AR, SC 0 ISZ: Increment and Skip-if-Zero D 6 T 4 : DR M[AR] D 6 T 5 : DR DR + 1 D 6 T6: M[AR] DR, if (DR = 0) then (PC PC + 1), SC 0
5.6 Memory Reference Instruction Memory-reference instruction AND ADD LDA STA D 0 T 4 D 1 T 4 D 2 T 4 D 3 T 4 DR M[AR] DR M[AR] DR M[AR] M[AR] AC SC 0 D 0 T 5 D 1 T 5 D 2 T 5 AC AC DR SC <- 0 AC AC + DR E Cout SC 0 AC DR SC 0 BUN BSA ISZ PC AR SC 0 D T 4 4 D T 5 4 D T 6 4 M[AR] PC AR AR + 1 PC AR SC 0 DR M[AR] D T 5 5 D T 6 5 DR DR + 1 D 6 T 6 M[AR] DR If (DR = 0) then (PC PC + 1) SC 0
5.7 Input-Output and Interrupt
5.7 Input-Output and Interrupt
5.7 Input-Output and Interrupt
5.7 Input-Output and Interrupt Interrupt
5.7 Input-Output and Interrupt
5.8 Complete Computer Description
5.8 Complete Computer Description
5.8 Complete Computer Description