PCI-X Electrical and Mechanical Addendum to the PCI Local Bus Specification Revision 2.0a

PCI-X Electrical and Mechanical Addendum to the PCI Local Bus Specification Revision 2.0a August 22, 2003

REVISION REVISION HISTORY DATE 1.0 Initial release. 9/22/99 1.0a Clarifications and typographical corrections. 7/24/00 1.0b Clarifications and errata. 7/29/2002 2.0 2.0a Specification divided into separate PCI-X Protocol Specification and PCI-X Electrical and Mechanical Specification. Added Mode 2 with 1.5V signaling, sourcesynchronous clocking of two or four subphases per clock. Added ECC, device ID messaging, and 16-bit interface. Incorporated the PCI-X slot and card identification ECN Incorporated errata through revision A.20. Changed references from PCI-X PT 2.0 to PCI-X PT 2.0a. Added clock jitter information to end of Appendix C. 11/4/02 8/22/03 The PCI-SIG disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does the PCI-SIG make a commitment to update the information contained herein. Contact the PCI-SIG office to obtain the latest revision of the specification. uestions regarding the PCI-X Addendum or membership in the PCI-SIG may be forwarded to: Membership Services http://www.pcisig.com E-mail: administration@pcisig.com Phone: 503-291-2569 800-433-5177 (USA Only) Fax: 503-297-1090 Technical Support techsupp@pcisig.com DISCLAIMER This PCI-X Addendum is provided as is with no warranties whatsoever, including any warranty of merchantability, noninfringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample. The PCI-SIG disclaims all liability for infringement of proprietary rights, relating to use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. All product names are trademarks, registered trademarks, or servicemarks of their respective owners. Copyright 1999, 2000, 2002, 2003 PCI-SIG 2

Contents 1. INTRODUCTION... 11 1.1. DOCUMENTATION CONVENTIONS... 12 1.2. TERMS AND ABBREVIATIONS... 14 1.3. FIGURE LEGEND... 19 2. ELECTRICAL SPECIFICATION... 21 2.1. DEVICE REUIREMENTS... 21 2.1.1. Driver and Receiver Categories... 21 2.1.2. 3.3V Signaling Environment... 22 2.1.2.1. 3.3V DC Specifications... 22 2.1.2.2. 3.3V AC Specifications... 24 2.1.2.3. 3.3V Maximum AC Ratings and Device Protection... 28 2.1.2.4. 3.3V Timing Specifications... 28 2.1.2.4.1. Clock Specification... 28 2.1.2.4.2. 3.3V Timing Parameters... 32 2.1.2.5. 3.3V Measurement and Test Conditions... 33 2.1.2.5.1. 3.3V Input and Output Timing... 33 2.1.2.5.2. 3.3V Measurement Condition Parameters... 35 2.1.2.5.3. 3.3V Test Circuits... 35 2.1.2.6. Mode 1 Device Internal Timing Examples... 36 2.1.3. 1.5V Signaling Environment... 38 2.1.3.1. Source-Synchronous Data Strobes... 41 2.1.3.2. Electrical Termination... 47 2.1.3.3. Input Receivers... 48 2.1.3.4. Interface Low-Power State... 49 2.1.3.5. 1.5V DC Specifications... 49 2.1.3.6. 1.5V AC Specifications... 51 2.1.3.7. 1.5V Maximum AC Ratings and Device Protection... 54 2.1.3.8. 1.5V Timing Specifications... 55 2.1.3.8.1. 1.5V Common-Clock Timing Parameters... 55 2.1.3.8.2. 1.5V Source-Synchronous Timing Parameters... 56 2.1.3.9. 1.5V Measurements and Test Conditions... 61 2.1.3.9.1. 1.5V Input and Output Timing... 61 2.1.3.9.2. 1.5V Measurement Condition Parameters... 65 2.1.3.9.3. 1.5V Test Circuits... 67 2.1.3.10. Mode 2 Device Internal Timing Examples... 69 2.1.3.10.1. Mode 2 Common-Clock Examples... 69 2.1.3.10.2. Mode 2 Source-Synchronous Examples... 72 2.1.4. Selection Between Mode 1 and Mode 2 by the Device... 74 2.2. ADD-IN CARD ROUTING REUIREMENTS... 75 2.2.1. Signal Loading... 76 2.2.2. Transmission Line Characteristics... 76 2.2.3. Trace Length Limits and Matching... 76 3

2.2.4. Trace Spacing and Geometries... 80 2.2.5. Add-in Card Edge-Connector Plane Excursion... 80 2.3. SYSTEM BOARD REUIREMENTS... 81 2.3.1. Clock Uncertainty... 81 2.3.2. Reset... 82 2.3.3. Pull-ups... 84 2.3.4. IDSEL Connection to AD Bus... 85 2.3.5. System Noise Budget... 86 2.3.5.1. Mode 1 System Noise Budget... 86 2.3.5.2. Mode 2 Category 1 System Noise Budget... 87 2.3.6. System Timing Budgets... 89 2.3.6.1. Mode 1 System Timing Budgets... 89 2.3.6.2. Mode 2 System Timing Budget... 90 2.3.6.2.1. Common-Clock Timing Budget... 90 2.3.6.2.2. Source-Synchronous Timing Budget... 92 2.3.6.2.3. Source-Synchronous to Common-Clock Setup... 95 2.4. PCIXCAP AND MODE2 CONNECTION... 96 2.5. POWER... 99 2.5.1. Power Requirements... 99 2.5.2. Sequencing... 99 2.5.3. Decoupling... 100 2.5.4. Mode 2 V I/O Requirements... 100 2.6. PIN MULTIPLEXING AND SHARING... 104 2.6.1. ECC Pins... 104 2.6.2. Locations of FSTROBE[2], SSTROBE[2], and AD[49::48]... 104 2.6.3. Summary of Pin Multiplexing and Sharing... 104 2.7. CONNECTOR PIN OUT... 106 3. MECHANICAL SPECIFICATION... 109 3.1. GENERAL MECHANICAL REUIREMENTS... 109 3.2. IDENTIFICATION REUIREMENTS... 109 3.2.1. System Requirement... 110 3.2.2. Add-in Card Requirement... 110 3.2.2.1. Requirements for Marking... 110 3.2.2.2. Placement of Marking... 111 A. APPENDIX DETECTION OF PCI-X ADD-IN CARD CAPABILITY... 113 A.1. MODE 1 ALTERNATIVES... 113 A.1.1. Three-level Comparator... 113 A.1.2. Programmable Pull-up and Binary Input Buffer... 115 A.2. FIVE-LEVEL COMPARATOR, MODE 2... 116 B. APPENDIX ADD-IN CARD MULTILAYER SPACING AND STACK-UP EXAMPLES... 119 B.1. SIX-LAYER ADD-IN CARD EXAMPLES... 119 B.2. EIGHT-LAYER ADD-IN CARD EXAMPLES... 120 4

C. APPENDIX PCI-X MODE 2 DEVICE DESIGN GUIDELINES AND EXAMPLES... 123 C.1. SOURCE-SYNCHRONOUS DATA CAPTURE... 123 C.2. CATEGORY 1 I/O BUFFER BLOCK EXAMPLE... 130 C.3. PACKAGE CONSIDERATIONS... 132 C.4. ON-DIE V I/O DECOUPLING CAPACITANCE... 133 C.5. EFFECTS OF CLK JITTER ON DEVICE TIMING... 138 C.5.1. Jitter Definitions... 138 C.5.1.1. Phase Jitter... 139 C.5.1.2. Period Jitter... 140 C.5.1.3. Cycle-to-Cycle Jitter... 141 C.5.2. Effects of Jitter on a Common-Clock Transfer... 143 C.5.3. Tracking CLK Jitter... 143 C.5.3.1. PLL Transfer Function... 143 C.5.3.2. PLL Tracking Error... 145 C.5.4. Impact on Device Timing... 147 C.5.5. Conclusions... 150 D. APPENDIX PCI-X MODE 2 SYSTEM DESIGN GUIDELINES... 151 D.1. SYSTEM SIGNAL INTEGRITY CONSIDERATIONS FOR 1.5V SIGNALING ENVIRONMENT... 151 D.1.1. Managing System Noise... 151 D.1.2. Managing Device Internal Noise... 152 D.1.3. AC Noise Margin Calculations... 153 D.1.4. Add-in Card Connector Considerations... 154 D.1.5. System Distortion of Signals at Device Inputs... 154 D.1.5.1. Input Signaling Limits... 154 D.1.5.2. Valid Signal Transition and Ringback... 156 D.1.5.3. Measuring V test Crossing... 157 D.2. SYSTEM-BOARD ROUTING GUIDELINES FOR CATEGORY 1 SIGNALS... 162 D.2.1. Optimum Power Plane and Trace Cross Sectional Geometries... 163 D.2.2. Transmission Line Characteristic... 163 D.2.3. Length Matching within a Source-Synchronous Signaling Group... 164 D.2.4. Group-to-Group Delay... 165 D.2.5. Trace Spacing and Geometries... 165 ACKNOWLEDGEMENTS... 167 5

Figures FIGURE 1-1: FIGURE LEGEND, MODE 1... 19 FIGURE 1-2: FIGURE LEGEND, MODE 2... 20 FIGURE 2-1: 3.3V PCI-X PULL-UP OUTPUT BUFFER I/V CURVES... 26 FIGURE 2-2: 3.3V PCI-X PULL-DOWN OUTPUT BUFFER I/V CURVES... 26 FIGURE 2-3: 3.3V PCI-X PULL-UP OUTPUT BUFFER V/I CURVES (REF)... 27 FIGURE 2-4: 3.3V PCI-X PULL-DOWN OUTPUT BUFFER V/I CURVES (REF)... 27 FIGURE 2-5: CLOCK WAVEFORM... 29 FIGURE 2-6: 3.3V OUTPUT TIMING MEASUREMENT CONDITIONS... 34 FIGURE 2-7: 3.3V INPUT TIMING MEASUREMENT CONDITIONS... 34 FIGURE 2-8: 3.3V T VAL (MAX) RISING EDGE TEST LOAD... 35 FIGURE 2-9: 3.3V T VAL (MAX) FALLING EDGE TEST LOAD... 36 FIGURE 2-10: 3.3V T VAL (MIN) TEST LOAD... 36 FIGURE 2-11: 3.3V OUTPUT SLEW RATE TEST LOAD... 36 FIGURE 2-12: DEVICE INTERNAL TIMING EXAMPLE, MODE 1... 37 FIGURE 2-13: SOURCE-SYNCHRONOUS & COMMON-CLOCK DOMAIN PARTITIONING... 39 FIGURE 2-14: SIGNAL PROPAGATION TIME EFFECTS ON COMMON-CLOCK TRANSFERS... 40 FIGURE 2-15: SIGNAL PROPAGATION TIME EFFECTS ON SOURCE-SYNCHRONOUS TRANSFERS... 40 FIGURE 2-16: PCI-X 266 START OF DATA STROBES... 42 FIGURE 2-17: PCI-X 533 START OF DATA STROBES... 42 FIGURE 2-18: PCI-X 266 END OF DATA STROBES, FOUR OR MORE DATA PHASES... 43 FIGURE 2-19: PCI-X 266 END OF DATA STROBES, THREE DATA PHASES... 43 FIGURE 2-20: PCI-X 266 END OF DATA STROBES, TWO DATA PHASES... 44 FIGURE 2-21: PCI-X 266 END OF DATA STROBES, ONE DATE PHASE... 44 FIGURE 2-22: PCI-X 533 END OF DATA STROBES, FOUR OR MORE DATA PHASES... 45 FIGURE 2-23: PCI-X 533 END OF DATA STROBES, THREE DATA PHASES... 45 FIGURE 2-24: PCI-X 533 END OF DATA STROBES, TWO DATA PHASES... 46 FIGURE 2-25: PCI-X 533 END OF DATA STROBES, ONE DATA PHASES... 46 FIGURE 2-26: CROSSTALK-INDUCED TRANSIENTS ON DATA STROBE INPUTS... 54 FIGURE 2-27: 1.5V ENVIRONMENT MAXIMUM AC WAVEFORMS... 55 FIGURE 2-28: PCI-X 266 TIMING PARAMETERS... 59 FIGURE 2-29: PCI-X 533 TIMING PARAMETERS... 60 FIGURE 2-30: 1.5V SIGNALING OUTPUT V TEST CROSSING... 62 FIGURE 2-31: 1.5V COMMON-CLOCK OUTPUT TIMING MEASUREMENT CONDITIONS... 63 FIGURE 2-32: 1.5V COMMON-CLOCK INPUT TIMING MEASUREMENT CONDITIONS... 63 FIGURE 2-33: SOURCE-SYNCHRONOUS OUTPUT TIMING MEASUREMENT CONDITIONS... 64 FIGURE 2-34: SOURCE-SYNCHRONOUS INPUT TIMING MEASUREMENT CONDITIONS... 64 FIGURE 2-35: DATA STROBE INPUT TRANSIENT REJECTION MEASUREMENT CONDITIONS65 FIGURE 2-36: 1.5V ENVIRONMENT V I/O EXTERNAL DECOUPLING CAPACITANCE TEST CIRCUIT... 67 FIGURE 2-37: 1.5V OUTPUT DC TEST LOAD... 67 FIGURE 2-38: 1.5V OUTPUT AC TEST LOAD... 68 6

FIGURE 2-39: PCI-X 533 DEVICE INTERNAL TIMING & I/O INTERFACE LOGIC STATES FOR DRIVER... 70 FIGURE 2-40: PCI-X 533 DEVICE INTERNAL TIMING & I/O INTERFACE LOGIC STATES FOR RECEIVER... 71 FIGURE 2-41: TRACE SPACING AND HEIGHT... 80 FIGURE 2-42: ADD-IN CARD EDGE CONNECTOR PLANE SPACING... 81 FIGURE 2-43: CLOCK UNCERTAINTY DIAGRAM... 82 FIGURE 2-44: RST# TIMING FOR SWITCHING TO PCI-X MODE... 83 FIGURE 2-45: MODE 1 NOISE BUDGET... 87 FIGURE 2-46: MODE 2 CATEGORY 1 NOISE BUDGET... 88 FIGURE 2-47: 1.5V ENVIRONMENT T PROP MEASUREMENT... 91 FIGURE 2-48: WORST CASE SOURCE-SYNCHRONOUS INPUT SETUP- AND HOLD-TIME RISE AND FALL CONDITIONS... 94 FIGURE 2-49: PCIXCAP CONNECTION FOR ADD-IN CARDS... 97 FIGURE 2-50: V I/O DECOUPLING... 103 FIGURE 3-1: PCI-X ADD-IN CARD IDENTIFICATION MARKING REUIREMENT... 111 FIGURE 3-2: 32-BIT 3.3V LOW PROFILE, SHORT (VARIABLE HEIGHT), AND STANDARD LENGTH ADD-IN CARD WITH PCI-X MARKING... 111 FIGURE 3-3: MINI PCI TYPE I, TYPE II, AND TYPE III ADD-IN CARDS WITH PCI-X MARKING... 112 FIGURE 3-4: MULTIPLE ADD-IN CARDS IN SLOTS... 112 FIGURE A-1: THREE-LEVEL COMPARATOR CIRCUIT... 114 FIGURE A-2: THREE-LEVEL COMPARATOR VOLTAGE RANGES... 114 FIGURE A-3: PROGRAMMABLE PULL-UP CIRCUIT... 115 FIGURE A-4: THRESHOLD RANGES WITH PROGRAMMABLE PULL-UP... 116 FIGURE A-5: FIVE-LEVEL COMPARATOR CIRCUIT... 117 FIGURE A-6: PCIXCAP AND COMPARATOR THRESHOLD VOLTAGES, MODE 2... 118 FIGURE B-1: EXAMPLE SIX-LAYER STACK-UP USING MICROSTRIP AND DUAL STRIPLINE... 119 FIGURE B-2: EXAMPLE EIGHT-LAYER STACK-UP... 121 FIGURE C-1: INPUT STAGING REGISTERS FOR PCI-X 266 DEVICE... 124 FIGURE C-2: INPUT STAGING REGISTERS FOR PCI-X 533 DEVICE... 125 FIGURE C-3: INPUT STAGING REGISTER TIMING EXAMPLE, NO WAIT STATES... 127 FIGURE C-4: INPUT STAGING REGISTER TIMING EXAMPLE, TWO WAIT STATES... 129 FIGURE C-5: MODE 2 CATEGORY 1 I/O BUFFER BLOCK EXAMPLE... 130 FIGURE C-6: V I/O POWER GRID IMPEDANCE AS SEEN BY THE DIE WITHOUT ON-DIE DECOUPLING CAPACITANCE... 134 FIGURE C-7: V I/O POWER GRID IMPEDANCE AS SEEN BY THE DIE 100 PF DECOUPLING CAPACITANCE PER I/O PAD... 135 FIGURE C-8: V I/O POWER GRID IMPEDANCE AS SEEN BY THE DIE AS DECOUPLING CAPACITANCE VARIES FROM 0 PF TO 250 PF PER I/O PAD... 136 FIGURE C-9: V I/O POWER GRID IMPEDANCE AS SEEN BY THE DIE AS SERIES RESISTANCE VARIES FROM 1 TO 25 Ω PER CAPACITOR, 100 PF PER I/O PAD... 137 FIGURE C-10: EXAMPLE ACTUAL TIME OF JITTERING CLK EDGES ILLUSTRATED ON A CONTINUOUS TIME SCALE... 139 7

FIGURE C-11: EXAMPLE OF PHASE JITTER... 140 FIGURE C-12: EXAMPLE OF PHASE AND PERIOD JITTER... 141 FIGURE C-13: EXAMPLE OF PHASE, PERIOD, AND CYCLE-TO-CYCLE JITTER... 142 FIGURE C-14: JITTER IN A COMMON-CLOCK TRANSFER... 143 FIGURE C-15: PLL TRANSFER FUNCTION EXAMPLES... 145 FIGURE C-16: MODEL FOR PLL TRACKING ERROR... 146 FIGURE C-17: PLL TRACKING ERROR TRANSFER FUNCTION EXAMPLES... 146 FIGURE C-18: EXAMPLE CLOCK PHASE JITTER, TIME DOMAIN... 147 FIGURE C-19: EXAMPLE CLOCK PHASE JITTER, FREUENCY DOMAIN... 148 FIGURE C-20: PLL TRACKING ERROR, FREUENCY DOMAIN... 148 FIGURE C-21: PLL TRACKING ERROR, TIME DOMAIN... 149 FIGURE C-22: PLL TRACKING ERROR, TIME DOMAIN, MAGNIFIED... 149 FIGURE D-1: 1.5V SIGNALING ENVIRONMENT RINGBACK... 156 FIGURE D-2: 1.5V SIGNALING INPUT THRESHOLD CROSSING, CHORD METHOD... 158 FIGURE D-3: 1.5V SIGNALING INPUT THRESHOLD CROSSING, EXTRAPOLATION METHOD, RISING EDGE... 160 FIGURE D-4: 1.5V SIGNALING INPUT THRESHOLD CROSSING, EXTRAPOLATION METHOD, FALLING EDGE... 161 8

Tables TABLE 1-1: CONVENTIONAL PCI AND PCI-X COMPARISON SUMMARY... 11 TABLE 1-2: SUPPORTED PCI-X MODES AND FEATURES... 12 TABLE 1-3: EXAMPLE PCI-X 533 GOAL NOTATIONAL CONVENTION... 14 TABLE 2-1: DRIVER AND RECEIVER CATEGORIES... 21 TABLE 2-2: 3.3V DC SPECIFICATIONS FOR PCI-X DEVICES... 23 TABLE 2-3: 3.3V OUTPUT SLEW RATES... 24 TABLE 2-4: 3.3V AC SPECIFICATIONS... 25 TABLE 2-5: CLOCK SPECIFICATIONS, MODE 1... 29 TABLE 2-6: CLOCK SPECIFICATIONS, MODE 2... 30 TABLE 2-7: 3.3V GENERAL TIMING PARAMETERS... 32 TABLE 2-8: 3.3V MEASUREMENT CONDITION PARAMETERS... 35 TABLE 2-9: T VAL DELAY PATHS, MODE 1... 37 TABLE 2-10: T SU AND T H DELAY PATHS, MODE 1... 38 TABLE 2-11: SOURCE-SYNCHRONOUS SIGNALING GROUPS, MODE 2... 41 TABLE 2-12: 1.5V DC SPECIFICATIONS... 50 TABLE 2-13: 1.5V AC SPECIFICATIONS... 51 TABLE 2-14: 1.5V TIMING PARAMETERS FOR COMMON-CLOCK SIGNALING... 56 TABLE 2-15: SOURCE-SYNCHRONOUS INITIATOR OUTPUT TIMING, PCI-X 533... 57 TABLE 2-16: SOURCE-SYNCHRONOUS INITIATOR OUTPUT TIMING, PCI-X 266... 58 TABLE 2-17: SOURCE-SYNCHRONOUS TARGET INPUT TIMING... 61 TABLE 2-18: 1.5V MEASUREMENT CONDITION PARAMETERS... 65 TABLE 2-19: T VAL DELAY PATHS FOR C/BE#, MODE 2 COMMON CLOCK... 69 TABLE 2-20: T SU AND T H DELAY PATHS FOR C/BE#, MODE 2 COMMON CLOCK... 72 TABLE 2-21: T IDVFH AND T IFHDX DELAY PATHS, MODE 2 SOURCE SYNCHRONOUS... 73 TABLE 2-22: T TDVFH AND T TFHDX DELAY PATHS, MODE 2 SOURCE SYNCHRONOUS... 74 TABLE 2-23: ADD-IN CARD TRANSMISSION LINE SPECIFICATIONS... 76 TABLE 2-24: ADD-IN CARD TRACE LENGTH LIMITS... 77 TABLE 2-25: ADD-IN CARD SIGNAL ELECTRICAL LENGTH MATCHING AND SEPARATION, MODE 2... 78 TABLE 2-26: MODE 2 ADD-IN CARD TRACE SPACING AND HEIGHT... 80 TABLE 2-27: CLOCK UNCERTAINTY PARAMETERS... 82 TABLE 2-28: IDSEL TO AD BIT ASSIGNMENT... 85 TABLE 2-29: MODE 1 SYSTEM NOISE BUDGET... 86 TABLE 2-30: SETUP TIME BUDGET, MODE 1 OPERATION... 89 TABLE 2-31: HOLD TIME BUDGET, MODE 1 OPERATION... 90 TABLE 2-32: COMMON-CLOCK SETUP TIME BUDGET, MODE 2 OPERATION... 91 TABLE 2-33: COMMON-CLOCK HOLD TIME BUDGET, MODE 2 OPERATION... 92 TABLE 2-34: SOURCE-SYNCHRONOUS SETUP TIME BUDGET, MODE 2... 94 TABLE 2-35: SOURCE-SYNCHRONOUS HOLD TIME BUDGET, MODE 2... 95 TABLE 2-36: SOURCE-SYNCHRONOUS DATA STROBE SETUP TO CLK BUDGET, MODE 2 96 TABLE 2-37: MAXIMUM TRACE LENGTHS FOR PCIXCAP COMPONENTS... 97 TABLE 2-38: PCIXCAP PULL-DOWN RESISTOR VALUES... 98 9

TABLE 2-39: PCIXCAP FET CHARACTERISTICS FOR PCI-X MODE 2... 98 TABLE 2-40: ADD-IN CARD POWER SUPPLY LIMITS... 99 TABLE 2-41: PCI-X MODE 2 V I/O REUIREMENTS... 102 TABLE 2-42: PCI-X PIN MULTIPLEXING AND SHARING... 105 TABLE 2-43: ADD-IN CARD CONNECTOR PIN OUT... 106 TABLE A-1: COMPARATOR RESISTORS AND THRESHOLDS... 115 TABLE A-2: COMPARATOR VOLTAGE MARGIN... 118 TABLE A-3: COMPARATOR OUTPUT DECODING, MODE 2... 118 TABLE B-1: TRACE SPACING FOR PARALLEL TRACES ON DUAL STRIPLINE... 120 TABLE C-1: I/O BUFFER BLOCK PIN-OUT... 131 TABLE C-2: I/O BUFFER BLOCK OUTPUT CASE SETTINGS... 132 TABLE C-3: I/O BUFFER BLOCK INPUT CASE SETTINGS... 132 TABLE C-4: PLL TRANSFER FUNCTION EXAMPLES... 145 TABLE C-5: SUMMARY OF PHASE TRACKING ERROR RESULTS... 150 TABLE D-1: EXAMPLE OF SYSTEM-LEVEL NOISE ALLOCATION... 152 TABLE D-2: EXAMPLE OF DEVICE-LEVEL NOISE ALLOCATION... 152 TABLE D-3: EXPECTED ACTUAL INPUT SIGNALING CONDITIONS... 155 TABLE D-4: SUMMARY OF V TEST CROSSING MEASUREMENT METHODS... 162 TABLE D-5: MODE 2 SYSTEM BOARD SIGNAL ELECTRICAL LENGTH MATCHING AND SEPARATION... 164 TABLE D-6: MODE 2 TRACE SPACING AND HEIGHT... 166 10

1 1. Introduction The PCI-X Electrical and Mechanical Addendum to the PCI Local Bus Specification, Revision 2.0a (PCI-X EM 2.0a), together with the PCI-X Protocol Addendum to the PCI Local Bus Specification, Revision 2.0a (PCI-X PT 2.0a), define enhancements to the PCI Local Bus Specification, Revision 2.3 (PCI 2.3), the PCI to PCI Bridge Architecture Specification, Revision 1.1 (PCI Bridge 1.1), the PCI Power Management Interface Specification, Revision 1.1 (PCI PM 1.1), and the PCI Hot-Plug Specification, Revision 1.1 (PCI HP 1.1), which are the latest versions of these specifications at the time of release of this document. Contact the PCI-SIG for any later revisions. PCI-X EM 2.0a and PCI-X PT 2.0a are collectively referred to as PCI-X 2.0 and together replace the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b (PCI-X 1.0b). A brief introduction to PCI-X Mode 1 and Mode 2 appears below. See PCI-X PT 2.0a for additional introductory material on PCI-X 2.0. PCI-X 2.0 defines two modes of operation. Mode 1 is the mode of operation defined in previous versions of the PCI-X definition. Table 1-1 compares maximum transfer rates and signaling levels among all the conventional and PCI-X modes. Table 1-1: Conventional PCI and PCI-X Comparison Summary Maximum Transfer Rate (MB/s) Mode Signaling Level 64-Bit Bus 32-Bit Bus 16-Bit Bus Conventional PCI 33 (ref) 5 V or 3.3 V 266 133 na Conventional PCI 66 (ref) 3.3 V 533 266 na PCI-X 66 3.3 V 533 266 na PCI-X 133 3.3 V 1066 533 na PCI-X 266 1.5 V and 3.3 V 2133 1066 533 PCI-X 533 1.5 V and 3.3 V 4266 2133 1066 11

Table 1-2 shows the supported combinations of modes and features for PCI-X. Table 1-2: Supported PCI-X Modes and Features Feature PCI-X Mode 1 PCI-X Mode 2 Device types PCI-X 66 PCI-X 133 PCI-X 266 PCI-X 533 64-bit optional 32-bit: Bus width 64-bit optional Required for add-in card applications. Optional for embedded applications 32-bit required 16-bit: Required for non-bridge devices. Optional for bridge secondary interface. Interface Signaling 3.3 V 1.5 V and 3.3 V Error protection Parity required ECC optional ECC required Data capture Common-clock Common-clock and source-synchronous 12-bit Configuration Space address Not supported Required Device ID messages Optional Required 1.1. Documentation Conventions In addition to the documentation conventions established in PCI 2.3, the following conventions are used in this document: Numbers and number bases Buses Hexadecimal numbers are written with a lower case h suffix, e.g., FFFFh and 80h. Hexadecimal numbers larger than four digits are represented with a space dividing each group of four digits, as in 1E FFFF FFFFh. Binary numbers are written with a lower case b suffix, e.g., 1001b and 10b. Binary numbers larger than four digits are represented with a space dividing each group of four digits, as in 1000 0101 0010b. All other numbers are decimal. As in PCI 2.3, collections of signals that are collectively driven and received are assigned the same signal name with numbers in brackets to indicate the bit or bits affected, e.g., AD[31::00], C/BE[7::4]#, and AD[2]. 12

Capitalization Reference information Clock numbering Names of transaction commands and target termination methods are presented with the first letter capitalized and the rest lower case, e.g., Memory Read Block, Memory Write Block, Retry, Target-Abort, and Single Data Phase Disconnect. As in PCI 2.3, register names and the names of fields and bits in registers and attributes are presented with the first letter capitalized and the rest lower case, e.g., PCI-X Status register, PCI-X Command register, Byte Count field, Bus Number field, and No Snoop attribute bit. Some other terms are capitalized to distinguish their definition in the context of this document from their common English meaning. These terms are listed in Section 1.2. Words not capitalized have their common English meaning. When terms such as memory write or memory read appear completely in lower case, they include all transactions of that type. For example, transactions using the Memory Write, Memory Write Block, and Alias to Memory Write Block commands are all included by the phrase, memory write transactions. Reference information is provided in various places to assist the reader and does not represent a requirement of this document. Such references are indicated by the abbreviation (ref). For example, in some places a clock that is specified to have a minimum period of 15 ns also includes the reference information maximum clock frequency of 66 MHz (ref). Requirements of other specifications also appear in various places throughout this document and are marked as reference information. Every effort has been made to guarantee that this information accurately reflects the referenced document. However, in case of discrepancy, the original document takes precedence. As in PCI 2.3, this document designates the clock that a particular event occurs based on its appearance on the bus. For example, if as a result of a particular clock edge, N, a device changes its output state to begin asserting a signal, that device is said to assert the signal on clock N+1 or the signal is said to be asserted on clock N+1. In PCI-X Mode 2, each source-synchronous data phase contains multiple subphases. For these data phases, a device is said to drive data between clocks N and N+1 even if the actual output delay is such that one or more subphases are delayed past clock N+1. 13

Device types PCI-X 266 requirements and PCI-X 533 design goals As in conventional PCI, PCI-X devices are required to operate up to a maximum frequency (down to a minimum clock period). The system is permitted to operate the bus at a lower frequency to compensate for additional bus loading. This document refers to the type of the device as either conventional or PCI-X and the appropriate maximum data transfer rate. Conventional PCI 33 Conventional PCI 66 PCI-X 66 PCI-X 133 PCI-X 266 PCI-X 533 In all cases, the actual operating clock frequency is between the minimum and maximum specified for that device. This document includes requirements for PCI-X 266 devices. It also includes design goals for PCI-X 533 devices. Future versions of this specification will replace these PCI-X 533 design goals with actual requirements. Design goals for PCI-X 533 devices are marked (goal) or appear in a shaded background as shown below, or both. PCI-X 533 (goal) PCI-X 266 Min Max Min Max Unit 7.5 20 7.5 20 ns 7.375 7.375 ns 3 3 ns Table 1-3: Example PCI-X 533 Goal Notational Convention 1.2. Terms and Abbreviations The following terms and abbreviations are used throughout this specification: attribute The 36-bit field driven on the bus during the attribute phase(s) of a PCI-X transaction. Used for further definition of the transaction. attribute The clock after the address phase(s). phase 14

burst push transaction burst transaction common clock data phase data subphase A burst transaction for which the initiator is the source of the data. Burst push transactions use one of the following commands: Memory Write Memory Write Block Alias to Memory Write Block Split Completion Device ID Message In PCI-X Mode 2, all burst push transactions except Memory Write transactions use source-synchronous clocking. No other transactions use source-synchronous clocking. A transaction using one of the following commands: Memory Read Block Memory Write Block Memory Write Alias to Memory Read Block Alias to Memory Write Block Split Completion Device ID Message Burst transactions can generally be of any length, from 1 to 4096 bytes. (Note that if the byte count is small enough, a burst transaction contains only a single data phase.) On 64-bit buses, they are permitted to be initiated both as 64-bit and 32-bit transactions. A data transfer method in which the devices that are the source and destination of the data use a single centrally generated clock. See also source synchronous. Each clock in which the target signals some kind of data transfer or terminates the transaction. Clocks in which the target signals Wait State one or more times and then signals something else are part of the same data phase. See also data subphase. One of multiple data transfer times within a single data phase. Data subphases use source-synchronous clocking and are used only in PCI-X Mode 2 for burst push transactions other than Memory Write. Mode Number of Data Subphases per Data Phase PCI-X 66 none PCI-X 133 none PCI-X 266 2 PCI-X 533 4 15

device disable receiver drive DWORD DWORD transaction A component of a PCI system that connects to a PCI bus. As defined by PCI 2.3, a device can be a single function or a multifunction device. All devices must be capable of responding as a target to some transactions on the bus. Many devices are also capable of initiating transactions on the bus. A PCI-X device also supports the requirements of this document. As in PCI 2.3, the term device is often used when describing requirements that apply individually to all functions within the device. Unless otherwise specified, requirements in the PCI-X definition for a device apply to single function devices and to each function individually of a multifunction device. In PCI-X Mode 2, the state of a Category 1 input buffer (as defined in Table 2-1) in which the device ignores the state of the input signal. PCI-X Mode 2 protocol enables devices to determine when signals are not being driven and to take appropriate action to guard against illegal logic levels. The precise action required by each device depends upon the design of the receiver. See Section 2.1.3.3. When a device has acquired exclusive ownership of a bus through a handshake with the bus arbiter or the initiator of a transaction, and when the target of a read transaction has reached the appropriate point in the read transaction, the device is said to drive the bus by placing its output buffers in a low impedance state to put the bits of the bus in the appropriate logic level. Four bytes of data on a naturally aligned four-byte boundary (i.e., the least significant two bits of the address are 00b). A transaction using one of the following commands: Interrupt Acknowledge Special Cycle I/O Read I/O Write Configuration Read Configuration Write Memory Read DWORD DWORD transactions address no more than a single DWORD and on 64- and 32-bit buses are permitted to be initiated only as 32-bit transactions (RE64# must be deasserted). During the attribute phase, the Requester Attributes contain valid byte enables. During the data phase, the C/BE# bus is reserved and driven high by the initiator. 16

ECC ECC mode float initiator parity mode PCI-X initialization pattern PCI-X Mode 1 Error correcting code. In ECC mode, each address, attribute, common-clock data phase, and source-synchronous data subphase include additional bits that are used to correct (if enabled) any single bit errors and detect any double bit errors. The mode of operation of the bus that uses ECC error protection. A bus operating in PCI-X Mode 1 operates either in parity mode or ECC mode, as determined by a bit in the ECC Control and Status register. A bus operating in PCI-X Mode 2 always operates in ECC mode. When a device has finished driving a bus or a control signal and it places the output buffers in the high-impedance state, the device is said to float the bus or the control signal. A device that initiates a transaction by requesting the bus, asserting FRAME#, and driving the command and address. A bridge forwarding a transaction is an initiator on the destination bus. The mode of operation of the bus that uses parity error protection. A bus operating in PCI-X Mode 1 operates either in parity mode or ECC mode, as determined by a bit in the ECC Control and Status register. A bus operating in PCI-X Mode 2 never operates in parity mode. A combination of bus control signals that is used to place PCI-X devices in PCI-X Mode 1 (with parity or ECC protection) or Mode 2 at the rising edge of RST#. Also indicates the range of frequency of the clock. A mode of operation compliant with revisions of this document prior to revision 2.0. It includes: PCI-X 66 and PCI-X 133 modes Data transfers always use common clock 3.3V signaling levels Optional ECC (added in revision 2.0) Devices compliant with revision 1.0 of this specification are automatically compliant with this revision in PCI-X Mode 1. Sometimes abbreviated as Mode 1 when the meaning is clear from the context. When used as an adjective, for example Mode 1 device, Mode 1 add-in card, Mode 1 system, or Mode 1 slot, it defines an object whose highest operating mode is either PCI-X 66 or PCI-X 133, whether or not that object is actually operating in PCI-X Mode 1. 17

PCI-X Mode 2 A mode of operation compliant with revision 2.0 of this document that includes: PCI-X 266 and PCI-X 533 modes Burst push transactions other than Memory Write use sourcesynchronous clocking 1.5V signaling levels for source-synchronous signals ECC All features not defined in revisions of this document prior to revision 2.0 apply in PCI-X Mode 2. (Some are optionally available in Mode 1, also.) Sometimes abbreviated as Mode 2 when the meaning is clear from the context. When used as an adjective, for example Mode 2 device, Mode 2 add-in card, Mode 2 system, or Mode 2 slot, it defines an object whose highest operating mode is either PCI-X 266 or PCI-X 533, whether or not that object is actually operating in PCI-X Mode 2. source bridge source synchronous system system board The bridge that creates a bus segment capable of PCI-X operation in a system hierarchy. The source bridge is required to initiate Type 0 configuration transactions on that bus segment. (Other devices optionally initiate Type 0 configuration transactions.) A host bridge is the source bridge for the PCI bus it creates. A PCI-X bridge is the source bridge for its secondary bus. A data transfer method in which the device that is the source of the data also drives strobes to be used for latching the data at the destination. Source-synchronous transactions use sourcesynchronous sampling for the AD and ECC buses in PCI-X Mode 2 for data phases of burst push transactions other than Memory Write. They use common-clock sampling for the AD and ECC buses during all other data phases and all address and attribute phases. They use common-clock sampling for the control signal during all phases. See also common clock. Any functional combination of a system board, add-in cards, and/or software. A collection of hardware that includes a CPU, host bridge, and a PCI bus. In some system boards, the bus includes one or more devices in addition to the source bridge. In some system boards the bus connects to one or more add-in card slots. The term is often used in dividing responsibilities between the system-board vendor and the add-in card vendor. See for example the system noise budgets in Sections 2.3.5.1 and 2.3.5.2. 18

target transaction A device that responds to bus transactions. A bridge forwarding a transaction is the target on the originating bus. A combination of address, attribute, target response, data, and bus turn-around phases associated with a single assertion of FRAME#. 1.3. Figure Legend The following conventions for the state of a signal at clock N are used in PCI-X Mode 1 timing diagrams throughout this document. N-1 N N+1 system clock rising edge triggered driven high signal driven low signal low signal state being driven high before being floated driven signal to an undefined state driven signal to a defined state driven signal to an undefined state or floated floated signal, high state maintained by system pull-up resistors floated signal, state unknown reserved for signal or bus turn-around. Neither owner drives the signal or bus on this clock. The time at which the previous owner stops driving and the next owner starts driving is shown by the state of the signal or bus in previous and subsequent clocks, respectively. Figure 1-1: Figure Legend, Mode 1 19

The following conventions for the state of a signal at clock N are used in PCI-X Mode 2 timing diagrams throughout this document. N-1 N N+1 system clock rising edge triggered Unterminated Signals floated signal, high state maintained by pull-up resistors driven low signal low signal state being driven high before being floated reserved for signal turn-around. Neither owner drives the signal on this clock. The time at which the previous owner stops driving and the next owner starts driving is shown by the state of the signal or bus in previous and subsequent clocks, respectively. Terminated Signals driven signal to an undefined state signal terminated, receiver on driven signal to a defined state signal terminated, receiver on driven signal to a defined state (PCI-X 266) signal terminated, receiver on driven signal to a defined state (PCI-X 533) signal terminated receiver on driven signal to an undefined state or floated signal terminated, receivers off floated signal, state unknown signals terminated, receivers off reserved for signal turn-around (floated signal) signal terminated, receivers off Neither owner drives the signal or bus on this clock. The time at which the previous owner stops driving and the next owner starts driving is shown by the state of the signal or bus in previous and subsequent clocks, respectively. Figure 1-2: Figure Legend, Mode 2 20

2 2. Electrical Specification 2.1. Device Requirements 2.1.1. Driver and Receiver Categories Different groups of signals on the bus have different driver and receiver requirements as shown in Table 2-1. This specification defines two signaling environments, 3.3V and 1.5V. Category 1 signals use 3.3V signaling when operating in PCI-X Mode 1 and 1.5V signaling when operating in PCI-X Mode 2. Category 2 and 3 signals use 3.3V signaling in both modes. 1 Category Supply Voltage Table 2-1: Driver and Receiver Categories Output Type Input Terminator Signals Notes Mode 1 3.3 V Totem pole No AD, C/BE#, PAR64/ECC[7], 1 RE64#/ECC[6], ECC[5::2], Mode 2 1.5 V Totem pole Yes ACK64#/ECC[1], PAR/ECC[0] 2 2 3.3 V Totem pole No FRAME#, IRDY#, DEVSEL#, TRDY#, STOP#, IDSEL, PERR#, LOCK#, RE#, GNT#, RST#, CLK 3 3.3 V Open drain No SERR#, INTx# 4 4 5 See PCI 2.3 See PCI PM 1.1 See PCI 2.3 See PCI PM 1.1 See PCI 2.3 See PCI PM 1.1 M66EN, PRSNT[1::2]#, TCK, TDI, TDO, TMS, TRST#, SMBCLK, SMBDAT PME# 6 na na na PCIXCAP, MODE2 6 Notes: 1. In Mode 1, these signals exclusively use common-clock timing. 2. In Mode 2, these signals use source-synchronous timing for data phases of source-synchronous transactions and common-clock timing in all other cases. All electrical terminators and input receivers for the upper bus are disabled under some conditions (see Section 2.12, Bus Width, in PCI-X PT 2.0a). Inputs use a differential receiver with a fixed reference voltage of V ref, as specified in Table 2-12. See Section 2.3.2 for special requirements for RE64#/ECC[6] at the rising edge of RST#. 3. These signals (except CLK) exclusively use common-clock timing. 3 5 21

4. As in conventional mode, SERR# asserts synchronously with CLK. The rising edge of SERR# and both edges of INTx# signals are asynchronous with respect to CLK. 5. JTAG signals use 3.3V signaling levels in PCI-X Mode 1 and Mode 2. 6. These are static card identification pins and do not connect to the PCI-X devices other than the central resource or hot-plug controller. See Section 2.4. IMPLEMENTATION NOTE Category 1 Signals in 16-Bit-Only Devices As described in Section 2.12.2, 16-Bit Bus Width, in PCI-X PT 2.0a, 16-bit buses operate exclusively in PCI-X Mode 2. Therefore, Category 1 signals in 16-bit-only devices operate exclusively with the 1.5V signaling environment. Category 1 signals for such devices are exempt from all the Mode 1 requirements listed here and can be optimized for lower-voltage operation. Category 1 signals use both source-synchronous and common-clock timing in Mode 2, so there is no exemption of any of the timing requirements for these signals. 2.1.2. 3.3V Signaling Environment 2.1.2.1. 3.3V DC Specifications Table 2-2 shows the DC specifications for the 3.3V signaling environment for devices operating in PCI-X mode. Conventional 3.3V signaling DC specifications are included for reference. Unless otherwise specified, all requirements are measured at the device pin. 22

Table 2-2: 3.3V DC Specifications for PCI-X Devices PCI-X 3.3V Conventional PCI (ref) Sym Parameter Condition Min Max Min Max Units Notes V cc V ih V il Vipu I il V oh V ol C in C clk CIDSEL Supply Voltage Input High Voltage Input Low Voltage Input Pull-up Voltage Input Leakage Current Output High Voltage Output Low Voltage Input Pin Capacitance CLK Pin Capacitance IDSEL Pin Capacitance 3.0 3.6 3.0 3.6 V 0.5V cc V cc + 0.5 0.5V cc V cc + 0.5 V -0.5 0.35V cc -0.5 0.3V cc V 0.7V cc 0.7V cc V 1 0 < V in < V cc ±10 ±10 µa 2 I out = -500 µa 0.9V cc 0.9V cc V I out = 1500 µa 0.1V cc 0.1V cc V 8 10 pf 3 5 8 5 12 pf 8 8 pf 4 L pin Pin Inductance 15 20 nh 5 I Off PME# input leakage V o 3.6 V V cc off or floating 1 1 µa 6 Notes: 1. This specification should be guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated network. Applications sensitive to static power utilization must assure that the input buffer is conducting minimum current at this input voltage. 2. Input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. 3. Absolute maximum pin capacitance for a PCI/PCI-X input except CLK and IDSEL. 4. For conventional PCI only, lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx]. PCI-X configuration transactions drive the AD bus four clocks before FRAME# asserts (see Section 2.7.2.1, Configuration Transaction Timing, in PCI-X PT 2.0a). 5. For conventional PCI, this is a recommendation not an absolute requirement. For PCI-X, this is a requirement. 6. This input leakage is the maximum allowable leakage into the PME# open drain driver when power is removed from V cc of the component. This assumes that no event has occurred to cause the device to attempt to assert PME#. 23

2.1.2.2. 3.3V AC Specifications The output drive characteristics for the 3.3V signaling environment for devices operating in PCI-X mode over the full range of output voltages are shown in Table 2-4 and Table 2-3. Conventional PCI 66 MHz values are included for reference. For clarity, AC output characteristic equations define lines that pass through the origin. Actual device requirements when the output voltage is above V oh (min) or below V ol (max) are specified in the DC characteristics (Table 2-2). As in conventional PCI, the DC characteristics are the only conditions under which steady-state operation is intended. The higher current portions of the AC characteristics are intended to be reached only during switching transients. Unless otherwise specified, all requirements are measured at the device pin. Table 2-3: 3.3V Output Slew Rates PCI-X Conventional PCI 66 (ref) Symbol Parameter Condition Min Max Min Max Units Notes slew r slew f Output Rise Slew Rate Output Fall Slew Rate 0.3V cc to 0.6V cc 1 6 1 4 V/ns 1 0.6V cc to 0.3V cc 1 6 1 4 V/ns 1 Note: 1. This parameter is to be interpreted as the cumulative edge rate across the specified range rather than the instantaneous rate at any point within the transition range. The test load is specified in Figure 2-11 (66 MHz reference values use the test load in Figure 2-10). The specified load is optional. The designer may elect to meet this parameter with an unloaded output per revision 2.0 of the PCI Local Bus Specification. However, adherence to both maximum and minimum parameters is required (the maximum is not simply a guideline). Rise slew rate does not apply to open drain outputs. 24

Table 2-4: 3.3V AC Specifications Symbol Parameter Condition Min Max Unit Notes PCI-X Output Buffer Drive Currents 0 < V cc -V out 3.6V -74(V cc -V out ) ma I oh(ac) I ol(ac) I cl I ch Switching Current High Switching Current Low Low Clamp Current High Clamp Current 0 < V cc -V out 1.2V -32 (V cc -V out ) ma 1 1.2V < V cc -V out 1.9V 1.9V < V cc -V out 3.6V -11 (V cc -V out ) -25.2 ma 1-1.8 (V cc -V out ) -42.7 ma 1 0 V out 3.6V 100V out ma 0 < V out 1.3V 48 V out ma 1 1.3V < V out 3.6V 5.7 V out + 55 ma 1 Clamp Currents -3V < V in -0.8875V -40 + (V in +1) / 0.005 ma -0.8875V < V in -0.625V 0.8875V V in -V cc < 4V 0.625V V in -V cc < 0.8875V -25 + (V in +1) / 0.015 ma 40 + (V in -V cc -1) / 0.005 25 + (V in -V cc -1) / 0.015 66 MHz Conventional PCI (ref) AC Drive Points ma ma I oh(ac) I ol(ac) V out = 0.7V cc -32V Switching cc ma Current High V out = 0.3V cc -12V cc ma 1 V out = 0.18V cc 38V Switching cc ma Current Low V out = 0.6V cc 16V cc ma 1 Clamp Currents I ch High clamp current V cc +4 > V in V cc +1 25 + (V in -V cc -1) / 0.015 ma I cl Low clamp current -3 < V in -1-25 + (V in +1) / 0.015 ma Note: 1. In conventional PCI switching, current characteristics for RE# and GNT# are permitted to be one half of that specified here; i.e., half size drivers may be used on these signals. In PCI-X devices, RE# and GNT# must have full-size drivers. This specification does not apply to CLK and RST# which are system-board outputs. "Switching Current High" specifications are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD#, which are open drain outputs. 25

Output drive current limits from Table 2-4 are illustrated in Figure 2-1 and Figure 2-2. Conventional PCI 33 MHz 3.3V limits are included for reference. 0 0 0.5 1 1.5 2 2.5 3 3.5-50 Ioh (ma) -100-150 -200 PCI PCI-X -250-300 Vcc - Vout (volt) Figure 2-1: 3.3V PCI-X Pull-Up Output Buffer I/V Curves 400 350 Iol (ma) 300 250 200 150 PCI PCI-X 100 50 0 0 1 2 3 Vout (volt) Figure 2-2: 3.3V PCI-X Pull-Down Output Buffer I/V Curves 26

Figure 2-3 and Figure 2-4 are reference information showing the same output drive characteristics as Figure 2-1 and Figure 2-2 with the axes the same as PCI 2.3. Vout (volt) Vcc x 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 PCI PCI-X 0-20 Vcc -40 Vcc -60 Vcc -80 Vcc -100 Vcc Iout (ma) Figure 2-3: 3.3V PCI-X Pull-Up Output Buffer V/I Curves (ref) Vcc x 1 Vout (volt) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 PCI-X PCI 0 20 Vcc 40 Vcc 60 Vcc 80Vcc 100 Vcc Iout (ma) Figure 2-4: 3.3V PCI-X Pull-Down Output Buffer V/I Curves (ref) 27

2.1.2.3. 3.3V Maximum AC Ratings and Device Protection Maximum AC rating and device protection requirements are the same for the 3.3V signaling environment for PCI-X devices as for conventional PCI devices in a 3.3V signaling environment. 2.1.2.4. 3.3V Timing Specifications 2.1.2.4.1. Clock Specification Clock measurement conditions are the same for PCI-X devices as for conventional PCI devices in a 3.3V signaling environment except for V il specified in Table 2-2. See Figure 2-5. In the case of add-in cards, compliance with the clock specification is measured at the add-in card component package pin, not at the connector. As with conventional PCI, devices used behind a PCI-to-PCI bridge on an add-in card use the clock output specification of the selected bridge rather than the specification shown here. Some PCI-to-PCI bridges have different clock output specifications. The same spread-spectrum clocking techniques are allowed in PCI-X as for 66 MHz conventional PCI. If a device includes a PLL, that PLL must track the input variations of spread-spectrum clocking specified in Table 2-5. Two classes of clock jitter requirements are specified for PCI-X Mode 1 devices. Support of clock jitter class 1 is required for all PCI-X Mode 1 devices. For clock jitter class 1, T cyc in Table 2-5 indicates the minimum and maximum CLK cycle times for the various specified frequencies. The minimum and maximum clock period specifications must not be violated for any single clock cycle. System designers must assure that the system clock period, including all sources of clock period variation (e.g., tolerance and jitter), is always within the minimum and maximum defined ranges. For example, if a specific system clock design has a maximum clock period variation of 180 ps, the maximum that the nominal frequency can be set for such a clock for 133 MHz operation is 1/(7.5 ns + 0.18 ns) = 130.208 MHz. This setting of the nominal frequency accounts for the clock period variation without violating the minimum clock period of 7.5 ns. Support for clock jitter class 2 is optional for all PCI-X Mode 1 devices. For clock jitter class 2, the long-term average minimum period corresponds to the nominal frequency (133 MHz and 66 MHz). Jitter in the clock circuit is allowed to reduce the absolute minimum period below the nominal as shown. Table 2-6 shows the timing requirements for CLK for devices operating in PCI-X Mode 2. Devices operating in Mode 2 have only one clock jitter class, which corresponds to clock jitter class 2 for Mode 1 operation. 28

T cyc T high 3.3 volt Clock 0.6 Vcc T low V ih(min) V test V il(max) 0.4 Vcc peak to peak (minimum) 0.2 Vcc Figure 2-5: Clock Waveform Table 2-5: Clock Specifications, Mode 1 PCI-X 133 PCI-X 66 Conv. PCI 66 (ref) Conv. PCI 33 (ref) Sym Parameter Min Max Min Max Min Max Min Max Unit Notes Clock Jitter Class 1 5 T cyc CLK Cycle Time 7.5 20 15 20 15 30 30 ns 1,3,4 T high CLK High Time 3 6 6 11 ns 4 T low CLK Low Time 3 6 6 11 ns 4 Clock Jitter Class 2 6 T cyc CLK Cycle Average 7.5 20 15 20 15 30 30 ns 1,4,7 Time Absolute minimum 7.375 14.8 14.8 29.7 ns 1,3,4 T high CLK High Time 2.5 5.5 5.5 10 ns 4 T low CLK Low Time 2.5 5.5 5.5 10 ns 4 T jit CLK Period Jitter 125-125 200-200 200-200 300-300 ps 8 Slew Rate - CLK Slew Rate 1.5 4 1.5 4 1.5 4 1 4 V/ns 2,4 Spread Spectrum Requirements f mod Modulation Frequency 30 33 30 33 30 33 khz f spread Frequency Spread -1 0-1 0-1 0 % Notes: 1. For clock frequencies above 33 MHz, the clock frequency may not change beyond the spread-spectrum limits except while RST# is asserted. 2. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown in Figure 2-5. 3. The minimum clock period must not be violated for any single clock cycle, i.e., accounting for all system jitter. 4. All PCI-X 133 devices must also be capable of operating in PCI-X 66. All PCI-X devices must be capable of operating in conventional PCI 33 mode and optionally are capable of conventional PCI 66 mode. 29

5. Support for this jitter class is required for all Mode 1 devices. 6. Support for this jitter class is optional for all Mode 1 devices. 7. Average T cyc is measured over any 1 µs period of time and must include all sources of clock variation. 8. Period jitter is the deviation between any single period of the clock, T cyc, and the average period of the clock, T cyc (average). Table 2-6: Clock Specifications, Mode 2 PCI-X 533 (goal) PCI-X 266 Sym Parameter Min Max Min Max Unit Notes T cyc CLK Cycle Time Average 7.5 20 7.5 20 ns 1, 2, 3 Absolute Minimum 7.375 7.375 ns 1, 2, 4 T high CLK High Time 3 3 ns 2 T low CLK Low Time 3 3 ns 2 T jit CLK Period Jitter 125-125 125-125 ps 6 Slew Rate - CLK Slew Rate 1.5 4 1.5 4 V/ns 5 Spread Spectrum Requirements f mod Modulation Frequency 30 33 30 33 khz f spread Frequency Spread -1 0-1 0 % Notes: 1. The clock frequency must not change beyond the spread-spectrum and jitter limits except while RST# is asserted. 2. All PCI-X 533 and 266 (Mode 2) devices must also be capable of operating in PCI-X 133 and 66 (Mode 1). All PCI-X devices (Mode 1 and Mode 2) must be capable of operating in conventional PCI 33 mode and optionally are capable of conventional PCI 66 mode. 3. Average T cyc is measured over any 1 µs period of time and must include all sources of clock variation. 4. The minimum clock period must not be violated for any single clock cycle, i.e., accounting for all system jitter. 5. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown in Figure 2-5. 6. Period jitter is the deviation between any single period of the clock, T cyc, and the average period of the clock, T cyc (average). 30

IMPLEMENTATION NOTE Meeting Output and Input Timing with a Jitter Class 2 Clock Device output and input timing is specified with respect to the actual rising edge of CLK for both clock jitter classes. Determining device output and input timing requirements relative to CLK depends on the method by which the clock is distributed within the device. Some devices distribute the clock to output and input latches using only fixed-delay elements in the clock path. This technique is common among 33 MHz conventional PCI devices, which are required to tolerate the clock changing frequency or stopping at any time. Devices that have only fixed-delay elements in the clock path calculate output and input time directly from the delays in the output, input, and clock paths. (See Sections 2.1.2.6 and 2.1.3.10.) Other devices distribute a clock internally that is derived from the CLK input. The method by which this internal clock is derived commonly introduces phase errors between the CLK input and the internal clock. These phase errors affect device output and input timing calculations. One example of a method for deriving an internal clock is to use a PLL in the clock distribution path. The output of the PLL is shifted in phase from the actual CLK input. This phase shift typically has three components: 1. Constant phase shift to compensate for delay in the clock distribution path. 2. Varying phase shift caused by tracking error in the PLL (internal PLL jitter). 3. Varying phase shift caused by filtering the jitter in the input CLK (external CLK jitter). Devices that use PLLs in their clock distribution path must accommodate these phase shifts in their output and input timing. In most cases, worst-case timing calculations must assume the full value of any varying phase shift in the clock distribution path, even though the worst case occurs only on some clock edges and not others. Typical system clock synthesizers include various sources of jitter that produce varying magnitudes of phase error at different frequencies. CLK jitter that the internal PLL filters introduces additional phase shift that the device input and output timing must accommodate. CLK jitter that the internal PLL tracks does not introduce additional phase shift and, therefore, can be ignored in the device input and output timing. For example, suppose a PLL has ±100 ps of internal jitter. That is, if the input CLK had no jitter, the rising edge of the output of the PLL would vary from the actual rising CLK edge by ±100 ps. Further suppose that this PLL has a closed-loop bandwidth such that it tracks low frequency jitter on the input CLK and filters high frequency jitter, which is limited to ±70 ps. In other words, the rising edge of the clock reference that this PLL tracks would always be within ±70 ps of the actual rising CLK edge. If such a PLL were used in a PCI-X 266 device, the output and input paths of the device must accommodate both the case in which the internal clock edge is 100 ps + 70 ps ahead of the actual rising CLK edge and the case in which it is 100 ps + 70 ps after the actual rising CLK edge. 31