REVISION ISTORY Revision Description Issue Date Rev. 1.0 Initial Issued Jan.09. 2012 Rev. 1.1 Add 48 pin BGA package type. Mar.12. 2012 Rev. 1.2 1. VCC - 0.2V revised as 0.2 for TEST July.19. 2012 CONDITION of Average Operating Power supply Current Icc1 on page3 2.Revised ORDERING INFORMATION Page11 Rev. 1.3 1. Revise TEST CONDITION for VO, VO on page 3 June. 04. 2013 IO = -8mA revised as -4mA IO =4mA revised as 8mA 2. Revise VI(max) & VI(min) note on page 3 VI(max) = VCC + 2.0V for pulse width less than 6ns. VI(min) = VSS - 2.0V for pulse width less than 6ns. Rev.1.4 Revised the address pin sequence of pin configuration of 48 pin TSOP-I on page 2 in order to be compatible with industry convention. (No function specifications and applications have been changed and all the characteristics are kept all the same as Rev 1.3 ) Oct. 30. 2013 0
FEATURES Fast access time : 10/12ns low power consumption: Operating current: 90/80mA (typical) Standby current: 4mA(Typical) Single 3.3V power supply All inputs and outputs TT compatible Fully static operation Tri-state output Data byte control : B# (DQ0 ~ DQ7) UB# (DQ8 ~ DQ15) Data retention voltage : 1.5V (MIN.) Green package available Package : 48-pin 12mm x 20mm TSOP-I 48-ball 6mmx8mm TFBGA GENERA DESCRIPTION The is a 16M-bit high speed CMOS static random access memory organized as 1024K words by 16 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The operates from a single power supply of 3.3V and all inputs and outputs are fully TT compatible PRODUCT FAMIY Product Operating Power Dissipation Vcc Range Speed Family Temperature Standby(ISB1,TYP.) Operating(Icc1,TYP.) 0 ~ 70 2.7 ~ 3.6V 10/12ns 4mA 90/80mA (I) -40 ~ 85 2.7 ~ 3.6V 10/12ns 4mA 90/80mA FUNCTIONA BOCK DIAGRAM PIN DESCRIPTION SYMBO A0 - A19 DQ0 DQ15 WE# OE# B# UB# VCC VSS DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Input Write Enable Input Output Enable Input ower Byte Control Upper Byte Control Power Supply Ground 1
PIN CONFIGURATION A B# OE# A0 A1 A2 NC B DQ8 UB# A3 A4 DQ0 C DQ9 DQ10 A5 A6 DQ1 DQ2 D Vss DQ11 A17 A7 DQ3 Vcc E Vcc DQ12 NC A16 DQ4 Vss F DQ14 DQ13 A14 A15 DQ5 DQ6 G DQ15 A19 A12 A13 WE# DQ7 A18 A8 A9 A10 A11 NC 1 2 3 4 5 6 TFBGA 2
ABSOUTE MAXIMUN RATINGS* PARAMETER SYMBO RATING UNIT Voltage on Vcc relative to VSS VT1-0.5 to 4.6 V Voltage on any other pin relative to VSS VT2-0.5 to Vcc+0.5 V Operating Temperature TA 0 to 70(C grade) -40 to 85(I grade) Storage Temperature TSTG -65 to 150 Power Dissipation PD 1 W DC Output Current IOUT 50 ma *Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUT TABE MODE OE# WE# B# UB# I/O OPERATION DQ0-DQ7 DQ8-DQ15 SUPPY CURRENT Standby X X X X igh Z igh Z Isb, ISB1, Output Disable X X igh Z igh Z X X igh Z igh Z ICC Read D OUT igh Z igh Z D OUT ICC Write X X X D OUT D IN igh Z D IN D OUT igh Z D IN D IN Note: = VI, = VI, X = Don't care. DC EECTRICA CARACTERISTICS PARAMETER SYMBO TEST CONDITION MIN. TYP. *4 MAX. UNIT Supply Voltage VCC 2.7 3.3 3.6 V Input igh Voltage VI *1 2.2 - VCC+0.3 V Input ow Voltage VI *2-0.3-0.8 V Input eakage Current II VCC VIN VSS - 1-1 µa Output eakage VCC VOUT VSS, IO Current Output Disabled - 1-1 µa Output igh Voltage VO IO = -4mA 2.4 - - V Output ow Voltage VO IO =8mA - - 0.4 V AverageOperating Power supply Current Standby Power Supply Current Icc Icc1 Isb = VI, II/O = 0mA ;f=max 0.2, Other pin is at 0.2V or Vcc-0.2V II/O = 0mA;f=max Vih Other pin is at Vil or Vih ICC -10-110 160 ma -12-100 140 ma -10 90 120 ma -12 80 110 ma - - 80 ma 3
Standby Power Supply Current ISB1 VCC - 0.2V; Other pin is at 0.2V or Vcc-0.2V - 4 40 ma Notes: 1. VI(max) = VCC + 2.0V for pulse width less than 6ns. 2. VI(min) = VSS - 2.0V for pulse width less than 6ns. 3. Over/Undershoot specifications are characterized on engineering evaluation stage, not for mass production test. 4. Typical values are included for reference only and are not guaranteed or tested. Typical valued are measured at VCC = VCC(TYP.) and TA = 25 CAPACITANCE (TA = 25, f = 1.0Mz) PARAMETER SYMBO MIN. MAX UNIT Input Capacitance CIN - 8 pf Input/Output Capacitance CI/O - 10 pf Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS speed Input Pulse evels Input Rise and Fall Times Input and Output Timing Reference evels Output oad 10/12ns 0.2V to Vcc-0.2V 3ns Vcc/2 C = 30pF + 1TT, IO/IO = -8mA/4mA AC EECTRICA CARACTERISTICS (1) READ CYCE -10-12 PARAMETER SYM. MIN. MAX. MIN. MAX. UNIT Read Cycle Time trc 10-12 - ns Address Access Time taa - 10-12 ns Chip Enable Access Time tace - 10-12 ns Output Enable Access Time toe - 4.5-5 ns Chip Enable to Output in ow-z tcz* 2-3 - ns Output Enable to Output in ow-z toz* 0-0 - ns Chip Disable to Output in igh-z tcz* - 4-5 ns Output Disable to Output in igh-z toz* - 4-5 ns Output old from Address Change to 2-2 - ns B#, UB# Access Time tba - 4.5-5 ns B#, UB# to igh-z Output tbz* - 4-5 ns B#, UB# to ow-z Output tbz* 0-0 - ns (2) WRITE CYCE -10-12 PARAMETER SYM. MIN. MAX. MIN. MAX. UNIT Write Cycle Time twc 10-12 - ns Address Valid to End of Write taw 8-10 - ns Chip Enable to End of Write tcw 8-10 - ns Address Set-up Time tas 0-0 - ns Write Pulse Width twp 8-10 - ns 4
Write Recovery Time twr 0-0 - ns Data to Write Time Overlap tdw 6-7 - ns Data old from End of Write Time td 0-0 - ns Output Active from End of Write tow* 2-2 - ns Write to Output in igh-z twz* - 4-5 ns B#, UB# Valid to End of Write tbw 8-10 - ns *These parameters are guaranteed by device characterization, but not production tested. TIMING WAVEFORMS READ CYCE 1 (Address Controlled) (1,2) Address trc taa to Dout Previous Data Valid Data Valid READ CYCE 2 ( and OE# Controlled) (1,3,4,5) Address trc taa B#,UB# tace OE# tba tbz tcz toz toe to toz tbz tcz Dout igh-z Data Valid igh-z Notes : 1.WE#is high for read cycle. 2.Device is continuously selected OE# = low, = low, B# or UB# = low. 3.Address must be valid prior to or coincident with = low, B# or UB# = low transition; otherwise taa is the limiting parameter. 4.tCZ, tbz, toz, tcz, tbz and toz are specified with C = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tcz is less than tcz, tbz is less than tbz, toz is less than toz. 5
WRITE CYCE 1 (WE# Controlled) (1,2,3,5,6) twc Address taw tcw tbw B#,UB# tas twp twr WE# twz TOW Dout (4) igh-z (4) tdw td Din Data Valid WRITE CYCE 2 ( Controlled) (1,2,5,6) twc Address taw tas twr B#,UB# tbw tcw twp WE# Dout twz (4) igh-z tdw td Din Data Valid 6
WRITE CYCE 3 (B#,UB# Controlled) (1,2,5,6) twc Address taw twr B#,UB# tas tcw tbw twp WE# Dout (4) twz igh-z tdw td Din Data Valid Notes : 1.WE#,, B#, UB# must be high during all address transitions. 2.A write occurs during the overlap of a low, low WE#, B# or UB# = low. 3.During a WE# controlled write cycle with OE# low, twp must be greater than twz + tdw to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the, B#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and twz are specified with C = 5pF. Transition is measured ±500mV from steady state. 7
DATA RETENTION CARACTERISTICS PARAMETER SYMBO TEST CONDITION MIN. TYP. MAX. UNIT VCC for Data Retention VDR VCC - 0.2V 1.5-3.6 V Data Retention Current IDR VCC = 1.5V VCC - 0.2V; Other pin is at 0.2V or Vcc-0.2V - 4 40 ma Chip Disable to Data See Data Retention tcdr Retention Time Waveforms (below) 0 - - ns Recovery Time tr trc * - - ns trc * = Read Cycle Time DATA RETENTION WAVEFORM VDR 1.5V Vcc Vcc(min.) Vcc(min.) tcdr tr VI Vcc-0.2V VI 8
PACKAGE OUTINE DIMENSION 48-pin 12mm x 20mm TSOP-I Package Outline Dimension 9
48-ball 6mm 8mm TFBGA Package Outline Dimension 10
ORDERING INFORMATION Package Type 48-pin(12mmx20mm) TSOP-I 48-Ball 6mmx8mm TFBGA Access Time Temperature Packing yontek Item No. (Speed)(ns) Range( ) Type 10 0 ~70 Tray -10 Tape Reel -10T -40 ~85 Tray -10I Tape Reel -10IT 12 0 ~70 Tray -12 Tape Reel -12T -40 ~85 Tray -12I Tape Reel -12IT 10 0 ~70 Tray G-10 Tape Reel G-10T -40 ~85 Tray G-10I Tape Reel G-10IT 12 0 ~70 Tray G-12 Tape Reel G-12T -40 ~85 Tray G-12I Tape Reel G-12IT 11
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