VHDL for Synthesis Course Description This course provides all necessary theoretical and practical know how to write an efficient synthesizable HDL code through VHDL standard language. The course goes into great depth and teaches efficient methods for writing VHDL code in a way that produces the precise digital circuit for various constraints like high frequency, low power, and minimal area. The course covers the full synthesis process flow starting from reviewing methodologies, using development tools, adding constraints, implementing every VHDL structure in an optimal way, understanding the problems with bad coding style, learning the differences between simulation pre and post synthesis, analyzing critical paths, and reading and analyzing synthesis reports. In addition, the course focuses on writing efficient code to save area, increasing frequency, designing for low power consumption, dealing with skew problems, working with external IPs, using attributes in VHDL code, implementing reliable, and high speed finite state machines, solving design problems like high fanout and more. The course combines 50% theory with 50% practical work in every meeting. The practical labs cover all the theory and also include practical digital design. Course Duration 5 days Goals 1. Understand the synthesis process flow and the difference between different tools 2. Learn precise coding style for combinational and sequential circuits 3. Understand synthesis of multi files projects 4. Become familiar with the various constraints and adding them to project 5. Become familiar with design problems resulting from bad coding style 6. Design efficient circuits for minimal area or high frequency 7. Work with IPs and combining them in the synthesis flow 8. Produce reports, detect and correct timing problems
Intended Users Hardware engineers who develop FPGAs and would like to enhance their skills, in order to understand synthesis limitations, to acquire better expertise on avoiding digital problems and to be to write efficient coding style for synthesis Previous Knowledge FPGA design, VHDL Course Material 1. Simulator: Modelsim 2. Synthesizer and Place & Route: Quartus Prime 3. Course book (including labs)
Table of Contents Introduction to Synthesis Day #1 o The synthesis process Technology library Constraint HDL files Compiler Mapping Generated Netlist o Hardware inference versus hardware instantiation o Simulation versus Synthesis Concurrent Signal Assignment Synthesis o General guidelines Data types Initialization of signals Operand length o Inference from declarations Integer State machine std_logic_vector Other data types o Inference from Z value tri state buffer Bi Directional I/O tri state MUX tri state buffer bus o Inference from simple concurrent signal assignment Logical operator RTL and Technology view analysis Using synthesizer attributes Closed feedback loop problem o Inference from conditional signal assignments WHEN ELSE synthesis LUT equation analysis UNAFFECTED key word
LATCH problem Don t care in synthesis std_match function WITH SELECT synthesis o Inference from arithmetic and relational operators Integer versus REAL Arithmetic operators: +,, *, /, abs, ** Relational operators: >, <, =, /=, >=, <= Constants in arithmetic and relational operators o Simulation versus synthesis behavior and synthesis guidelines Operator Sharing o Derivation of efficient HDL description o Reducing circuit size o Operator sharing using VHDL description o Operator sharing using synthesizer GUI options o Analyzing area and frequency o Tradeoff analysis o Complex operator sharing and synthesis tools limitations Day #2 Sequential Statements Synthesis o Inference from within processes introduction o General guidelines Using variables Case versus IF ELSE Combinational sensitivity list Sequential sensitivity list o Inference from simple assignment statements Signals versus Variables synthesis o Inference from IF THEN ELSE and IF THEN ELSIF statements Priority Latch problem Full versus partial sensitivity list Combinational versus sequential If statements
Variables versus Signals synthesis Operator sharing within process Nested IF statements synthesis Analyzing results on different synthesizers o Inference from Case statements When Others statement synthesis Combinational versus sequential sensitivity list Null key word Latch problem Don t care in Case statements o Inference from loop statements Serial loop versus parallel loop synthesis Loop index FOR loop versus while and simple loop synthesis Variables versus Signals in loop synthesis o Combinational circuit design examples Gray code incrementor Programmable priority encoder Signed addition with status Combinational adder based multiplier Hamming distance circuit Day #3 Sequential Statements Synthesis (continue) o Incomplete Sensitivity List Bad versus good coding style, simulation pre and post synthesis o Inference using Variables Versus Signals variables and signals in combinational processes, variables and signals in sequential processes, when variable becomes register, analyzing synthesis warnings, debugging variables in post synthesis simulation o Synchronous Circuits Inference latch versus flip flop inference Synchronous and asynchronous reset Load and enable signals
o Inference from WAIT Statements Combinational WAIT processes Sequential WAIT processes Non synthesizable WAIT statements Variables versus signals in WAIT statements Synchronous reset in WAIT statements Finite State Machine Synthesis o State machine structure (Mealy and Moore block diagram) o State encoding (Auto, one hot, binary, Johnson, two hot, Gray, User specific) o State machine implementation in VHDL (one, two or three processes) o Bad coding style for state machine o Specifying encoding style in VHDL and in synthesizer tool o Analyzing encoding style area and performance o High reliability safe state machines using attributes, handling illegal states Day #4 Timing Analysis of a Synchronous Sequential Circuits o Introduction to timing constraints and synchronous design techniques o Synchronized versus unsynchronized I/O o Setup time violation and maximal clock rate o Synthesis static analysis formula o Hold time violation o Output related timing considerations o Input related timing considerations o Poor design practices and their remedies Misuse of asynchronous signals Misuse of gated clock Misuse of derived clocks Global clock Clock skew o Analyzing critical paths in details o Synthesis static timing analysis versus Place & Route static timing analysis
o Fanout and long combinational chain timing problems o Using PLL in the system o Physical Synthesis versus logical synthesis Day #5 Synthesis of Large Projects o Synthesis of Package & Package Body o Synthesis of functions & procedures o Reuse methodology o Synthesis of IEEE packages Integrating IP Core o IP core generation and integration into VHDL code o IP black box constraints Maximize Clock Rate o Introduction to pipeline o Latency and throughput o Pipelined combinational circuits o Pipelining considerations o Pipeline balancing o Effectiveness of pipeline o Adding a pipeline in VHDL o Analyze clock rate in pipelined design o Complex pipeline circuits o Retiming