Set No. 1 IV B.Tech I Semester Supplementary Examinations, March - 2017 COMPUTER ARCHITECTURE & ORGANIZATION (Common to Electronics & Communication Engineering and Electronics & Time: 3 hours Max. Marks: 70 PART A (22 Marks) 1. a) Convert the number (7654) 8 to hexadecimal. b) Write about Reduced Instruction Set Computer. c) Define micro program. d) Write about virtual memory. e) Define source -initiated transfer using handshaking. f) Define cache coherence. PART B (3x16 = 48 Marks) 2. a) Briefly write about r's complement and (r-1)'s complement. b) Explain any two ways of adding decimal numbers. 3. a) Discuss about stack organization of memory. Give its applications. b) Briefly write about instruction codes. 4. a) A computer has 16 registers, an ALU with 32 operations and a shifter with eight operations, all connected to a common bus i) Formulate a control word for a micro operation ii) Specify the number of bits in each field of control word and give a general encoding scheme [10] b) Differentiate hard wired control unit and micro programmed control unit. [6] 5. a) Explain Set Associative mapping for organizing cache memory. b) Consider the following reference string: 1 2 3 4 1 2 5 1 2 3 4 5, apply FIFO page replacement algorithm and calculate number of page faults by considering 3 frames. 6. a) Differentiate Isolated I/O and memory mapped I/O. b) Explain daisy chain priority interrupt. 7. a) Write in detail about inter processor communication and synchronization. b) Explain the concept of pipelining for floating - point addition and subtraction. '' '' '' ''' '
Set No. 1 IV B.Tech I Semester Regular Examinations, November - 2016 COMPUTER ARCHITECTURE & ORGANIZATION (Common to Electronics & Communication Engineering and Electronics & Time: 3 hours Max. Marks: 70 PART A (22 Marks) 1. a) Write the structure of buses used in computer system? b) List out the typical logical and bit manipulation instructions. c) Write about the fetch routine in symbolic microinstructions. d) Differentiate logical and physical address representations. e) Write about first-in and first-out buffers in asynchronous data transfer. f) What is inter- process arbitration? PART B (3x16 = 48 Marks) 2. a) Explain various number systems and number representations used in system. b) Dividend A=01110 Divisor B=10001. Explain flowchart for divide operation. 3. a) What is the purpose of addressing modes? Explain various addressing mode techniques. b) Design and explain 4-bit adder-subtractor and 4-bit arithmetic circuit to perform addition and subtraction using full adders. 4. a) Explain micro sequencer organization with a neat sketch. b) Discuss the following: Computer configuration for micro program, Symbolic micro program and binary micro program. 5. a) Explain Cache memory organization with Associative mapping? Explain how it improves the memory access time? b) What is the need for replacement? Explain various cache block replacement algorithms. 6. a) Show internal configuration of a DMA controller diagrammatically and explain how it s working. b) Explain about Prioritized Interrupts and interrupts cycle. 7. a) Write about i) No-operations ii) instruction reordering iii) annulling b) What is cache coherence problem? Explain various protocols to handle it.
Set No. 2 IV B.Tech I Semester Regular Examinations, November - 2016 COMPUTER ARCHITECTURE & ORGANIZATION (Common to Electronics & Communication Engineering and Electronics & Time: 3 hours Max. Marks: 70 PART A (22 Marks) 1. a) How to estimate the performance of software? b) What is high impedance state in bus buffer? c) Explain the format of micro instruction. d) What is segmented page mapping? e) Write about parallel priority interrupts. f) List out the typical characteristic of multiprocessors. PART B (3x16 = 48 Marks) 2. a) Perform the subtraction of Unsigned numbers using 10 s and 2 s compliment. Give at least two examples. b) Explain the process of multiplying binary integers with Booth s algorithm. 3. a) Define micro-operation and explain the four Basic types of shift micro-operation and their variants. b) Consider the arithmetic statement X= (A+B)*(C+D). Explain the influence of number of addresses on computer program. 4. a) Explain the organizations of micro programmed control unit with neat sketch. b) What is address sequencing? Explain the conditional branching and mapping of instruction in it. 5. a) Explain Cache with Set-Associative and direct mapping. Assume your own example address and explain. b) Explain how memory management unit provides memory protection. 6. a) Explain Types of Interrupts with an example for each. b) Explain with a neat diagram, system configuration incorporating an I/O processor. 7. a) Explain how to resolve branch conflicts in Instruction pipeline. b) Discuss various inter connection structures available for multiprocessor systems.
Set No. 3 IV B.Tech I Semester Regular Examinations, November - 2016 COMPUTER ARCHITECTURE & ORGANIZATION (Common to Electronics & Communication Engineering and Electronics & Time: 3 hours Max. Marks: 70 PART A (22 Marks) 1. a) What is fixed point representation? b) How to specify the internal organization of a digital computer? c) Write short notes on conditional branching. d) Define pages, blocks and page frames. e) What is data transparency? f) Define delayed load and delayed branch. PART B (3x16 = 48 Marks) 2. a) Convert the (256) 10 into following codes i) Binary Coded Decimal (BCD) ii) Excess 3 codes iii) Gray code iv) Reflected Code b) Explain addition and subtraction algorithms for data represented in signedmagnitude and signed 2 s compliment. 3. a) Explain the following with respect to stack organization i) Register stack ii) Stack Operations iii) Reverse Polish Notation [9] b) With neat sketch explain the design of control unit of basic computer. [7] 4. a) Write the format of the micro instruction and micro operations for the control memory. b) Explain the mapping from instruction code to micro instruction address. Give the first micro instruction for the 0010, 1011 and 1111. 5. a) Explain how the logical address is translated into physical address in paging. [10] b) Explain the relationship between address and memory space in virtual memory system. [6] 1 of 2
Set No. 3 6. a) Explain the following with respect to serial communication: Character oriented protocol and Bit Oriented protocol. b) What are the handshaking signals? Explain handshake control of data transfer during input and output operations. 7. Write short notes on the following a) Parallel Arbitration b) Matrix multiplication using vector processing. c) RS232 serial Interface. [5] [5] [6] 2 of 2
Set No. 4 IV B.Tech I Semester Regular Examinations, November - 2016 COMPUTER ARCHITECTURE & ORGANIZATION (Common to Electronics & Communication Engineering and Electronics & Time: 3 hours Max. Marks: 70 PART A (22 Marks) 1. a) Write about alphanumeric codes. b) What is register-reference instruction? c) What is the role of control memory in micro programmed control? d) What is content addressable memory? e) Differentiate isolated I/O and Memory mapped I/O. f) Write short notes on three segment instruction pipeline. PART B (3x16 = 48 Marks) 2. a) How to represent the signed integer numbers? Perform arithmetic addition and subtraction using 2 s compliment. In this how to handle overflow? b) Multiplicand B=10111, Multiplier A= 10011. Explain the hardware implementation and algorithm for multiply operation. 3. a) Explain the complete design of simple system to implement RTL code using direct connections, bus and tri-state buffers. b) What are the different phases a basic computer instruction cycle consists? Explain instruction cycle with flowchart. 4. a) Explain the design of control unit. How to decode the micro operation fields? Explain the process. b) Write the differences between hardwired control and micro programmed control? Is it possible to have a hardwired control associated with a control memory? 2 of 2
Set No. 4 5. a) Explain Cache with associative and two way Set- Associative mapping with a line size of 4 bytes. [10] b) What are the techniques used to write Data into the Cache? [6] 6. a) Explain different types of I/O communication techniques with merits and demerits. b) What is the need for I/O Processor? Explain the working style of I/O processor. 7. a) Explain different physical forms available to establish inter-connection between various functional units in multiprocessor systems. b) With neat sketch explain Time Shared Common Bus Organization and also discuss its merits and demerits. 2 of 2
Set No. 1 IV B.Tech I Semester Regular/Supplementary Examinations, October/November - 2017 COMPUTER ARCHITECTURE AND ORGANIZATION (Common to Electronics and Communication Engineering and Electronics and Time: 3 hours Max. Marks: 70 PART A(22 Marks) 1. a) b) c) d) e) f) Describe about memory unit. Discuss various types of Interrupts. Define Microinstruction. What do you mean by content addressable memory? What is the difference between isolated I/O and memory mapped I/O? What are the advantages and disadvantages of each? What do you mean by delayed load? [5] [2] PART B(3x16 = 48 Marks) 2. a) Distinguish between fixed point representation and floating point representation. b) Represent the number (+46.5)10 as a floating-point binary number with 24 bits. The normalized fraction mantissa has 16 bits and the exponent has 8 bits. 3. a) What are the basic differences among a branch instruction, a call subroutine instruction, and program interrupt? b) Construct a bidirectional shift register with parallel load and give the function table of the circuit. 4. a) Give an overview of address sequencing in microprogrammed control unit. b) Formulate a mapping procedure that provides eight consecutive microinstructions for each routing. The operation code has six bits and the control memory has 2048 words. 5. a) Explain the functionalities of memory management hardware. b) Explain various mapping procedures of cache memory with an example. 6. a) Demonstrate how communication proceeds between CPU and IOP. b) Explain in detail various I/O modes of transfer. 7. a) Illustrate arithmetic pipeline with an example. b) Derive speedup achieved by a pipeline unit over a non-pipeline unit. '' ' '' ''' '
Set No. 2 IV B.Tech I Semester Regular/Supplementary Examinations, October/November - 2017 COMPUTER ARCHITECTURE AND ORGANIZATION (Common to Electronics and Communication Engineering and Electronics and Time: 3 hours Max. Marks: 70 PART A(22 Marks) 1. a) b) c) d) e) f) Describe about Arithmetic Logic Unit. Describe the basic Instruction format. Define Micro-operation. What is the purpose of cache memory? Define cycle stealing. Write about Pipeline conflicts. PART B(3x16 = 48 Marks) 2. a) Demonstrate the procedure for obtaining product-of-sums using k-maps. b) Define (r 1) s complement and r s complement. 3. a) Give the major characteristics of RISC and CISC architectures. b) What are addressing modes? Give an overview of the addressing modes. 4. a) Distinguish between microprogrammed and hardwired control unit. b) What are the microinstructions needed for the fetch routine? Explain. 5. a) A computer employs RAM chips of 256 8 and ROM chips of size 1024 8. Extend the memory system to 4096 bytes of RAM and 4096 bytes of RAM. List the memory address map and indicate what size decoders are needed. b) Demonstrate with an example address mapping using pages. 6. a) Design parallel priority interrupt hardware for a system with eight interrupt sources. b) What is direct memory transfer? Give an overview and the block diagram of a DMA controller. 7. a) Illustrate with an example hardware implementation of division algorithm. b) What are the pipeline conflicts that cause the instruction pipeline to deviate from its normal operation? '' ' '' ''' '
Set No. 3 IV B.Tech I Semester Regular/Supplementary Examinations, October/November - 2017 COMPUTER ARCHITECTURE AND ORGANIZATION (Common to Electronics and Communication Engineering and Electronics and Time: 3 hours Max. Marks: 70 PART A(22 Marks) 1. a) Describe about control unit. b) Describe the phases of instruction cycle briefly. [5] c) Define microprogram. d) What do you mean by bootstrap loader? e) What do you mean by vectored interrupt? f) Write about delayed branch. PART B(3x16 = 48 Marks) 2. a) Describe fixed point representation and floating point representation. b) Give an overview of the basic functional units and bus structures of a computer. 3. a) An 8-bit register contains the binary value 10011100. What is the register value after arithmetic shift right? Starting from the initial number 10011100, determine the register value after an arithmetic shift left, and state whether there is an overflow b) Give few examples of external interrupts and few examples of internal interrupts. What is the difference between a software interrupt and subroutine call. 4. a) What are main types of control units? Explain briefly. b) Give the block diagram of a control memory and the associated hardware needed for selecting the next micro-instruction address. 5. a) Suppose that the processor has access to two levels of memory. Level 1 contains 1000 words and has an access time of 0.01 µs; level 2 contains 1,00,000 words and has an access time of 0.1µs. Assume that if a word to be accessed is in level 1, then the processor accesses it directly. If it is in level 2, then the word is first transferred to level 1 and then accessed by the processor. Suppose, we ignore the time required to determine whether the word is in level 1 or level 2 and 95% of the memory accesses are found in the cache, then what is the average access time of a word. b) What is cache memory? What are its advantages? Explain. 6. a) Demonstrate interrupt-initiated I/O. b) Explain the functionalities of an IOP interface unit. 7. a) Illustrate with an example an instruction pipeline. b) Illustrate with an example Booth multiplication algorithm. '' ' '' ''' '
Set No. 4 IV B.Tech I Semester Regular/Supplementary Examinations, October/November - 2017 COMPUTER ARCHITECTURE AND ORGANIZATION (Common to Electronics and Communication Engineering and Electronics and Time: 3 hours Max. Marks: 70 PART A(22 Marks) 1. a) Distinguish among computer organization and computer architecture. b) What do you mean by register transfer language? What are the uses of register transfer language? c) Define Microcode. d) What do you mean by associative memory? Give applications of associative memory. e) What do you mean by multiprogramming? f) Describe about MIMD. [5] PART B(3x16 = 48 Marks) 2. a) Illustrate with examples fixed point representation and floating point representation. b) Give an overview of the performance measurement of computers. 3. a) Using a 4-bit counter with parallel load and a 4-bit adder, draw a block diagram that shows how to implement the following statements: x: R1 R1+R2 Add R2 to R1 x'y: R1 R1+1 Increment R1 where R1 is a counter with parallel load and R2 is a 4-bit register b) Explain the functionalities and applications of the following: i. Decoders ii. Encoders iii. Multiplexers iv. De-multiplexers 4. a) What is the difference between a microprocessor and microprogram? Is it possible to design a microprocessor? b) Explain how address sequencing is done in a microprogrammed control unit. 5. a) Demonstrate logical to physical address mapping using segmented-paging. b) What is virtual memory? Explain. 6. a) Give an overview of parallel priority interrupt hardware. b) Demonstrate the mechanism of DMA. 7. a) Illustrate with an example an arithmetic pipeline. b) Give the flowchart of addition and subtraction of two floating-point binary numbers. '' ' '' ''' '