SRM ARTS AND SCIENCE COLLEGE SRM NAGAR, KATTANKULATHUR 603203 DEPARTMENT OF COMPUTER SCIENCE & APPLICATIONS LESSON PLAN (207-208) Course / Branch : M.Sc CST Total Hours : 50 Subject Name : Computer Architecture Subject Code : CTC6C Faculty Name : K. Priya lakshmi Designation : Asst.Pressor Semester / Year : EVEN / III : 50 PPT Hours : Minimum Hour per Aim: To study about the nature, structure and functions contemporary computer system. Objectives: To explore the competence changeover the computer system over different generations. To study about system architecture like bus structure and PCI etc. Giving an overview about types memory and their hierarchy. To explain about secondary storage backup technique like RAID In-depth analysis core concepts like instruction fetch and execute, instruction cycle etc. To study about Instruction Pipelining, RISC etc. Text Book(s):. M.M.Mano - Computer System Architecture, 3 rd Edition- PHI, 994. 2. J.P.Hayes Computer System Architecture McGrawHill - 988
-I: Central Processing : General Register and Stack Organization Instruction Formats Addressing Modes Data Transfer and Manipulation Program Control RISC. I General Register Organization i) Control Word ii) Examples Microprocessors T 242-246 2 I Stack Organization i) Register Stack ii) Memory Stack iii) Reverse Polish Notation T 247-254 3 I Instruction Formats i) Three Address Instructions ii) Two Address Instructions T 253-258 4 I Instruction Formats iii) One Address Instructions iv) Zero Address Instructions v) RISC Instructions T 259-260 5 I Addressing Modes T 260-264 6 I Data Transfer & Manipulation i) Data Transfer Instructions ii) DataManipulation iii) Arithmetic Instructions iv) Logical & Bit Instructions v) Shift Instructions T 266-272 7 I 8 I Program Control i) Status Bit Conditions ii) Conditional Branch iii) Subroutine Call & Return Program Control iv) Program Interrupt v) Types Interrupts T 273-278 T 279-28 9 I RISC i) CISC Characteristics ii) RISC Characteristics 0 I Test T 282-285 2
-II: Pipelining Arithmetic, Instruction and RISC Pipelining Vector Processing Array Processors II Parallel Processing T 299-302 2 II Pipelining i) General Considerations T 302-307 3 II Arithmetic Pipeline T 307-30 4 II Instruction Pipeline i) Four Segment Instruction T 30-32 5 II Instruction Pipeline ii) Data Dependency iii) Handling Branch T 33-35 6 II RISC Pipeline i) Three Segment Instruction ii) Delayed Load iii) Delayed Branch T 35-38 7 II Vector Processing i) Vector Operations ii) Matrix Multiplication T 39-32 8 II Vector Processing iii) Memory Interleaving iv) Supercomputers T 324-326 9 II Array Processors i) Attached Array Processor T 326-329 20 II Test 3
-III: Computer Arithmetic Addition and Subtraction Multiplication and Division Algorithms Floating Point and Decimal Arithmetic Operations Addition and Subtraction 2 III 22 III 23 III 24 III 25 III 26 III 27 III 28 III 29 III i) With Signed-Magnitude ii) Hardware Implementation Addition and Subtraction iii) Hardware Algorithm iv) Signed-2 s Complement data Multiplication Algorithm i) Hardware Implementation ii) Hardware Algorithm Multiplication Algorithm iii) Booth Multiplication Alg. iv) Array Multiplier Division Algorithm i) Hardware Implementation ii) Hardware Algorithm iii) Divide Overflow Floating Point Arithmetic Operations i) Basic Considerations ii) Register Configuration iii) Addition & Subtraction Floating Point Arithmetic Operations iv) Multiplication v) Division Decimal Arithmetic Operations i) Addition & Subtraction ii) Multiplication Decimal Arithmetic Operations iii) Division iv) Floating Point Operations 30 III Test T 333-336 T 337-339 T 340-342 T 343-347 T 348-353 T 354-358 T 360-362 T 369-373 T 374-376 4
-IV: Input Output Organization Peripheral devices I/O Interface Asynchronous Data Transfer Modes Transfer Priority Interrupt - Direct Memory Access I/O Processor Serial Communication 3 IV Peripheral Devices T 38-384 32 IV 33 IV 34 IV 35 IV 36 IV 37 IV 38 IV 39 IV Input-Output Interface i) I/O Bus & Interface Modules ii) I/O versus Memory Bus iii) Isolated versus Memory- Mapped I/O Asynchronous Data Transfer i) Strobe Control ii) Handshaking iii) Asynchronous Serial Transfer iv)asynchronous Communication Interface Modes Transfer i) Example Programmed I/O ii) Interrupt-Initiated I/O iii) Stware Considerations Priority Interrupt i) Daisy-Chaining Priority ii) Parallel Priority Interrupt iii) Priority Encoder Priority Interrupt iv) Interrupt Cycle v) Stware Routines vi) Intial and Final Operations Direct Memory Access i) DMA Controller ii) DMA Transfer Input-Output Processor i) CPU-IOP Communication ii) IBM 370 I/O Channel Serial Communication i) Character-Oriented Protocol ii) Transmission Example iii) Data Transparency iv) Bit-Oriented Protocol 40 IV Test T 385-390 T 39-400 T 402-406 T 407-4 T 42-45 T 45-49 T 420-428 T 429-439 5
-V: Memory Organization Memory Hierarchy Main Memory Auxiliary Memory Associative Cache and Virtual Memory Interconnection Structures Interprocessor Arbitration. i)memory Organization 4 V ii)memory Hierarchy T 445-452 a)ram & ROM Chips 42 V 43 V 44 V 45 V 46 V 47 V 48 V 49 V b)memory Address Map Auxiliary Memory i) Magnetic Disk ii) Magnetic Tape Associative Memory i) Hardware Operations ii) Match Logic iii) Read Operation iv) Write Operation Cache Memory i) Associative Mapping ii) Direct Mapping iii) Set-Associative Mapping iv) Writing into Cache v) Cache Initialization Virtual Memory i) Address Space & Memory Space ii) Address Mapping Using Pages Virtual Memory iii) Associative Memory Page iv) Page Replacement Interconnection Structure i) Time-shared Common Bus ii) Multiport Memory iii) Crossbar Switch Interconnection Structure iv) Multistage Switching Network v) Hypercube Interconnection Interprocessor Arbitration i) System Bus ii) Serial Arbitration Procedure iii) Parallel Arbitration Logic 50 V Test T 452-455 T 456-46 T 462-469 T 469-473 T 473-476 T 489-494 T 496-500 T 500-505 * T Text Book / R Book 6