NAME: 1a. (10 pts.) Describe the characteristics of numbers for which this floating-point data type is well-suited. Give an example.

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MSU CSC 285 Spring, 2007 Exam 2 (5 pgs.) NAME: 1. Suppose that a eight-bit floating-point data type is defined with the eight bits divided into fields as follows, where the bits are numbered with zero at the right-hand side. A one-bit sign field, in bit 7 A five-bit exponent field, in bits 6..2 A two-bit significand field, in bits 1..0 In addition to the fields explicitly described above, there is a hidden bit to the significand, similar to IEEE 754. 1a. (10 pts.) Describe the characteristics of numbers for which this floating-point data type is well-suited. Give an example. 1b. (10 pts.) Compare this floating-point data type to the IEEE 754 32-bit floating-point data type. Which can represent more values between two consecutive powers of two? Explain your answer, three sentences maximum. Page 1

2. Suppose you design a computer in which numbers are represented using a numerator and a denominator in two fields of a 32-bit word. Each field contains a two s complement number. The numerator field is 12 bits and the denominator field is 20 bits. For example, 3.5 = 7 / 2, which would be represented by 12-bit numerator field 20-bit denominator field 000000000111 00000000000000000010 2a. (5 pts.) Give an example of a number that cannot be perfectly represented by this scheme. 2b. (5 pts.) What is the largest positive number that can be represented by this scheme? You may express this number as a formula. 2c. (15 pts.) Assume that registers $s0 and $s1 contain numbers in this form, and that the denominators of the two numbers are equal. Write MIPS code to add the two numbers, placing the result into register $s3. Assume that overflow does not occur during the computation. Assume that the fraction in your result does not need to be in lowest terms (that s a weakness in this scheme). Page 2

3. Consider the algorithm and hardware for floating-point addition. A portion of the existing addition hardware is shown on the next page, which is Fig. 3.17, p. 201. If you have any question about where the location of the colored datalines on the figure, please see instructor. 3a. (5 pts.) What is the width of the blue data line? (Number of bits on the line) 3b. (5 pts.) Suppose the control line to the multiplexer prior to the pink data line is malfunctioning so that its value is unpredictable (either zero or one). Under what circumstances will the circuit operate correctly? 3c. (10 pts.) What is the meaning of the blue data line? (Interpretation of bits on the line) 3d. (10 pts.) Suppose your computer will always and only be used to add floating-point numbers with equal exponents. Circle and highlight the circuit component (components) that could be removed to simplify the circuit in that situation. Consider only the portion of the circuit shown on this exam. Page 3

Portion of Fig. 3.17, p. 201. ALU for Floating point addition Pink Blue 4. (10 pts.) Suppose the following decimal values are to be put into IEEE 754 32-bit floating point form (see p. 277). Show the normalized binary form of the value with true exponent, which means 1.significand multiplied by the non-biased power of two, such as 1.0100111 * 2 4. 32768 = 2 15 = 67/8 = 5/32 = Page 4

5. (20 pts.) Computer1 and Computer2 have the characteristics below for the same benchmark program. Computer1 and Computer2 have the same clock rate. Instruction Type Cycles on Computer 1 Cycles on Computer 2 Percentage of this instruction type in the benchmark program (%, total is 100) Arithmetic and Logical 4 3 25 Load and Store 2 3 10 Branches 2 1 25 Floating point 3 5 40 5a. (10 pts.) Which program will complete in less time? Show your work. 5b. (10 pts.) What two other items of information are needed to find out how long the two computers actually take (start to finish) to run the program? Hint: clock. EXTRA CREDIT. (10 pts., not to exceed perfect score) A common operation in MIPS is to convert an address from units of words to units of bytes. Show two ways of doing that in MIPS code, neither of which is the mult instruction. Page 5