ECE 313 Computer Organization FINAL EXAM December 13, 2000

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1 This exam is open book and open notes. You have until 11:00AM. Credit for problems requiring calculation will be given only if you show your work. 1. Floating Point Representation / MIPS Assembly Language 20 Points (a) Write a sequence of MIPS assembly language instructions that uses integer instructions to compare two positive IEEE floating-point numbers stored in registers $s1 and $2. If $s1 < $s2, your program should set register $s3=1, otherwise it should set $s3=0. Do not use floating point instructions. (b) Explain how you would extend your code to handle the case where the signs of the two floating point numbers are not known ahead of time. You do not need to write code just describe an approach. 2. Arithmetic & Logic 10 Points In the space provided below, show the logic necessary to test whether a 32-bit two s complement integer is greater than or equal to zero. Page 1 of 6

2 3. Multi-Cycle Processor Design 20 Points Modify the multi-cycle processor datapath and control to implement the bgez (branch if greater than or equal) instruction. The register transfer description for this instruction is as follows: if (Reg[rs] 0) PC = PC (extnd(imm) << 2); else PC = PC + 4; Mark the necessary changes to the datapath and control on the diagrams shown below. How many clock cycles will this instruction take to execute? (Book Fig. 5.33, p. 383) Page 2 of 6

3 (See Book Figure 5.33, p. 383) Page 3 of 6

4 Multicycle Design State Diagram 4. Pipelined Processor Design 20 Points Modify the pipelined processor datapath and control to implement the bgez (branch if greater than or equal to zero) instruction described in the previous problem. Mark the necessary changes to the datapath and control on the diagrams shown below. You may find it helpful to review the control table in Fig on p. 469 of the text. (Book Fig. 6.30, p. 470) Instr. Bgez Reg Dst EX Stage Control Lines ALU Op0 ALU Op1 ALU Src Branch MEM Stage Control Lines Mem Mem Read Write WB Stage Control Lines Reg Memto Write Reg Page 4 of 6

5 5. Pipelined Design Forwarding and Stalls 20 Points Consider the following sequence of MIPS instructions and assume that we are using the pipelined design with forwarding shown in Fig of the book (p. 484). add $1, $2, $3 lw $4, 1000($1) sub $5, $4, $6 (a) Circle any data dependencies which exist in these instructions for the given pipeline. (b) Fill in the multi-cycle pipeline diagram below to show how the given instructions flow through the pipeline. You should label each instruction, shade the ALU, register, and memory blocks to show which parts of each stage are active during each cycle, show connections for any forwarding that is needed, and clearly mark stalled instructions. (c) Assuming that the pipeline is initially empty, how many clock cycles does it take for this sequence of instructions to execute? CC 1 CC 2 CC 3 CC 4 CC 5 CC 6 CC 7 CC 8 CC 9 CC 10 CC 11 Page 5 of 6

6 6. Memory Systems Short Answers 10 Points A processor with a cache performs a memory read and a cache miss occurs. A list of possible consequences of the cache miss are shown below. For each item in the list, circle the word (always, sometimes, never) which most accurately describes whether the consequence occurs. (a) The processor pipeline stalls always sometimes never (b) A new block is read from memory into the cache always sometimes never (c) An existing block in the cache is replaced always sometimes never (d) An existing cache block is written to memory always sometimes never (e) The program is suspended by the OS always sometimes never Page 6 of 6

ECE 313 Computer Organization FINAL EXAM December 14, This exam is open book and open notes. You have 2 hours.

ECE 313 Computer Organization FINAL EXAM December 14, This exam is open book and open notes. You have 2 hours. This exam is open book and open notes. You have 2 hours. Problems 1-5 refer to the following: We wish to add a new R-Format instruction to the MIPS Instruction Set Architecture called l_inc (load and increment).