CISC 36 Topics Cache Memories Nov 25, 28 Generic cache memory organization Direct mapped caches Set associative caches Impact of caches on performance
Cache Memories Cache memories are small, fast SRAM-based memories managed automatically in hardware. Hold frequently accessed blocks of main memory CPU looks first for data in L, then in L2, then in main memory. Typical bus structure: CPU chip register file L ALU cache cache bus system bus memory bus L2 cache bus interface I/O bridge main memory 2 CISC 36, Fa8
Inserting an L Cache Between the CPU and Main Memory The transfer unit between the CPU register file and the cache is a 4-byte block. line line The transfer unit between the cache and main memory is a 4-word block (6 bytes). block block 2 block 3 a b c d... p q r s... w x y z... The tiny, very fast CPU register file has room for four 4-byte words. The small fast L cache has room for two 4-word blocks. The big slow main memory has room for many 4-word blocks. 3 CISC 36, Fa8
General Org of a Cache Memory Cache is an array of sets. valid bit per line t bits per line B = 2 b bytes per cache block Each set contains one or more lines. set : valid valid B B E lines per set Each line holds a block of data. valid B S = 2 s sets set : valid B valid B set S-: valid B Cache size: C = B x E x S data bytes 4 CISC 36, Fa8
Addressing Caches Address A: t bits s bits b bits set : v v B B m- <> <set index> <block offset> set : set S-: v v v v B B B B The word at address A is in the cache if the bits in one of the <valid> lines in set <set index> match <>. The word contents begin at offset <block offset> bytes from the beginning of the block. 5 CISC 36, Fa8
Direct-Mapped Cache Simplest kind of cache Characterized by exactly one line per set. set : valid cache block E= lines per set set : valid cache block set S-: valid cache block 6 CISC 36, Fa8
Accessing Direct-Mapped Caches Set selection Use the set index bits to determine the set of interest. set : valid cache block selected set set : valid cache block m- t bits s bits b bits set index block offset set S-: valid cache block 7 CISC 36, Fa8
Accessing Direct-Mapped Caches Line matching and word selection Line matching: Find a valid line in the selected set with a matching Word selection: Then extract the word =? () The valid bit must be set selected set (i): 2 3 4 5 6 7 w w w 2 w 3 (2) The bits in the cache line must match the bits in the address m- =? t bits s bits b bits i set index block offset (3) If () and (2), then cache hit, and block offset selects starting byte. 8 CISC 36, Fa8
Direct-Mapped Cache Simulation t= s=2 b= x xx x M=6 byte addresses, B=2 bytes/block, S=4 sets, E= entry/set Address trace (reads): [ 2 ], [ 2 ], 3 [ 2 ], 8 [ 2 ], [ 2 ] () [ 2 ] (miss) v data m[] M[-] m[] (3) 3 [ 2 ] (miss) v data m[] M[-] m[] M[2-3] m[3] m[2] (4) 8 [ 2 ] (miss) v data m[9] M[8-9] m[8] M[2-3] [ 2 ] (miss) v data m[] M[-] m[] m[3] m[2] 9 CISC 36, Fa8 (5) M[2-3]
Why Use Middle Bits as Index? 4-line Cache High-Order Bit Indexing Adjacent memory lines would map to same cache entry Poor use of spatial locality Middle-Order Bit Indexing Consecutive memory lines map to different cache lines Can hold C-byte region of address space in cache at one time High-Order Bit Indexing Middle-Order Bit Indexing CISC 36, Fa8
Set Associative Caches Characterized by more than one line per set set : valid cache block valid cache block E=2 lines per set set : set S-: valid cache block valid cache block valid cache block valid cache block CISC 36, Fa8
Accessing Set Associative Caches Set selection identical to direct-mapped cache set : valid valid cache block cache block Selected set set : valid valid cache block cache block m- t bits s bits b bits set index block offset set S-: valid valid cache block cache block 2 CISC 36, Fa8
Accessing Set Associative Caches Line matching and word selection must compare the in each valid line in the selected set. =? () The valid bit must be set. 2 3 4 5 6 7 selected set (i): w w w 2 w 3 (2) The bits in one of the cache lines must match the bits in the address m- =? t bits s bits b bits i set index block offset (3) If () and (2), then cache hit, and block offset selects starting byte. 3 CISC 36, Fa8
Multi-Level Caches Options: separate data and instruction caches,, or a unified cache Processor Regs L d-cache L i-cache Unified L2 Cache Memory disk size: speed: $/Mbyte: line size: 2 B 3 ns 8-64 KB 3 ns 8 B 32 B larger, slower, cheaper -4MB SRAM 6 ns $/MB 32 B 28 MB DRAM 6 ns $.5/MB 8 KB 3 GB 8 ms $.5/MB 4 CISC 36, Fa8
Intel Pentium Cache Hierarchy Regs. L Data cycle latency 6 KB 4-way assoc Write-through 32B lines L Instruction 6 KB, 4-way 32B lines L2 Unified 28KB--2 MB 4-way assoc Write-back Write allocate 32B lines Main Memory Up to 4GB Processor Chip 5 CISC 36, Fa8
Cache Performance Metrics Miss Rate Fraction of memory references not found in cache (misses/references) Typical numbers: 3-% for L can be quite small (e.g., < %) for L2, depending on size, etc. Hit Time Time to deliver a line in the cache to the processor (includes time to determine whether the line is in the cache) Typical numbers: clock cycle for L 3-8 clock cycles for L2 Miss Penalty Additional time required because of a miss Typically 25- cycles for main memory 6 CISC 36, Fa8
Writing Cache Friendly Code Repeated references to variables are good (temporal locality) Stride- reference patterns are good (spatial locality) Examples: cold cache, 4-byte words, 4-word cache blocks int sumarrayrows(int a[m][n]) { int i, j, sum = ; int sumarraycols(int a[m][n]) { int i, j, sum = ; for (i = ; i < M; i++) for (j = ; j < N; j++) sum += a[i][j]; return sum; for (j = ; j < N; j++) for (i = ; i < M; i++) sum += a[i][j]; return sum; Miss rate = /4 = 25% Miss rate = % 7 CISC 36, Fa8
The Memory Mountain Read throughput (read bandwidth) Number of bytes read from memory per second (MB/s) Memory mountain Measured read throughput as a function of spatial and temporal locality. Compact way to characterize memory system performance. 8 CISC 36, Fa8
Memory Mountain Test Function /* The test function */ void test(int elems, int stride) { int i, result = ; volatile int sink; for (i = ; i < elems; i += stride) result += data[i]; sink = result; /* So compiler doesn't optimize away the loop */ /* Run test(elems, stride) and return read throughput (MB/s) */ double run(int size, int stride, double Mhz) { double cycles; int elems = size / sizeof(int); test(elems, stride); /* warm up the cache */ cycles = fcyc2(test, elems, stride, ); /* call test(elems,stride) */ return (size / stride) / (cycles / Mhz); /* convert cycles to MB/s */ 9 CISC 36, Fa8
Memory Mountain Main Routine /* mountain.c - Generate the memory mountain. */ #define MINBYTES ( << ) /* Working set size ranges from KB */ #define MAXBYTES ( << 23) /*... up to 8 MB */ #define MAXSTRIDE 6 /* Strides range from to 6 */ #define MAXELEMS MAXBYTES/sizeof(int) int data[maxelems]; /* The array we'll be traversing */ int main() { int size; /* Working set size (in bytes) */ int stride; /* Stride (in array elements) */ double Mhz; /* Clock frequency */ init_data(data, MAXELEMS); /* Initialize each element in data to */ Mhz = mhz(); /* Estimate the clock frequency */ for (size = MAXBYTES; size >= MINBYTES; size >>= ) { for (stride = ; stride <= MAXSTRIDE; stride++) printf("%.f\t", run(size, stride, Mhz)); printf("\n"); exit(); 2 CISC 36, Fa8
The Memory Mountain read throughput (MB/s) Slopes of Spatial Locality 2 8 6 4 2 xe L2 L Pentium III Xeon 55 MHz 6 KB on-chip L d-cache 6 KB on-chip L i-cache 52 KB off-chip unified L2 cache Ridges of Temporal Locality s s3 s5 s7 stride (words) mem s9 s s3 s5 2 CISC 36, Fa8 8m 2m 52k 28k 32k 8k 2k working set size (bytes)
Ridges of Temporal Locality Slice through the memory mountain with stride= illuminates read throughputs of different caches and memory 2 main memory region L2 cache region L cache region read througput (MB/s) 8 6 4 2 8m 4m 2m 24k 52k 256k 28k 64k 32k 6k 8k 4k 2k k 22 working set size (bytes) CISC 36, Fa8
A Slope of Spatial Locality Slice through memory mountain with size=256kb shows cache block size. 8 7 6 read throughput (MB/s) 5 4 3 2 one access per cache line s s2 s3 s4 s5 s6 s7 s8 s9 s s s2 s3 s4 s5 s6 stride (words) 23 CISC 36, Fa8
Matrix Multiplication Example Major Cache Effects to Consider Total cache size Exploit temporal locality and keep the working set small (e.g., by using blocking) /* ijk */ Variable sum Block size for (i=; i<n; i++) { held in register Exploit spatial locality for (j=; j<n; j++) { sum =.; for (k=; k<n; k++) sum += a[i][k] * b[k][j]; Multiply N x N matrices c[i][j] = sum; Description: O(N3) total operations Accesses N reads per source element N values summed per destination» but may be able to hold in register 24 CISC 36, Fa8
Miss Rate Analysis for Matrix Multiply Assume: Line size = 32B (big enough for 4 64-bit words) Matrix dimension (N) is very large Approximate /N as. Cache is not even big enough to hold multiple rows Analysis Method: Look at access pattern of inner loop k j j i k i A B C 25 CISC 36, Fa8
Layout of C Arrays in Memory (review) C arrays allocated in row-major order each row in contiguous memory locations Stepping through columns in one row: for (i = ; i < N; i++) sum += a[][i]; accesses successive elements if block size (B) > 4 bytes, exploit spatial locality compulsory miss rate = 4 bytes / B Stepping through rows in one column: for (i = ; i < n; i++) sum += a[i][]; accesses distant elements no spatial locality! compulsory miss rate = (i.e. %) 26 CISC 36, Fa8
Matrix Multiplication (ijk) /* ijk */ for (i=; i<n; i++) { for (j=; j<n; j++) { sum =.; for (k=; k<n; k++) sum += a[i][k] * b[k][j]; c[i][j] = sum; Inner loop: (i,*) (*,j) (i,j) A B C Row-wise Columnwise Fixed Misses per Inner Loop Iteration: A B C.25.. 27 CISC 36, Fa8
Matrix Multiplication (jik) /* jik */ for (j=; j<n; j++) { for (i=; i<n; i++) { sum =.; for (k=; k<n; k++) sum += a[i][k] * b[k][j]; c[i][j] = sum Misses per Inner Loop Iteration: A B C.25.. Inner loop: (i,*) (*,j) (i,j) A B C Row-wise Columnwise Fixed 28 CISC 36, Fa8
Matrix Multiplication (kij) /* kij */ for (k=; k<n; k++) { for (i=; i<n; i++) { r = a[i][k]; for (j=; j<n; j++) c[i][j] += r * b[k][j]; Inner loop: (i,k) (k,*) (i,*) A B C Fixed Row-wise Row-wise Misses per Inner Loop Iteration: A B C..25.25 29 CISC 36, Fa8
Matrix Multiplication (ikj) /* ikj */ for (i=; i<n; i++) { for (k=; k<n; k++) { r = a[i][k]; for (j=; j<n; j++) c[i][j] += r * b[k][j]; Inner loop: (i,k) (k,*) (i,*) A B C Fixed Row-wise Row-wise Misses per Inner Loop Iteration: A B C..25.25 3 CISC 36, Fa8
Matrix Multiplication (jki) /* jki */ for (j=; j<n; j++) { for (k=; k<n; k++) { r = b[k][j]; for (i=; i<n; i++) c[i][j] += a[i][k] * r; Inner loop: (*,k) (*,j) (k,j) A B C Misses per Inner Loop Iteration: A B C... Column - wise Fixed Columnwise 3 CISC 36, Fa8
Matrix Multiplication (kji) /* kji */ for (k=; k<n; k++) { for (j=; j<n; j++) { r = b[k][j]; for (i=; i<n; i++) c[i][j] += a[i][k] * r; Misses per Inner Loop Iteration: A B C... Inner loop: (*,k) (k,j) (*,j) A B C Fixed Columnwise Columnwise 32 CISC 36, Fa8
Summary of Matrix Multiplication ijk (& jik): 2 loads, stores misses/iter =.25 kij (& ikj): 2 loads, store misses/iter =.5 jki (& kji): 2 loads, store misses/iter = 2. for (i=; i<n; i++) { for (j=; j<n; j++) { sum =.; for (k=; k<n; k++) sum += a[i][k] * b[k][j]; c[i][j] = sum; for (k=; k<n; k++) { for (i=; i<n; i++) { r = a[i][k]; for (j=; j<n; j++) c[i][j] += r * b[k][j]; for (j=; j<n; j++) { for (k=; k<n; k++) { r = b[k][j]; for (i=; i<n; i++) c[i][j] += a[i][k] * r; 33 CISC 36, Fa8
Pentium Matrix Multiply Performance Miss rates are helpful but not perfect predictors. Code scheduling matters, too. 6 5 Cycles/iteration 4 3 2 kji jki kij ikj jik ijk 25 5 75 25 5 75 2 225 25 275 3 325 35 375 4 34 CISC 36, Fa8 Array size (n)
Improving Temporal Locality by Blocking Example: Blocked matrix multiplication block (in this context) does not mean cache block. Instead, it mean a sub-block within the matrix. Example: N = 8; sub-block size = 4 A A 2 A 2 A 22 X B B 2 B 2 B 22 = C C 2 C 2 C 22 Key idea: Sub-blocks (i.e., A xy ) can be treated just like scalars. C = A B + A 2 B 2 C 2 = A B 2 + A 2 B 22 C 2 = A 2 B + A 22 B 2 C 22 = A 2 B 2 + A 22 B 22 35 CISC 36, Fa8
Blocked Matrix Multiply (bijk) for (jj=; jj<n; jj+=bsize) { for (i=; i<n; i++) for (j=jj; j < min(jj+bsize,n); j++) c[i][j] =.; for (kk=; kk<n; kk+=bsize) { for (i=; i<n; i++) { for (j=jj; j < min(jj+bsize,n); j++) { sum =. for (k=kk; k < min(kk+bsize,n); k++) { sum += a[i][k] * b[k][j]; c[i][j] += sum; 36 CISC 36, Fa8
Blocked Matrix Multiply Analysis Innermost loop pair multiplies a X bsize sliver of A by a bsize X bsize block of B and accumulates into X bsize sliver of C Loop over i steps through n row slivers of A & C, using same B for (i=; i<n; i++) { for (j=jj; j < min(jj+bsize,n); j++) { sum =. for (k=kk; k < min(kk+bsize,n); k++) { sum += a[i][k] * b[k][j]; Innermost c[i][j] += sum; Loop Pair kk jj jj i kk i row sliver accessed bsize times A B C block reused n times in succession Update successive elements of sliver 37 CISC 36, Fa8
Pentium Blocked Matrix Multiply Performance Blocking (bijk( and bikj) ) improves performance by a factor of two over unblocked versions (ijk( and jik) relatively insensitive to array size. 6 Cycles/iteration 5 4 3 2 25 5 75 25 5 75 2 225 25 275 3 325 35 375 4 38 CISC 36, Fa8 Array size (n) kji jki kij ikj jik ijk bijk (bsize = 25) bikj (bsize = 25)
Concluding Observations Programmer can optimize for cache performance How data structures are organized How data are accessed Nested loop structure Blocking is a general technique All systems favor cache friendly code Getting absolute optimum performance is very platform specific Cache sizes, line sizes, associativities, etc. Can get most of the advane with generic code Keep working set reasonably small (temporal locality) Use small strides (spatial locality) 39 CISC 36, Fa8