IMPORTANT NOTICE. As a result, the following changes are applicable to the attached document.

IMPORTANT NOTICE Dear customer, As from August 2 nd 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless. As a result, the following changes are applicable to the attached document. Company name - NXP B.V. is replaced with ST-NXP Wireless. Copyright - the copyright notice at the bottom of each page NXP B.V. 200x. All rights reserved, shall now read: ST-NXP Wireless 200x - All rights reserved. Web site - http://www.nxp.com is replaced with http://www.stnwireless.com Contact information - the list of sales offices previously obtained by sending an email to salesaddresses@nxp.com, is now found at http://www.stnwireless.com under Contacts. If you have any questions related to the document, please contact our nearest sales office. Thank you for your cooperation and understanding. ST-NXP Wireless www.stnwireless.com

Rev. 04 21 December 2006 Application note Document information Info Keywords Abstract Content isp1582; isp1583; peripheral controller; usb; universal serial bus This document explains the firmware programming of the ISP1582/83.

Revision history Rev Date Description 04 20061221 Fourth release. Table 1: added table note. Section 2.3: updated the text before the code. Section 2.5: added a remark. Added Section 2.6 and Section 2.7. Section 3: added remarks. Updated Fig 7, Fig 8, Fig 9 and Fig 10. Added Section 4. Added Fig 11 and Fig 12. 03 20060907 Third release: Updated Fig 3. Section 2.6: updated the last paragraph. Section 3: updated the last two paragraphs. Updated Table 7. 02 20050103 Second release: updated Section 2.6. 01 20040603 First release. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com _4 Application note Rev. 04 21 December 2006 2 of 49

1. Introduction The ISP1582/83 is a Hi-Speed Universal Serial Bus (USB) Peripheral Controller that provides a flexible interface for a wide range of microcontrollers. The high-speed microcontroller interface increases system throughput and reduces processor utilization. The ISP1582/83 can be configured to function, with a common USB bus enumeration process, as a Generic Direct Memory Access (GDMA) application or a mass storage application. Fig 1 shows the ISP1582/83 firmware-programming model. ISP1582/83 initialization Mass storage initialization Mass storage or GDMA GDMA initialization USB enumeration Mass storage process Mass storage or GDMA GDMA process End Fig 1. Flowchart of the ISP1582/83 firmware-programming model _4 Application note Rev. 04 21 December 2006 3 of 49

2. ISP1582/83 initialization routine 2.1 Initializing the ISP1582/83 registers The initialization routine depends on the application targeted, such as mass storage and GDMA, for the ISP1582/83. The routine has most of the initializations common to all applications, except for the DMA Configuration and DMA Hardware registers that determine the function of the ISP1582/83. Fig 2 shows the flowchart of the ISP1582/83 register initialization. Initialize Mode register Initialize Interrupt Configuration register Initialize Interrupt Enable register Initialize DMA Configuration register Initialize DMA Hardware register Initialize DMA Burst Counter register Initialize DMA Interrupt Enable register Initialize endpoint End Fig 2. Register initialization _4 Application note Rev. 04 21 December 2006 4 of 49

Table 1. 2.2 Initializing the Mode register After the power-on reset, the processor initializes the Mode register (see Table 1). This register can be programmed, depending on the application. ISP1583 Mode register: bit allocation Bit 15 14 13 12 11 10 9 8 Symbol TEST2 TEST1 TEST0 reserved DMACLK ON Reset - - - - - - 0 Bus reset - - - - - - 0 VBUSSTAT [1] [1] Access R R R - - - R/W R Bit 7 6 5 4 3 2 1 0 Symbol CLKAON SNDRSU GOSUSP SFRESET GLINTENA WKUPCS PWRON SOFTCT Reset 0 0 0 0 0 0 0 0 Bus reset 0 0 0 0 unchanged 0 0 unchanged Access R/W R/W R/W R/W R/W R/W R/W R/W [1] Value depends on the status of the V BUS pin. The DMACLKON bit of the Mode register determines whether the clock must be supplied to the DMA core of the ISP1582/83. Disabling the bit at initialization saves power. The DMA clock can be switched on when DMA is required using the DMACLKON bit. Power can also be saved by disabling clock CLKAON during suspend mode. It is recommended that you use this power-saving mechanism to save power when the ISP1582/83 is configured to bus-powered applications. Next, set the global interrupt enable (bit GLINTENA) to enable the interrupt mechanism of the ISP1582/83. The ISP1582/83 allows you to wake up the system from suspend mode by toggling the chip select (pin CS_N) of the ISP1582/83. The ISP1582/83 allows you to design systems to support sleep mode, in which power to the ISP1582/83 is turned off to save power. The PWRON bit in the Mode register configures the ISP1582/83 into two modes of operation when it is in the suspend state. When the bit is set to logic 0, the firmware must issue an unlock command to the ISP1582/83 before any write operation to a register can be performed. This prevents accidental writing to registers when the processor wakes up from power-saving mode. The SoftConnect feature (bit SOFTCT) is used to connect the pull-up resistor to the DP line of the ISP1582/83. This affords you complete discretion on when to connect and disconnect from the USB bus. The SOFTCT bit is used together with V BUS (bit VBUSSTAT) that reflects whether the USB cable is plugged in or out. 2.3 Initializing the Interrupt Configuration register After the Mode register is set, the Interrupt Configuration register (see Table 2) is initialized. This register controls how an interrupt is generated for the control pipe, IN endpoint and OUT endpoint. _4 Application note Rev. 04 21 December 2006 5 of 49

Table 2. Interrupt Configuration register: bit allocation Bit 7 6 5 4 3 2 1 0 Symbol CDBGMOD[1:0] DDBGMODIN[1:0] DDBGMODOUT[1:0] INTLVL INTPOL Reset 1 1 1 1 1 1 0 0 Bus reset 1 1 1 1 1 1 unchanged unchanged Access R/W R/W R/W R/W R/W R/W R/W R/W The interrupt generation depends on the type of mode setting specified in the register; see Table 3. CDBGMOD is for the control pipe, DDBGMODIN is for the IN pipe, and DDBGMODOUT is for the OUT pipe. The register sets the interrupt to the level or pulse trigger by using the INTLVL bit. The polarity of the interrupt signal is control by INTPOL. Table 3. Debug mode settings Value CDBGMOD DDBGMODIN DDBGMODOUT 00h Interrupt on all ACK and NAK Interrupt on all ACK and NAK Interrupt on all ACK, NYET and NAK 01h Interrupt on all ACK Interrupt on ACK Interrupt on ACK and NYET 1Xh Interrupt on all ACK and first NAK Interrupt on all ACK and first NAK Interrupt on all ACK, NYET and first NAK The typical function of the Interrupt Configuration register is to enable the ACK interrupt. Fig 3 show the CATC trace of the ACK interrupt, with the red arrows indicating the interrupt signal that will be generated on the INT pin when an ACK condition occurs. Fig 3. CATC capture of setup and OUT ACK interrupt The following sample code programs the IN endpoint interrupt to all ACK conditions; OUT endpoint, interrupt to all ACK and NYET condition, control endpoint interrupt to all ACK conditions: Void Init_D14_SFR(void) { //Set the control pipe to ACK only interrupt //Set the IN pipe to ACK only interrupt //Set OUT pipe to ACK and NYET interrupt D14_Cntrl_Reg.D14_INT_CONFIG = 0x54; _4 Application note Rev. 04 21 December 2006 6 of 49

} Fig 4. CATC capture of IN ACK interrupt The OUT endpoint is programmed to all ACK and NYET interrupts as shown in Fig 5. Fig 5. CATC capture of OUT ACK and NYET interrupt 2.4 Initializing the Interrupt Enable register Next is the initialization of the Interrupt Enable register (see Table 4). Setting the respective bit to logic 1 enables the interrupt signal to be generated on the INT pin of the ISP1582/83. Take into consideration the Interrupt Service Routine (ISR) because an AND operation must be performed on the bits in the Interrupt register with the Interrupt Enable register. The Interrupt register reflects the status bit of the respective event, even if the enable bit is not set in the Interrupt Enable register. _4 Application note Rev. 04 21 December 2006 7 of 49

Table 4. Interrupt Enable register: bit allocation Bit 31 30 29 28 27 26 25 24 Symbol reserved IEP7TX IEP7RX Reset - - - - - - 0 0 Bus reset - - - - - - 0 0 Access - - - - - - R/W R/W Bit 23 22 21 20 19 18 17 16 Symbol IEP6TX IEP6RX IEP5TX IEP5RX IEP4TX IEP4RX IEP3TX IEP3RX Reset 0 0 0 0 0 0 0 0 Bus reset 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 15 14 13 12 11 10 9 8 Symbol IEP2TX IEP2RX IEP1TX IEP1RX IEP0TX IEP0RX reserved IEP0 SETUP Reset 0 0 0 0 0 0-0 Bus reset 0 0 0 0 0 0-0 Access R/W R/W R/W R/W R/W R/W - R/W Bit 7 6 5 4 3 2 1 0 Symbol IEVBUS IEDMA IEHS_STA IERESM IESUSP IEPSOF IESOF IEBRST Reset 0 0 0 0 0 0 0 0 Bus reset 0 0 0 0 0 0 0 unchanged Access R/W R/W R/W R/W R/W R/W R/W R/W The following is a sample code for the ISR: Void Int_Ext_0(void) interrupt 0 using 1 { // Read in USB interrupt reason register USB_Int_Flag.VALUE = D14_Cntrl_Reg.D14_INT.VALUE; USB_Int_Flag.VALUE &= D14_INT_ENABLE; // Read in DMA interrupt register DMA_Int_Flag.VALUE = D14_Cntrl_Reg.D14_DMA_INT.VALUE; DMA_Int_Flag.VALUE &= D14_DMA_INT_ENABLE; } //Clear DMA interrupt register D14_Cntrl_Reg.D14_DMA_INT.VALUE = DMA_Int_Flag.VALUE; // Clear USB interrupt reason register D14_Cntrl_Reg.D14_INT.VALUE = USB_Int_Flag.VALUE; _4 Application note Rev. 04 21 December 2006 8 of 49

Table 5. 2.5 Initializing the DMA Configuration and Hardware registers Next, you configure the DMA Configuration register (see Table 5) and DMA Hardware register (see Table 6) to either GDMA or mass storage application. Based on the application, some associated registers must be programmed. ISP1583 DMA Configuration register: bit allocation Bit 15 14 13 12 11 10 9 8 Symbol reserved ATA_ MODE DMA_MODE[1:0] PIO_MODE[2:0] Reset - - 0 0 0 0 0 0 Bus reset - - 0 0 0 0 0 0 Access - - R/W R/W R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 Symbol DIS_XFER_ CNT reserved MODE[1:0] reserved WIDTH Reset 0 - - - 0 0-1 Bus reset 0 - - - 0 0-1 Access R/W - - - R/W R/W - R/W Table 6. ISP1583 DMA Hardware register: bit allocation Bit 7 6 5 4 3 2 1 0 Symbol ENDIAN[1:0] EOT_POL MASTER ACK_POL DREQ_ POL WRITE_ POL READ_POL Reset 0 0 0 0 0 1 0 0 Bus reset 0 0 0 0 0 1 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W The ISP1582/83 can be configured to various operation modes, depending on the combination of the various bits in the DMA Configuration and DMA Hardware registers. Table 7 illustrates valid combinations. Remark: Only ISP1583 supports DMA master and ATA mode. Table 7. DMA configuration ATA mode Master DMA mode PIO mode DIS_XFER _CNT Mode Width Description 0 0 t used t used 0 0 1 GDMA slave mode DMA transfer counter DIOR as read strobe DIOW as write strobe 16-bit data bus _4 Application note Rev. 04 21 December 2006 9 of 49

ATA mode Master DMA mode PIO mode DIS_XFER _CNT Mode Width Description t used t used 0 1 1 GDMA slave mode DMA transfer counter DIOR as read strobe DACK as write strobe 16-bit data bus t used t used 0 2 1 GDMA slave mode DMA transfer counter DACK as read strobe DACK as write strobe 16-bit data bus t used t used 1 2 1 GDMA slave mode EOT mode DACK as read strobe DACK as write strobe 16-bit data bus t used t used 0 0 0 GDMA slave mode DMA transfer counter DIOR as read strobe DIOW as write strobe 8-bit data bus t used t used 0 1 0 GDMA slave mode DMA transfer counter DIOR as read strobe DACK as write strobe 8-bit data bus t used t used 0 2 0 GDMA slave mode DMA transfer counter DACK as read strobe DACK as write strobe 8-bit data bus t used t used 1 2 0 GDMA slave mode EOT mode DACK as read strobe DACK as write strobe 8-bit data bus 1 0 0 0 t used t used 1 ATA mode MDMA mode 0 strobe timing PIO mode 0 timing _4 Application note Rev. 04 21 December 2006 10 of 49

ATA mode Master DMA mode PIO mode DIS_XFER _CNT Mode Width Description 1 1 t used t used 1 ATA mode MDMA mode 1 strobe timing PIO mode 1 timing 2 2 t used t used 1 ATA mode MDMA mode 2 strobe timing PIO mode 2 timing 2 3 t used t used 1 ATA mode MDMA mode 2 strobe timing PIO mode 3 timing 2 4 t used t used 1 ATA mode MDMA mode 2 strobe timing PIO mode 4 timing 1 1 t used t used t used 0 1 GDMA Master mode DMA Transfer Counter ATA MDMA 0 Strobe timing 16-bit data bus t used t used t used 1 1 GDMA master mode DMA transfer counter ATA MDMA 1 strobe timing 16-bit data bus t used t used t used 2 1 GDMA master mode DMA transfer counter ATA MDMA 2 strobe timing 16-bit data bus t used t used t used 0 0 GDMA master mode DMA transfer counter ATA MDMA 0 strobe timing 8-bit data bus t used t used t used 1 0 GDMA master mode DMA transfer counter ATA MDMA 1 strobe timing 8-bit data bus t used t used t used 2 0 GDMA master mode DMA transfer counter ATA MDMA 2 strobe timing 8-bit data bus 0 1 Invalid Invalid Invalid Invalid Invalid Invalid mode _4 Application note Rev. 04 21 December 2006 11 of 49

When DIS_XFER_CNT is set to logic 1, the DMA transfer counter is not in use, and the DMA termination is done using the input signal of pin EOT. This mode is called EOT mode. The polarity of pin EOT can be set using the EOT_POL bit of the DMA Hardware register. 2.6 Initializing DMA burst counter The DMA burst counter is initialized in multiples of two for 16-bit mode. DREQ is asserted and de-asserted based on the value in the DMA Burst Counter register. 2.7 Initializing DMA interrupt enable The IEDMA bit in the Interrupt Enable register must be logic 1 to enable DMA interrupts on the INT pin. The respective bits of the DMA Interrupt Enable register are set to logic 1 to enable interrupt on the INT pin. If the bits are set to logic 0, the interrupt status is reflected on the DMA Interrupt Reason register but the interrupt does not appear on the INT pin. 2.8 Initializing the ISP1582/83 endpoint The endpoint FIFO configuration is done using the Endpoint MaxPacketSize register (see Table 8) and the Endpoint Type register (Table 9), and indexed using the Endpoint Index register (see Table 10). For the same endpoint number, ensure that initialization is done for both the IN and OUT, even if only IN or OUT is used. Table 8. Endpoint MaxPacketSize register: bit allocation Bit 15 14 13 12 11 10 9 8 Symbol reserved NTRANS[1:0] FFOSZ[10:8] Reset - - - 0 0 0 0 0 Bus reset - - - 0 0 0 0 0 Access - - - R/W R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 Symbol FFOSZ[7:0] Reset 0 0 0 0 0 0 0 0 Bus reset 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W _4 Application note Rev. 04 21 December 2006 12 of 49

Table 9. Endpoint Type register: bit allocation Bit 15 14 13 12 11 10 9 8 Symbol reserved Reset - - - - - - - - Bus reset - - - - - - - - Access - - - - - - - - Bit 7 6 5 4 3 2 1 0 Symbol reserved NOEMPKT ENABLE DBLBUF ENDPTYP[1:0] Reset - - - 0 0 0 0 0 Bus reset - - - 0 0 0 0 0 Access - - - R/W R/W R/W R/W R/W Table 10. Endpoint Index register: bit allocation Bit 7 6 5 4 3 2 1 0 Symbol reserved EP0SETUP ENDPIDX[3:0] DIR Reset - - 0 0 0 0 0 0 Bus reset - - 0 0 0 0 0 0 Access - - R/W R/W R/W R/W R/W R/W Initialization of the endpoint is done as depicted in the flowchart in Fig 6. _4 Application note Rev. 04 21 December 2006 13 of 49

Full-speed Initialize the Endpoint Index to the required endpoint High-speed or fullspeed High-speed Initialize the Endpoint Index to the required endpoint Set the MaxPacketSize of the endpoint to full-speed Set the MaxPacketSize of the endpoint to high-speed All endpoints configured? Initialize the endpoint index to the required endpoint Set endpoint type and enable endpoint All endpoints configured? End _4 Fig 6. Initializing endpoint The initialization routine is used when: The system is powered up. A bus-reset event occurs. There is a change from full-speed to high-speed. The following is a sample code for the endpoint initialization: void Init_Endpoint(void) { //check if device in full speed state Application note Rev. 04 21 December 2006 14 of 49

if(kernel_flag.bits.hs_fs_state == FULL_SPEED) { //Bulk Out MaxPacketSize Endpoint D14_Cntrl_Reg.D14_ENDPT_INDEX = 4; D14_Cntrl_Reg.D14_ENDPT_MAXPKTSIZE.VALUE = 0x4000; } //Bulk In MaxPacketSize Endpoint D14_Cntrl_Reg.D14_ENDPT_INDEX = 5; D14_Cntrl_Reg.D14_ENDPT_MAXPKTSIZE.VALUE = 0x4000; //Bulk Out Endpoint Type D14_Cntrl_Reg.D14_ENDPT_INDEX = 4; D14_Cntrl_Reg.D14_ENDPT_TYPE.VALUE = 0x1600; //Bulk In Endpoint Type D14_Cntrl_Reg.D14_ENDPT_INDEX = 5; D14_Cntrl_Reg.D14_ENDPT_TYPE.VALUE = 0x1600; //enable FIFO D14_Cntrl_Reg.D14_ENDPT_INDEX = 4; D14_Cntrl_Reg.D14_ENDPT_TYPE.VALUE = 0x0800; //enable FIFO D14_Cntrl_Reg.D14_ENDPT_INDEX = 5; D14_Cntrl_Reg.D14_ENDPT_TYPE.VALUE = 0x0800; //check if device in high speed if(kernel_flag.bits.hs_fs_state == HIGH_SPEED) { //Bulk Out MaxPacketSize Endpoint D14_Cntrl_Reg.D14_ENDPT_INDEX = 4; D14_Cntrl_Reg.D14_ENDPT_MAXPKTSIZE.VALUE = 0x0002; //Bulk In MaxPacketSize Endpoint D14_Cntrl_Reg.D14_ENDPT_INDEX = 5; D14_Cntrl_Reg.D14_ENDPT_MAXPKTSIZE.VALUE = 0x0002; //Bulk Out Endpoint Type D14_Cntrl_Reg.D14_ENDPT_INDEX = 4; D14_Cntrl_Reg.D14_ENDPT_TYPE.VALUE = 0x1600; //Bulk In Endpoint Type D14_Cntrl_Reg.D14_ENDPT_INDEX = 5; D14_Cntrl_Reg.D14_ENDPT_TYPE.VALUE = 0x1600; //enable FIFO D14_Cntrl_Reg.D14_ENDPT_INDEX = 4; D14_Cntrl_Reg.D14_ENDPT_TYPE.VALUE = 0x0800; _4 Application note Rev. 04 21 December 2006 15 of 49

} } //enable FIFO D14_Cntrl_Reg.D14_ENDPT_INDEX = 5; D14_Cntrl_Reg.D14_ENDPT_TYPE.VALUE = 0x0800; The initialization of the endpoint is done as shown in Fig 6 to allow the endpoint FIFO RAM to be configured. Ensure that the total FIFO size of endpoints does not exceed 8 kb. 3. ISP1582/83 USB enumeration process The USB enumeration process can be divided into three categories: Set-up token with the data IN stage; see Section 3.1 Set-up token with the data OUT stage; see Section 3.2 Set-up token with no data stage; see Section 3.3 Besides these categories, there is also a stalling procedure for the endpoint (see Section 3.4). Pay special attention when stalling the endpoint of the ISP1582/83. The Endpoint Index register is used to reference the control endpoint and the set-up endpoint. The set-up endpoint is 8 bytes in length. It is used to store the USB peripheral request from the host. The firmware only needs to program the EP0SETUP bit of the ISP1582/83 (see Table 10) to reference the index to the set-up endpoint. Data from the set-up or control endpoint, indexed by the endpoint index is read from the FIFO using the Data Port register; see Table 10. Table 11. Data Port register: bit allocation Bit 15 14 13 12 11 10 9 8 Symbol DATAPORT[15:8] Reset 0 0 0 0 0 0 0 0 Bus reset 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 Symbol DATAPORT[7:0] Reset 0 0 0 0 0 0 0 0 Bus reset 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W When writing to the endpoint, the Data Port register is also used for the data transfer to the control IN endpoint. The control endpoint is controlled by the Control Function register (see Table 12) that allows the firmware to clear data in the OUT endpoint by using the CLBUF bit. The endpoint FIFO can be validated either by the Buffer Length register or by the VENDP bit in the Control Function register. The Buffer Length register (see Table 13) reflects the amount of data in the OUT endpoint. As for the IN endpoint _4 Application note Rev. 04 21 December 2006 16 of 49

Table 12. FIFO, the buffer length is a means for the firmware to auto-validate the FIFO once the value is reached. It is used when data to be sent in the IN endpoint is a short packet. Control Function register: bit allocation Bit 7 6 5 4 3 2 1 0 Symbol reserved CLBUF VENDP DSEN STATUS STALL Reset - - - 0 0 0 0 0 Bus reset - - - 0 0 0 0 0 Access - - - R/W R/W R/W R/W R/W Table 13. Buffer Length register: bit allocation Bit 15 14 13 12 11 10 9 8 Symbol DATACOUNT[15:8] Reset 0 0 0 0 0 0 0 0 Bus reset 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 Symbol DATACOUNT[7:0] Reset 0 0 0 0 0 0 0 0 Bus reset 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W In the control function, the DSEN bit is for the ISP1582/83 to proceed to the data stage. If the set-up token is with a data OUT stage, the firmware must set the DSEN bit to the ISP1582/83 for the device to generate an ACK handshake to the OUT endpoint. This bit also governs the IN endpoint data. An IN endpoint after a set-up token with the data IN stage will not be sent to the USB bus even when the VENDP bit is issued. Therefore, the DSEN bit must be set for the ISP1582/83 to proceed to the data stage of the setup. Remark: The DSEN bit is cleared once the OUT token is acknowledged by the device and the IN token is acknowledged by the PC host. The status stage is achieved by setting the STATUS bit in the Control Function register. On setting the STATUS bit, the endpoint will generate a zero-length packet to the IN token and send an ACK for the OUT token. The status stage will not generate the control IN endpoint interrupt. Remark: The STATUS bit is cleared to zero once the zero-length packet is acknowledged by the device or the PC host. _4 Application note Rev. 04 21 December 2006 17 of 49

3.1 Set-up token with data IN stage Set-up token interrupt occurs Initialize the endpoint index to the set-up endpoint by using bit EP0SETUP It is not required to read the buffer length of the set-up token buffer because all USB request is 8 bytes in length and the set-up FIFO is also 8 bytes in length Read the device request from the Data Port register Proceed to other set-up token process Set-up token with data IN The buffer length and the VENDP bit of the Control Function register is not required when data length is 64 bytes Initialize the endpoint index to the control IN endpoint Set the DSEN bit register to enable the data stage Fill the IN endpoint to 64 bytes Firmware determines whether the descriptor length is greater than 64 bytes IN token ACK interrupt occur Descriptor length > 64 bytes Next block of data > 64 bytes Fill the IN endpoint with the partial data and set the VENDP bit of the Control Function register Fill the IN endpoint with the device request data and validate using the Buffer Length register or the VENDP bit When the buffer length is used, bit VENDP of the Control Function register is not required and vice versa. IN token ACK interrupt occur Initialize the endpoint index to the control OUT endpoint Set the STATUS bit to terminate the set-up token with data IN OUT endpoint interrupt generated for the STATUS stage End Fig 7. Set-up token with data IN stage _4 Application note Rev. 04 21 December 2006 18 of 49

3.2 Set-up token with data OUT stage Set-up token interrupt occurs Initialize the endpoint index to the set-up endpoint by using bit EP0SETUP It is not required to read back the buffer length of the set-up token buffer because all USB request is 8 bytes in length and the set-up FIFO is also 8 bytes in length Read the device request from the Data Port register Proceed to other set-up token process Set-up token with data OUT Initialize the endpoint index to the control OUT endpoint Set the DSEN bit in the Control Function register OUT token ACK interrupt occurs Check the endpoint data length by using the Buffer Length register and start reading the OUT data Check if all OUT token is received All OUT received Initialize the endpoint index to the control IN endpoint Set the STATUS bit of the Control Function register to terminate the set-up token with data OUT IN endpoint interrupt generated for the status stage End Fig 8. Set-up token with data OUT stage _4 Application note Rev. 04 21 December 2006 19 of 49

3.3 Set-up token with no data stage Set-up token interrupt occurs Initialize the endpoint index to the set-up endpoint by using bit EP0SETUP It is not required to read back the buffer length of the set-up token buffer because all USB request is 8 bytes in length and the set-up FIFO is also 8 bytes in length Read the device request from the Data Port register Proceed to other set-up token process Set-up token without data Initialize the endpoint index to the control IN endpoint Set the STATUS bit of the Control Function register to terminate the set-up token without data IN endpoint interrupt generated for the status stage End Fig 9. Set-up token with no data stage _4 Application note Rev. 04 21 December 2006 20 of 49

3.4 Stalling set-up token Set-up token interrupt occurs Initialize the endpoint index to the set-up endpoint by using bit EP0SETUP Read the device request from the Data Port register Proceed to set-up token process Set-up token not supported Initialize the endpoint index to control IN endpoint Set the STALL bit to stall the endpoint Host receives stall and will send the clear feature request to the device Device receive the clear feature token Set the Endpoint Index register to the stalled endpoint Endpoint is unstalled by clearing the STALL bit Disable and enable by clearing and setting the ENABLE bit Set the endpoint index to a value other than that in the DMA Endpoint register. Set the DMA Endpoint register to the stalled endpoint and issue a Clear Buffer command to the DMA Command register End Fig 10. Stalling set-up token _4 Application note Rev. 04 21 December 2006 21 of 49

3.5 Data IN transfer Index to IN endpoint Data > MaxPacketSize? Fill Buffer Length register with the data size Fill MaxPacketSize of Data to Data Port register Fill data to Data Port register IN token ACK interrupt occurs IN token ACK interrupt occurs Filled data is sent to Host successfully Filled data is sent to Host successfully Next block of data > MaxPacketSize? End Fig 11. Data IN transfer _4 Application note Rev. 04 21 December 2006 22 of 49

3.6 Data OUT transfer OUT token interrupt occurs? Index to OUT endpoint Check the endpoint data length using the Buffer Length register Read data port register for the size of data specified in buffer length register Is All OUT token data read? End Fig 12. Data OUT transfer _4 Application note Rev. 04 21 December 2006 23 of 49

4. DMA 4.1 DMA reset The DMA reset command is used to reset the DMA core to the power-on reset state. Issue the DMA reset command using the DMA command register. 4.2 DMA start To issue a DMA transfer: 1. Initialize the Endpoint Index register to a value not equal to the selected endpoint. 2. Initialize the DMA Endpoint register to the value of the selected endpoint buffer. 3. Assign the DMA transfer counter to the number of bytes to be transferred. 4. Write the required DMA command to the DMA Command register, depending on the application. 4.3 DMA stop The GDMA stop command is used to stop the GDMA transfer command and the MDMA stop command is used to stop the MDMA transfer command. These commands are used to abruptly stop a transfer. To issue a DMA stop: 5. Assign to the Endpoint Index register a value not equal to the selected endpoint. 6. Initialize the DMA Endpoint register to the respective endpoint. 7. Issue the GDMA stop (for a GDMA transfer) or MDMA stop (for a MDMA transfer) command using the DMA Command register. 4.4 DMA interrupt handling A DMA transfer will either be successfully completed or terminated. To identify the interrupt source, the status in the Interrupt register and the DMA Interrupt Reason register must be read during the interrupt service routine. If bit DMA_XFER_OK in the DMA Interrupt Reason register is asserted, it means the transfer counter has reached zero and the DMA transfer was successfully stopped. If bit INT_EOT in the DMA Interrupt Reason register is set, it indicates that a short or empty packet was received. That is, DMA transfer was terminated. rmally, for an OUT transfer, it means that the remote host wishes to terminate the DMA transfer. If bits DMA_XFER_OK and INT_EOT are simultaneously set, it means the transfer counter reached zero and the last packet of the transfer is a short packet. Therefore, the DMA transfer was successfully stopped. If bit GDMA_STOP in the DMA Interrupt Reason register is set, it indicates the GDMA transfer is abruptly stopped by the issue of the GDMA stop command in the DMA command register. _4 Application note Rev. 04 21 December 2006 24 of 49

5. Mass storage application After successful enumeration, the respective device drivers come into play. For a mass storage application, the firmware must conform to USB Mass Storage Class Bulk-Only Transport Specification and the ATA/ATAPI protocol. The host sends a 31-byte Command Block Wrapper (CBW). The ATAPI command is embedded in CBW. In an ATAPI device, for each CBW received, the ATAPI packet command is issued to the device, followed by the ATAPI command in CBW. In an ATA device, the ATAPI command in CBW must be translated into an ATA command, before it is issued to the device. The ATAPI command phase is followed by an optional data phase, which is followed by a status phase. If the command is successfully completed, the firmware must report good status in the status field of the 13-byte Command Status Wrapper (CSW). See Table 14 and Table 15 for CBW and CSW, respectively. Table 14. Command Block Wrapper Bit 7 6 5 4 3 2 1 0 Byte 30 to 15 (1Eh to 0Fh) CBWCB 14 (0Eh) reserved (0) bcbwcblength 13 (0Dh) reserved (0) bcbwlun 12 (0Ch) bmcbwflags 11 to 8 (0Bh to 08h) dcbwdatatransferlength 7 to 4 dcbwtag 3 to 0 dcbwsignature Table 15. Command Status Wrapper Bit 7 6 5 4 3 2 1 0 Byte 12 (0Ch) bcswstatus 11 to 8 (0Bh to 08h) dcswdataresidue 7 to 4 dcswtag 3 to 0 dcswsignature _4 Application note Rev. 04 21 December 2006 25 of 49

5.1 Mass storage protocol Bulk-only mass storage protocol ATA and ATAPI protocol Check if the OUT token is 31 bytes CBW received? Process the CBW and issue command to the drive Data IN or OUT process Data stage required Determine the status of the drive Status error? Report CSW with error status Report CSW with good status Stop Fig 13. Mass storage protocol 5.1.1 Extracting Command Block Wrapper 8. Initialize the Endpoint Index register to the respective OUT endpoint. 9. Read the Buffer Length register. A buffer length of 31 indicates a command packet is in the buffer. 10. Read the Data Port register to extract CBW. 11. Check for valid CBW signature in the command block. If the CBW signature is valid, the command is issued to the ATA or ATAPI device. For an invalid command block, the respective OUT endpoint is stalled. _4 Application note Rev. 04 21 December 2006 26 of 49

5.1.2 Handling CBW for ATA and ATAPI device 1. Initialize the Drive Select register (1F6) to the master or slave, based on the device present. 2. Initialize the Error or Feature register to 1 for a DMA transfer. 3. Initialize the ATAPI Byte Count LSB and ATAPI Byte Count MSB registers to the number of bytes to be transferred as specified in CBW. 4. The ATAPI packet command is issued to the device by writing the Command or Status register. 5. Issue the 12-byte command block in CBW to the Task File Data register. 6. Check for the next phase. If CBW.dCBWDataTransferLength is zero, then the next phase is status. If CBW.dCBWDataTransferLength is non-zero and USB_CBW.bmCBWFlags is 80h, then the next phase is read. If CBW.dCBWDataTransferLength is non-zero and USB_CBW.bmCBWFlags is not equal to 80h, then the next phase is write. 7. The read or write phase is followed by the status phase. _4 Application note Rev. 04 21 December 2006 27 of 49

Initialize the Drive or Select register to master or slave Initialize the Error or Feature register to one for DMA Initialize ATAPI byte count LSB and MSB Write the ATAPI packet command to the Command or Status register Write 12-byte command in CBW to the Task File Data register CBW.dCBWDataTransferLength not equal to zero CBW.bmCBWFlags == 0x80 ATAPI Write Phase ATAPI Read Phase ATAPI Status phase Stop Fig 14. Handling CBW for ATAPI device _4 Application note Rev. 04 21 December 2006 28 of 49

Initialize the Endpoint Index register to the OUT endpoint Initialize the DMA Transfer Counter register to CBW.dCBWDataTranferLength Write to the DMA Command register with the DMA or PIO write command Bits CMD_INTRQ_OK and INTRQ_PENDING refrr to the variable to which the DMA Interrupt Reason register is copied in the interrupt routine CMD_INTRQ_OK == 0 AND INTRQ_PENDING == 0 DMA Interrupt Reason register: bit allocation Read the DMA transfer counter to check for partial transfer A nonzero value indicates partial transfer CMD_INTRQ_OK == 0 AND INTRQ_PENDING == 1 Clear INTRQ_PENDING Read the Command or Status Task File register CMD_INTRQ_OK == 1 AND INTRQ_PENDING == 1 Clear CMD_INTRQ_OK DMA Command register = DMA_FLUSH set transfer error flag Partial transfer CMD_INTRQ_OK == 0 Clear CMD_INTRQ_OK Clear CMD_INTRQ_OK Clear INTRQ_PENDING CMD_INTRQ_OK == 0 AND INTRQ_PENDING == 0 Clear CMD_INTRQ_OK Clear INTRQ_PENDING Stop Fig 15. ATAPI write phase _4 Application note Rev. 04 21 December 2006 29 of 49

Initialize the Endpoint Index register to the IN endpoint Initialize the DMA Transfer Counter register to CBW.dCBWDataTransferLength Write to the DMA Command register with the DMA or PIO Read command Bits CMD_INTRQ_OK and INTRQ_PENDING are from a variable to which the DMA Interrupt Reason register is copied in the interrupt routine CMD_INTRQ_OK == 0 AND INTRQ_PENDING == 0 DMA Interrupt Reason register: bit allocation Read the DMA transfer counter to check for partial transfer. A nonzero value indicates partial transfer. CMD_INTRQ_OK == 0 AND INTRQ_PENDING == 1 Clear INTRQ_PENDING Read the Command or Status Task File register CMD_INTRQ_OK == 1 AND INTRQ_PENDING == 1 Partial transfer Clear CMD_INTRQ_OK DMA command regiser = DMA_FLUSH set transfer error flag Clear CMD_INTRQ_OK Clear INTRQ_PENDING CMD_INTRQ_OK == 0 AND INTRQ_PENDING == 0 CMD_INTRQ_OK == 0 Clear CMD_INTRQ_OK Clear INTRQ_PENDING Clear CMD_INTRQ_OK Stop Fig 16. ATAPI read phase _4 Application note Rev. 04 21 December 2006 30 of 49

Bits INTRQ_PENDING and CMD_INTRQ_OK refer to the variable to which DMA Interrupt Reason register is copied in the interrupt routine CMD_INTRQ_OK == 0 AND INTRQ_PENDING == 0 Clear INTRQ_PENDING Read the Command or Status Task File register INTRQ_PENDING == 1 AND CMD_INTRQ_OK == 0 INTRQ_PENDING == 1 AND CMD_INTRQ_OK == 1 Clear CMD_INTRQ_OK Clear INTRQ_PENDING Clear CMD_INTRQ_OK INTRQ_PENDING == 1 AND CMD_INTRQ_OK == 1 Clear INTRQ_PENDING Clear CMD_INTRQ_OK Read alternate Status or Device Control Task File register Alternate Status or Device Control Task File register AND 0x01 == 1 Set Error_Occur flag Reset Error_Occur flag Stop Fig 17. ATAPI status phase _4 Application note Rev. 04 21 December 2006 31 of 49

5.1.3 Handling invalid CBW A command block is invalid if it has an invalid CBW signature. 1. Initialize the Endpoint Index register to the respective OUT endpoint. 2. Set the STALL bit in the Control Function register. When the host receives a stall, it will send a clear feature command. Wait for the set-up token interrupt for the clear feature. 3. Initialize the Endpoint Index register to the respective OUT endpoint, and clear the STALL bit in the Control Function register. 4. Set and reset the ENABLE bit in the Endpoint Type register. This will reset the data toggle. 5. Initialize the Endpoint Index register to 1 and set the STATUS bit in the Control Function register 6. Wait till the EP0Tx interrupt is received. 7. Wait for the EP0SETUP interrupt, for the bulk-only mass storage reset command. 8. Initialize the Endpoint Index register, by setting the EP0SETUP bit in the Endpoint Index register. 9. Read the set-up buffer and re-initialize the ATA or ATAPI device, for a valid mass storage reset command. 5.1.4 Handling error If the error_occur flag or transfer_error flag is set, the error must be handled, by stalling the respective endpoint involved in the transfer. For the data OUT transfer, the respective OUT endpoint is stalled. For the data IN transfer, the respective IN endpoint is stalled. Clear the error_occur and transfer_error flags. 5.1.5 Handling CBW for an ATA device CBW contains the ATAPI command embedded in the command block. For an ATA device, the ATAPI packet command must be translated into an ATA command, before it is issued to the device. The CBWCDB[0] field in CBW contains the ATAPI command and the remaining field contains command parameters. Based on the ATAPI command, the corresponding ATA command is selected and issued to the device. _4 Application note Rev. 04 21 December 2006 32 of 49

Is CBWCDB[0] == INQUIRY CMD B Handle ATA inquiry A Is CBWCDB [0] == READ_10 CMD Is CBWCDB [0] == WRITE_10 CMD Handle ATA WRITE_10 CMD Handle ATA READ_10 A Is CBWCDB [0] == READ_CAPACITY CMD A Is CBWCDB [0] == TEST_UNIT_READY CMD Handle ATA READ_CAPACITY A Is CBWCDB [0] == READ_FORMAT_CAPACITIES CMD Handle ATA READ_FORMAT- CAPACITIES Error_Code.SENSE_KEY = 0 Error_Code.ASC = 0 Error_Code.ASCQ = 0 Reset Error_Occur flag Is CBWCDB [0] == REQUEST_SENSE CMD A CBW.Length!= 0 AND CBW.dCBWFlags == 0x80 Handle ATA REQUEST_SENSE A Is CBWCDB [0] == MODE_SENSE_10 CMD Initialize the Endpoint Index register the IN endpoint Validate the endpoint Handle ATA MODE_SENSE_10 B Is CBWCDB [0] == START_STOP_UNIT/MODE_SENSE_06/ MODE_SELECT_06 CMD A Stop Handle ATA MODE_SENSE_06 A B Fig 18. Handling ATA command translator _4 Application note Rev. 04 21 December 2006 33 of 49

Initialize the drive select Task File register to master or slave based on the device present Initialize the Endpoint Index register to the respective IN endpoint Bits INTRQ_PENDING, CMD_INTRQ_OK and READ_1F0 are from a variable to which DMA Interrupt reason register is copied in the interrupt routine Is CBW.dCBWDataTransferLength == 6 Initialize the DMA transfer counter = 512 Initialize the Byte count Task File register = 512 Issue ATA IDENTIFY DEVICE command by writing to the Command or Status Task File register INTRQ_PENDING == 0 AND CMD_INTRQ_OK == 0 Write values 0x00, 0x00, 0x00, 0x01, 0x1F, 0x00 to the Data Port register Bytes_Transferred_Count = CBW.dCBWDataTransferLength INTRQ_PENDING = 0 CMD_INTRQ_OK = 0 DMA Command register = READ_1F0 READ_1F0 == 0 READ_1F0 = 0 Read to the Data Task File register (LSB) 512 times and store the Model number in the identify device Write to the Data Port register 0x00, 0x00, 0x00, 0x01, 0x1F, 0x00, 0x00, 0x00 and the Model number Validate the data using VENP in the Control Function register Bytes_Transferred_Count = CBW.dCBWDataTranferLength Stop Fig 19. Handling ATA_INQUIRY _4 Application note Rev. 04 21 December 2006 34 of 49

Is CBW.dCBWFlags == 0 Initialize the Endpoint Index register to the respective IN endpoint Initialize the Endpoint Index register to the respective OUT endpoint DMA Transfer Counter register = Atapi_Bytecount Is CBW.dCBWFlags == 0 DMA command register = MDMA_Read_command INTRQ_PENDING == 0 AND CMD_INTRQ_OK == 0 DMA command register = MDMA_Write_command Bits CMD_INTRQ_OK and INTRQ_PENDING refer to the variable to which the DMA Interrupt Reason register is copied in the interrupt routine Read the DMA Transfer Counter register to check partial transfer Byte_Transfered_Count = DMA Transfer Counter register INTRQ_PENDING == 1 AND CMD_INTRQ_OK == 0 INTRQ_PENDING = 0 Read the Command or Status Task File register CMD_INTRQ_OK = 0 INTRQ_PENDING == 0 AND CMD_INTRQ_OK == 0 INTRQ_PENDING == 1 AND CMD_INTRQ_OK == 1 INTRQ_PENDING = 0 AND CMD_INTRQ_OK = 0 CMD_INTRQ_OK == 0 CMD_INTRQ_OK = 0 Byte_Transfered_Count!= 0 AND CBW.dCBWFlags == 0x80 Issue the DMA FLUSH command to the DMA Command register Set Transfer_Error flag INTRQ_PENDING == 0 AND CMD_INTRQ_OK == 0 ATAPI_Bytecount = 0 Stop Fig 20. Handling ATA_DATA_TRANSFER _4 Application note Rev. 04 21 December 2006 35 of 49

A Sector_Count = CBW.CDB[7] Endpt_FIFO = CBW.dCBWDataTransferLength Transfer Error == 1 Sector_Count!= 0 Prev_State = ATAPI_Read Phase CBW.Length!= 0 Byte Transfered Count = CBW.dCBWDataTransferLength Atapi_ByteCount = 512 CBW.dCBWDataTransferLength = CBW.dCBWDataTransferLength - 512 Interrupt Reason Task File register = 0 Atapi_ByteCount = CBW.dCBWDataTransferLength Interrupt Reason Task File register = CBW.CDB[8] Set Transfer_Done flag Sector Number Task File register = CBW.CDB[5] Byte count LSB Task File register = CBW.CDB[4] Byte count MSB Task File register = CBW.CDB[3] Stop Is master ATA drive Drive Select Task File register = SLAVE LBA_MODE CBW.CDB[2] Drive Select Task File register = MASTER LBA_MODE CBW.CDB[2] Command Status Task File register = ATA READ_DMA command Auto_PIO = 0 MDMA_Mode = 1 UDMA_Mode = 0 Handle ATA Data Transfer Sector_Count = Sector Count - 1 CBW.CDB[4] = CBW.CDB[4] + 1 Transfer_Done == 0 AND Transfer_Error == 0 Reset Transfer_Done flag CBW.dCBWDataTransferLength = Endpt_FIFO A Fig 21. Handling ATA_READ_10 _4 Application note Rev. 04 21 December 2006 36 of 49

Initialize the Endpoint Index register to the respective IN endpoint Buffer length LSB Task File register = 8 Buffer length MSB Task File register = 0 Write to the Data Port register 4 bytes of Drive_Setup.LBA[0-3]: 0x00, 0x00, 0x02, 0x00 Byte_Transfered_Count = CBW.dCBWDataTransferLength Stop Fig 22. Handling ATA READ CAPACITY _4 Application note Rev. 04 21 December 2006 37 of 49

Initialize the Endpoint Index register to the respective IN endpoint Buffer Length LSB Task File register = 12 Buffer Length MSB Task File register = 0 Write these values to Data Port register 0x00, 0x00, 0x00, 0x08, Drive_Setup.LBA[0-3], 0x00, 0x00,0x02, 0x00 Byte_Transfered_Count = 12 Prev_State = ATAPI_status phase Set Transfer_Error flag Stop Fig 23. Handling ATA READ_FORMAT_CAPACITIES Initialize the Endpoint Index register to the respective IN endpoint In the 8-bit mode, write to the LSB and then the MSB of the Data Port register Write these values to the Data Port register: 0x70, 0x00, Error_Code.SENSE_KEY, 0x00, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,Error_Code.ASC, Error_Code.ASCQ, 0x00, 0x00, 0x00, 0x00 Validate the buffer using the Control Function register bit VENDP Byte_Transfered_Count = CBW.dCBWDataTransferLength Stop Fig 24. Handling ATA REQUEST_SENSE _4 Application note Rev. 04 21 December 2006 38 of 49

Initialize the Endpoint Index register to the respective IN endpoint Write the following values to the Data Port register: 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 Validate the buffer BY using bit VENDP in the Control Function register Byte_Transfered_Count = CBW.dCBWDataTransferLength Stop Fig 25. Handling ATA MODE_SENSE_10 Error_Code.SENSE_KEY = 5 Error_Code.ASC = 0x24 Error_Code.ASCQ = 0 Set Error_Occur flag Prev_State = ATAPI_Cmd_Packet_Phase Byte_Transfered_Count = 0 Stop Fig 26. Handling ATA MODE_SENSE_06 _4 Application note Rev. 04 21 December 2006 39 of 49

Sector_Count = CBW.CDB[7] Endpt_FIFO = CBW.dCBWDataTransferLength Sector_Count!= 0 CBW.Length!= 0 A Atapi_ByteCount = 512 CBW.dCBWDataTransferLength = CBW.dCBWDataTransferLength - 512 Interrupt Reason Task File register = 0 Atapi_ByteCount = CBW.dCBWDataTransferLength Interrupt Reason Task File register = CBW.CDB[8] Set Transfer_Done flag Sector Number Task File register = CBW.CDB[5] Byte count LSB Task File register = CBW.CDB[4] Byte count MSB Task File register = CBW.CDB[3] Is master ATA drive Drive Select Task File register = SLAVE LBA_MODE CBW.CDB[2] Drive Select Task File register = MASTER LBA_MODE CBW.CDB[2] Command Status Task File register = ATA WRITE_DMA command Auto_PIO = 0 MDMA_Mode = 1 UDMA_Mode = 0 Handle ATA Data Transfer Sector_Count = Sector Count - 1 CBW.CDB[4] = CBW.CDB[4] + 1 Transfer_Done == 0 AND Transfer_Error == 0 A Reset Transfer_Done flag CBW.dCBWDataTransferLength = Endpt_FIFO Byte_Transfered_Count = CBW.dCBWDataTransferLength Stop Fig 27. Handling ATA WRITE_10 _4 Application note Rev. 04 21 December 2006 40 of 49

6. GDMA application The GDMA application supports GDMA slave and PIO modes. These modes are selected based on the vendor-specific command issued by the host. The host sends an 8-byte set-up packet, followed by 6-byte vendor-specific information. The number of bytes to be transferred, the direction of transfer, and the mode of transfer are embedded in the vendor-specific command. Format of set-up data USB_Device_Request.bmRequestType == vendor_specific (0xC0, 0x40, 0xA1, 0x21) USB_Device_Request.bRequest == 0x0C AND USB_Device_Request.bmRequestType == 0x40 Standard USB Request USB_Device_Request.wIndex == 0x7104 USB_Device_Request.wIndex == 0x7204 Handle the GDMA command Initialize the Endpoint Index register to 1 Stall the endpoint by setting bit STALL in the Control Function register EP0SETUP == 0 Reset bit EP0Tx in the copy of the Interrupt Reason register Handle the GDMA Stop command Bit EP0Tx is from a variable to which the Interrupt Enable register is copied in the interrupt routine Stop Fig 28. GDMA flowchart _4 Application note Rev. 04 21 December 2006 41 of 49

Initialize the Endpoint Index register to 0 Set bit DSEN in the Control Function register Wait for OUT token ACK EP0Rx == 0 Clear EP0Rx bit Initialize the Endpoint Index register to 0 Bit EP0Rx is from the variable to which the Interrupt Reason register is copied in the interrupt routine Read the 6-byte vendor-specific information from the Data Port register into variable FileSize Initialize the Endpoint Index register to 1 Set bit STATUS in the Control Function register FileSize.Size == 0 Reset Out_Reset_Done flag Reset IN_Reset_Done flag FileSize.DIR == 0x00 OR FileSize.DIR == 0x80 Handle PIO/GDMA Read Handle PIO/GDMA Write Stop Fig 29. Handling GDMA start command _4 Application note Rev. 04 21 December 2006 42 of 49

DMA_Test_Mode!= PIO Stop the CPLD DMA controller Reset the CPLD DMA controller Is master mode Initialize the CPLD DMA controller for Slave Read mode Initialize the CPLD DMA controller for Master Write mode Initialize the CPLD DMA counter to FileSize.SIze Set the CPLD DMA mode Initialize the DMA Endpoint register to the respective OUT endpoint Initialize the Endpoint Index register to a value not equal to the DMA Endpoint register Initialize the DMA transfer counter to FileSize.Size DMA_Test_Mode == GDMA Bits DMA_XFER_OK and INT_EOT are from the variable to which the DMA Interrupt Reason register is copied in the interrupt routine DMA_Test_Mode == MDMA Handle PIO_Write DMA command register = MDMA_Write command DMA_XFER_OK == 0 AND INT_EOT == 0 DMA command register = GDMA_Write command SUSP ==1 OR BUS_RESET ==1 OR EP0SETUP ==1 Bits SUSP and EP0SETUP are from the variable to which the Interrupt reason register is copied in the interrupt routine BUS_RESET is a flag Reset internal variable DMA_XFER_OK = 0 INT_EOT = 0 Write to the DMA command register with DMA_REST; reinitialize the DMA Stop Fig 30. Handling PIO or GDMA write _4 Application note Rev. 04 21 December 2006 43 of 49

DMA_Test_Mode!= PIO Stop the CPLD DMA controller Reset the CPLD DMA controller Is master mode Initialize the CPLD DMA controller for Slave Write mode Set CPLD DMA mode Initialize the CPLD DMA controller for Master Read mode Initialize the CPLD DMA counter to FileSize.SIze Initialize the DMA Endpoint register to the respective IN endpoint Initialize the Endpoint Index register to value not equal to the DMA Endpoint register Initialize the DMA transfer counter to FileSize.Size DMA_Test_Mode == GDMA DMA command register = GDMA_Read command Bit DMA_XFER_OK is from the variable to which the DMA Interrupt reason register is copied in the interrupt routine DMA_Test_Mode == MDMA DMA command register = MDMA_Read command Bits SUSP and EP0SETUP are from the variable to which the Interrupt reason register is copied in the interrupt routine Handle PIO_Read DMA_XFER_OK == 0 BUS_RESET is a flag SUSP ==1 OR BUS_RESET ==1 OR EP0SETUP ==1 Reset internal variable DMA_XFER_OK = 0 Write to the DMA command register with DMA_REST Reinitialize the DMA Stop Fig 31. Handling PIO or GDMA read _4 Application note Rev. 04 21 December 2006 44 of 49

A Enable CPLD PIO mode Issue the CPLD PIO Reset command This_buffer_remain = This_transfer_size Initialize the Endpoint Index register to the respective OUT endpoint This_buffer_remain C D Is the device full-speed PIO_maxpacket_size = 512 PIO_Bytes_Remaining = FileSize.Size PIO_maxpacket_size = 64 This_buffer_size = 64 This_buffer_remain - = 64 This_buffer_remain > 64 This_buffer_size = This_buffer_remain This_buffer_remain = 0 Count_PIO = 0 PIO_Bytes_Remaining!= 0 B Read the Data Port register LSB to the internal RAM Increment Count_PIO Read the Data Port register MSB to the internal RAM Increment Count_PIO PIO_Bytes_Remaining > PIO_MaxPaketSize This_tranfer_size = PIO_Bytes_remaining PIO_Bytes_Remaining = 0 Buffer Staus register == 0 A SUSP OR EP0SETUP OR BUS_RESET This_tranfer_size = PIO_MaxPacketSize PIO_Bytes_remaining - = PIO_MaxPacketSize BUS_RESET is a flag which is set on BUS_RESET interrupt Bits EP2Rx, SUSP and EP0SETUP are from the variable to which the Interrupt Reason register is copied in the interrupt routine D Count_PIO < this_buffer_size Count_PIO = 0 CPLD PIO Write LSB from the internal RAM Increment Count_PIO CPLD PIO Write MSB from the internal RAM Increment Count_PIO Count_PIO < this_buffer_size SUSP OR BUS_RESET B C Stop Fig 32. Handling PIO write _4 Application note Rev. 04 21 December 2006 45 of 49

Initialize the Endpoint Index register to the respective IN endpoint A Count_PIO = 0 Enable CPLD PIO mode Issue the CPLD PIO Reset command Is the device full-speed? PIO_maxpacket_size = 512 PIO_maxpacket_size = 64 CPLD PIO Read LSB to the internal RAM Increment Count_PIO CPLD PIO Read MSB to the internal RAM Increment Count_PIO Count_PIO < this_buffer_size PIO_Bytes_Remaining = FileSize.Size Count_PIO = 0 D PIO_Bytes_Remaining!= 0 B Write to the Data Port register LSB from the internal RAM Increment Count_PIO Write to the Data Port register MSB from the internal RAM Increment Count_PIO PIO_Bytes_Remaining > PIO_MaxPaketSize This_tranfer_size = PIO_Bytes_remaining PIO_Bytes_Remaining = 0 This_buffer_remain = This_transfer_size This_tranfer_size = PIO_MaxPacketSize PIO_Bytes_remaining - = PIO_MaxPacketSize Validate the buffer by setting bit VENDP in the Control Function register for short packet Count_PIO < this_buffer_size This_transfer_size < PIO_MaxPacketSize This_buffer_remain This_buffer_remain > 64 This_buffer_size = This_buffer_remain This_buffer_remain = 0 C This_buffer_size = 64 This_buffer_remain - = 64 Bits SUSP and EP0SETUP are from the variable into which the Interrupt Reason register is copied in the interrupt routine BUS_RESET is a flag which is set on the BUS_RESET interrupt C Wait if the Buffer Status register == 3 (exit on SUSP, BUS_RESET, EP0SETUP) SUSP OR BUS_RESET B D A Stop Fig 33. Handling PIO read _4 Application note Rev. 04 21 December 2006 46 of 49