ECEN 468 Advanced Logic Design

Similar documents
Arithmetic Operators There are two types of operators: binary and unary Binary operators:

Chap 6 - Introduction to HDL (b)

GO - OPERATORS. This tutorial will explain the arithmetic, relational, logical, bitwise, assignment and other operators one by one.

ECE Digital System Design & Synthesis Exercise 1 - Logic Values, Data Types & Operators - With Answers

ECE 4514 Digital Design II. Spring Lecture 7: Dataflow Modeling

Verilog Dataflow Modeling

14:332:231 DIGITAL LOGIC DESIGN. Hardware Description Languages

Introduction to Digital VLSI Design מבוא לתכנון VLSI ספרתי

Chapter 3: Dataflow Modeling

Course Topics - Outline

Basic operators, Arithmetic, Relational, Bitwise, Logical, Assignment, Conditional operators. JAVA Standard Edition

Lab 4: Arithmetic Logic Unit (ALU)

JAVA OPERATORS GENERAL

Lecture 3: Modeling in VHDL. EE 3610 Digital Systems

Lab 5: Arithmetic Logic Unit (ALU)


Design Using Verilog

Synthesis of Language Constructs. 5/10/04 & 5/13/04 Hardware Description Languages and Synthesis

Lecture #2: Verilog HDL

Lecture Topics. Announcements. Today: Integer Arithmetic (P&H ) Next: continued. Consulting hours. Introduction to Sim. Milestone #1 (due 1/26)

Introduction to Verilog. Garrison W. Greenwood, Ph.D, P.E.

Combinational Logic II

Java provides a rich set of operators to manipulate variables. We can divide all the Java operators into the following groups:

Digital Design with FPGAs. By Neeraj Kulkarni

A Verilog Primer. An Overview of Verilog for Digital Design and Simulation

Verilog HDL:Digital Design and Modeling. Chapter 4. Expressions

ESCI 386 IDL Programming for Advanced Earth Science Applications Lesson 1 IDL Operators

CS/COE 0447 Example Problems for Exam 2 Spring 2011

IT T35 Digital system desigm y - ii /s - iii

Lecture 1: VHDL Quick Start. Digital Systems Design. Fall 10, Dec 17 Lecture 1 1

Introduction To Verilog Design. Chun-Hung Chou

1. Prove that if you have tri-state buffers and inverters, you can build any combinational logic circuit. [4]

Experiment 7 Arithmetic Circuits Design and Implementation

Why Should I Learn This Language? VLSI HDL. Verilog-2

Operators. Java operators are classified into three categories:

Arithmetic Operations

Register Transfer Level in Verilog: Part I

Department of Computer Science

register:a group of binary cells suitable for holding binary information flip-flops + gates

Lecture 10: Combinational Circuits

Binary Adders: Half Adders and Full Adders

Le L c e t c ur u e e 2 To T p o i p c i s c t o o b e b e co c v o e v r e ed e Variables Operators

Chapter 4 Arithmetic Functions

Digital Design (VIMIAA01) Introduction to the Verilog HDL

EN2911X: Reconfigurable Computing Lecture 05: Verilog (2)

Contents. Appendix D Verilog Summary Page 1 of 16

Register Transfer Language and Microoperations (Part 2)

DLD VIDYA SAGAR P. potharajuvidyasagar.wordpress.com. Vignana Bharathi Institute of Technology UNIT 3 DLD P VIDYA SAGAR

Timing for Ripple Carry Adder

Chapter 3 Part 2 Combinational Logic Design

Operators & Expressions

Lecture 2: Data Types, Modeling Combinational Logic in Verilog HDL. Variables and Logic Value Set. Data Types. Why use an HDL?

In this lecture, we will go beyond the basic Verilog syntax and examine how flipflops and other clocked circuits are specified.

Verilog. Reminder: Lab #1 due tonight! Fall 2008 Lecture 3

How a Digital Binary Adder Operates

Department of Computer Science and Electrical Engineering. Intro to Verilog II

Combinational Logic Circuits

Introduction. Following are the types of operators: Unary requires a single operand Binary requires two operands Ternary requires three operands

ECEN 468 Advanced Digital System Design

EE 8351 Digital Logic Circuits Ms.J.Jayaudhaya, ASP/EEE

CSE140L: Components and Design Techniques for Digital Systems Lab. Verilog HDL. Instructor: Mohsen Imani UC San Diego. Source: Eric Crabill, Xilinx

Arithmetic and Logic Blocks

Digital Circuit Design and Language. Datapath Design. Chang, Ik Joon Kyunghee University

CMPE 415 Working with Operands and Variables Prof. Ryan Robucci

BUILDING BLOCKS OF A BASIC MICROPROCESSOR. Part 1 PowerPoint Format of Lecture 3 of Book

RUBY OPERATORS. Ruby Arithmetic Operators: Ruby Comparison Operators:

Lecture #21 March 31, 2004 Introduction to Gates and Circuits

Verilog. What is Verilog? VHDL vs. Verilog. Hardware description language: Two major languages. Many EDA tools support HDL-based design

Chapter 4. Operations on Data

1. Mark the correct statement(s)

Under-Graduate Project Logic Design with Behavioral Models

Computer Organization and Levels of Abstraction

Logic Design: Part 2

This Lecture. Some components (useful for the homework) Verilog HDL (will continue next lecture)

Parallel logic circuits

*Instruction Matters: Purdue Academic Course Transformation. Introduction to Digital System Design. Module 4 Arithmetic and Computer Logic Circuits

Chapter 3: part 3 Binary Subtraction

Topics. Computer Organization CS Exam 2 Review. Infix Notation. Reverse Polish Notation (RPN)

Chapter 3: Operators, Expressions and Type Conversion

EE292: Fundamentals of ECE

Prof. Navrati Saxena TA: Rochak Sachan

Lec-6-HW-3-ALUarithmetic-SOLN

Java provides a rich set of operators to manipulate variables. We can divide all the Java operators into the following g roups:

Operators in java Operator operands.

9/10/10. Arithmetic Operators. Today. Assigning floats to ints. Arithmetic Operators & Expressions. What do you think is the output?

Expression and Operator

Expressions and Precedence. Last updated 12/10/18

EN164: Design of Computing Systems Lecture 06: Lab Foundations / Verilog 2

Informatics Ingeniería en Electrónica y Automática Industrial

Verilog Tutorial. Introduction. T. A.: Hsueh-Yi Lin. 2008/3/12 VLSI Digital Signal Processing 2

Hardware description language (HDL)

Real Digital Problem Set #6

Computer Organization

Verilog HDL Introduction

Speaker: Kayting Adviser: Prof. An-Yeu Wu Date: 2009/11/23

GC03 Boolean Algebra

Verilog Module 1 Introduction and Combinational Logic

Verilog Design Principles

Von Neumann Architecture

CSE303 Logic Design II Laboratory 01

Transcription:

ECEN 468 Advanced Logic Design Lecture 26: Verilog Operators ECEN 468 Lecture 26

Operators Operator Number of Operands Result Arithmetic 2 Binary word Bitwise 2 Binary word Reduction 1 Bit Logical 2 Boolean value Relational 2 Boolean value Shift 1 Binary word Conditional 3 Expression ECEN 468 Lecture 26 2

Arithmetic Operators v 2 s complement representation v MSB is sign bit v For scalar and vector v For nets and registers Symbol Operator + Addition - Subtraction * Multiplication / Division % Modulus ECEN 468 Lecture 26 3

Bitwise Operators ~(101011) = 010100 (010101) & (001100) = 000100 (010101) ^ (001100) = 011001 Shorter word will extend to the size of longer word by padding bits with 0 Symbol Operator ~ Bitwise negation & Bitwise and Bitwise inclusive or ^ Bitwise exclusive or ~^, ^~ Bitwise exclusive nor ECEN 468 Lecture 26 4

Reduction Operators &(101011) = 0 (001100) = 1 Symbol & ~& Operator Reduction and Reduction nand v Unary operators v Return single-bit value Reduction or ~ Reduction nor ^ ~^, ^~ Reduction xor Reduction xnor ECEN 468 Lecture 26 5

Logical Operators v Case equality operators detect exact bit-by-bit match, including x or z v The logical equality operator is less restrictive, x is returned for any ambiguity v Verilog is loosely typed - OK to use A&&B when A and B are vectors o A&&B returns true if both words are non-zero integers v === can recognize x and z while == would return x for ambiguity Symbol Operator! Logical negation && Logical and Logical or == Logical equality!= Logical inequality === Case equality!== Case inequality ECEN 468 Lecture 26 6

Relational and Shift Operators Relational operators Shift operators < << <= >> > >= v Relational operators return x for ambiguity v 0xxx > 1xxx returns 1 if ( ( a < b ) && ( a >= c ) ) result = a << 3; ECEN 468 Lecture 26 7

Conditional Operator Y = ( A == B )? C : D; wire [1:0] select; wire [15:0] D1, D2, D3, D4; wire [15:0] bus = (select == 2 b00)? D1 : (select == 2 b01)? D2 : (select == 2 b10)? D3 : (select == 2 b11)? D4 : 16 bx? : 0 1 X 0 0 X X 1 X 1 X X X X X v z is not allowed in conditional_expression v If conditional_expression is ambiguous, both true_expression and false_expression are evaluated bitwisely according to the truth table to get the result ECEN 468 Lecture 26 8

Operands v A Verilog operand may be compose of o Nets o Registers o Constants o Numbers o Bit-select of a net or a register o Part-select of a net or a register o A function call o Concatenation of any of above ECEN 468 Lecture 26 9

Operator Precedence Operator precedence Highest Operator symbol -! ~ (unary) * / % + - (binary) << >> < <= > >= ==!= ===!== & ~& ^ ^~ ~^ ~ && Lowest? : Parentheses for precaution! ECEN 468 Lecture 26 10

Synthesis of Arithmetic Operators v If corresponding library cell exists, an operator will be directly mapped to it v Synthesis tool may select among different options in library cell, for example, when synthesize an adder o Small wordlength -> ripple-carry adder o Long wordlength -> carry-look-ahead adder o Need small area -> bit-serial adder v Implementation of * and / o May be inefficient when both operands are variables o If a multiplier or the divisor is a power of two, can be implemented through shift register ECEN 468 Lecture 26 11

Synthesis of Shift Operators v Synthesis tools normally support shifting by a constant number of bits v Cannot support a variable shift ECEN 468 Lecture 26 12

Relational Operators Relational operators ( <, >, >=, <= ) can be implemented through o Combinational logic o Adder/subtractor In bit-extended format Calculate A B, check extended bit of result 0 -> A >= B 1 -> A < B module compare ( lt, gt, eq, A, B ); input A, B; output lt, gt, eq; assign lt = ( A < B ); assign gt = ( A > B ); assign eq = ( A == B ); endmodule ECEN 468 Lecture 26 13

Synthesis of Identity Operators v The logical identity operators ( ==,!= ) and the case identity operators ( ===,!== ) are normally synthesized to combinational logic ECEN 468 Lecture 26 14

Reduction, Bitwise and Logical Operators v They are translated into a set of equivalent Boolean equations and synthesized into combinational logic ECEN 468 Lecture 26 15

Conditional Operator v The conditional operator (? : ) synthesizes into library muxes or gates that implement the functionality of a mux v The expression to the left of? is formed as control logic for the mux ECEN 468 Lecture 26 16

Concatenation Operator v Equivalent to a logical bus v No functionality of its own v Generally supported by synthesis tool ECEN 468 Lecture 26 17

Grouping of Operators module operator_group ( sum1, sum2, a, b, c, d ); input a, b, c, d; output sum1, sum2; assign sum1 = a + b + c + d; assign sum2 = ( a + b ) + ( c + d ); endmodule b a c adder adder adder d adder adder sum2 adder sum1 ECEN 468 Lecture 26 18

2024 © technodocbox.com Privacy Policy | Terms of Service | Feedback