16Mbit, 512KX32 CMOS S-RAM MODULE Features Access Times: 17 and 20ns Package Options: 66-Pin Ceramic PGA 1.080" SQ 66-Pin Ceramic PGA 1.173" SQ 68-Lead Ceramic QFP 0.88" SQ Fit & Function JEDEC 68-CQFJ or 68-PLCC Product Description Industrial and Military Screening User Configurable as 512Kx32, 1024Kx16, 2048Kx8 TTL Compatible Input/Output Single 5V (±10%) Power Data Retention (Low Power Version Only) The MES51232 is a 16 megabit High Speed Static Ram MCM. Each MCM is constructed from four 512KX8 SRam assembled in a multilayered cofired ceramic package, designed with power and ground planes for lower noise and better ground bounce. These MCMs are available in 17ns and 20ns versions. Low Power versions are also available. Block Diagram December, 2003 Rev. A 1 of 14
Pin Names Truth Table (H=VIH, L=VIL, X=Don't Care) Pin Name Pin Function OE# WE# CS# I/O Mode A0 A18 Address Inputs X X H Hi-Z Standby DQ0 DQ31 Data Inputs/Outputs L H L DOUT Read CS1# CS4# Chip Selects X L L DIN Write WE1# WE4# Write Enables H H L Hi-Z Out Disable OE# Output Enable GND Ground VCC Power (+5V ±10%) NC No Connection Note: # Symbol means "Active Low" Signal Pin Configuration for 66-Pin PGA (G7,G3) (Top View) A B C F G H 1 DQ8 WE2# DQ15 DQ24 VCC DQ31 2 DQ9 CS2# DQ14 DQ25 CS4# DQ30 3 DQ10 GND DQ13 DQ26 WE4# DQ29 4 A13 DQ11 DQ12 A6 DQ27 DQ28 5 A14 A10 OE# A7 A3 A0 6 A15 A11 A18 NC A4 A1 7 A16 A12 WE1# A8 A5 A2 8 A17 VCC DQ7 A9 WE3# DQ23 9 DQ0 CS1# DQ6 DQ16 CS3# DQ22 10 DQ1 NC DQ5 DQ17 GND DQ21 11 DQ2 DQ3 DQ4 DQ18 DQ19 DQ20 December, 2003 Rev. A 2 of 14
Pin Numbers & Functions MES51232XXXXX Pin # Function Pin # Function Pin # Function Pin # Function 1 GND 18 GND 35 OE# 52 GND 2 CS3# 19 DQ8 36 CS2# 53 DQ23 3 A5 20 DQ9 37 A17 54 DQ22 4 A4 21 DQ10 38 WE2# 55 DQ21 5 A3 22 DQ11 39 WE3# 56 DQ20 6 A2 23 DQ12 40 WE4# 57 DQ19 7 A1 24 DQ13 41 A18 58 DQ18 8 A0 25 DQ14 42 NC 59 DQ17 9 NC 26 DQ15 43 NC 60 DQ16 10 DQ0 27 VCC 44 DQ31 61 VCC 11 DQ1 28 A11 45 DQ30 62 A10 12 DQ2 29 A12 46 DQ29 63 A9 13 DQ3 30 A13 47 DQ28 64 A8 14 DQ4 31 A14 48 DQ27 65 A7 15 DQ5 32 A15 49 DQ26 66 A6 16 DQ6 33 A16 50 DQ25 67 WE1# 17 DQ7 34 CS1# 51 DQ24 68 CS4# Pin Configuration for 68-Lead CQFP (S) December, 2003 Rev. A 3 of 14
Absolute Maximum Ratings Item Supply Voltage Relative to GND Voltage on Any Pin Relative to GND Operating Temperature Storage Temperature Rating -0.5V to +7.0V -0.5V to VCC +0.5V -55 C to +125 C -65 C to +150 C Recommended Operating Conditions Parameter Symbol Min Max Unit Supply Voltage VCC 4.5 5.5 V Input High Voltage VIH 2.2 VCC +0.3 V Input Low Voltage VIL -0.5 +0.8 V Operating (Military) TA -55 +125 C Temperature (Industrial) -40 +85 C Capacitance (TA = +25 C, VIN = 0V, f = 1.0 MHz) Description Symbol Limits Unit Min Max OE# Capacitance COE 50 pf WE#1 to WE#4 Capacitance CWE 20 pf CS#1 to CS#4 Capacitance CCS 20 pf DQ0 to DQ31 Capacitance CI/O 20 pf A0 to A18 Capacitance CAD 50 pf These parameters are guaranteed, but not tested. December, 2003 Rev. A 4 of 14
DC Characteristics (Vcc = 5V) Parameter Symbol Min Max Units Input Leakage Current ILI (1) -10 10 µa Output Leakage Current ILO (2) -10 10 µa Output Low Voltage VOL (3) 0.4 V Output High Voltage VOH (4) 2.4 V Standby Supply Current ISB (5) 17ns 40 ma 20ns 40 Dynamic Operating Current ICC (6) 17ns 640 ma (32 bit operation mode) 20ns 640 Notes: (1) VCC = Max, VI/O = VCC to GND (2) VI/O = VCC to GND, CS# VIH, OE# VIH (3) VCC = Min, IOL = +8mA (4) VCC = Min, IOH = -4mA (5) CS # = VIH, OE # = VIH, VCC = Max, f = 5.0 MHz (6) VCC = Max, CS# = VIL, OE# = VIH, f = 5.0 MHz December, 2003 Rev. A 5 of 14
AC Characteristics Write Cycle Parameter Symbol 17ns 20ns Limits Units Write Cycle Time TAVAV 17 20 min ns Address Set-up Time TAVWL 0 0 min ns Address Valid to End of Write TAVWH 13 15 min ns Data Valid to End of Write TDVWH 10 15 min ns Chip Select Low to End of Write TELWH 13 15 min ns Write Pulse Width TWLWH 13 15 min ns Address Hold from Write End TWHAX 0 0 min ns Data Hold Time TWHDX 0 0 min ns Write Low to High Z TWLQZ * 10 10 max ns Output Active from End of Write TWHQX * 4 5 min ns Read Cycle Parameter Symbol 17ns 20ns Limits Units Read Cycle Time TAVAV 17 20 min ns Address Access Time TAVQV 17 20 max ns Output Hold from Address Change TAVQX 4 4 min ns Chip Select Access Time TELQV 17 20 max ns Output Enable to Output Valid TGLQV 10 10 max ns Chip Select to Output in Low Z TELQX* 4 4 min ns Chip Disable to Output in High Z TEHQZ* 10 10 max ns Output Enable to Output in Low Z TGLQX* 0 0 min ns Output Disable to Output in High Z TGHQZ* 8 8 max ns (*) - Parameter is guaranteed, but not tested. December, 2003 Rev. A 6 of 14
Timing Waveforms of Write Cycle December, 2003 Rev. A 7 of 14
Timing Waveforms of Read Cycle December, 2003 Rev. A 8 of 14
AC Test Conditions Item Conditions Input Pulse Levels GND to 3.0V Input Rise and Fall Times 5ns Input Timing Reference Level 1.5V Output Timing Reference Level 1.5V Output Load: 17ns to 70ns 1 TTL Load, CL=30pF 85ns and up 1 TTL Load, CL=100pF Note: For TWHQX, TWLQZ, TELQX, TEHQZ, TGLQX and TGHQZ CL = 5pF Data Retention Characteristics (Over Operating Temp Range) For Low Power Version Only (1) Test Conditions: GND = 0V, VCC = 3V, CE# VCC-0.2V, VIH VCC - 0.2V, VIL 0.2V. Characteristic Symbol Min Typ. Max Unit VCC for Data Retention VDR 2 V D.R Quiescent Current ICCDR 2000 (2) 8000 (1)(2) µa Chip Disable to D.R Time TCDR 0 nsec Operation Recovery Time TR TAVAV nsec (1) Contact Factory (2) Lower D.R Currents are available upon request Data Retention (CE# - Controlled) December, 2003 Rev. A 9 of 14
Outline Drawing for 66-Pin Ceramic PGA (G7) December, 2003 Rev. A 10 of 14
Outline Drawing for 66-Pin Ceramic PGA (G3) December, 2003 Rev. A 11 of 14
Outline Drawing for 68-Lead Ceramic QFP (S) December, 2003 Rev. A 12 of 14
Ordering Information (Standard Military Screened Products*) Model Number Speed Package MES51232G717M 17ns CPGA MES51232G720M 20ns CPGA MES51232G317M 17ns CPGA MES51232G320M 20ns CPGA MES51232S17M 17ns CQFP MES51232S20M 20ns CQFP (*) - Contact Elisra for additional designs December, 2003 Rev. A 13 of 14
Part Number Breakdown December, 2003 Rev. A 14 of 14