PSoC 63 with BLE TRM PSoC 6 MCU PSoC 63 with BLE Architecture Technical Reference Manual (TRM) Document No. 002-18176 Rev. *D October 4, 2017 Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 www.cypress.com
Copyrights Cypress Semiconductor Corporation, 2016-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ( Cypress ). This document, including any software or firmware included or referenced in this document ( Software ), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ( Unintended Uses ). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. 2 PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No. 002-18176 Rev. *D
Contents Overview Section A: Overview 19 1. Introduction... 21 2. Getting Started... 27 3. Document Construction... 29 Section B: CPU Subsystem 33 4. CPU Subsystem (CPUSS)... 35 5. Inter-Processor Communication... 43 6. Fault Monitoring... 47 7. Interrupts... 55 8. Protection Units... 69 9. DMA Controller... 79 10. Cryptographic Function Block (Crypto)... 87 11. Program and Debug Interface... 91 12. Nonvolatile Memory Programming... 101 13. efuse Memory... 117 14. Chip Operational Modes... 119 15. Device Security... 121 Section C: System Resources Subsystem (SRSS) 123 16. Power Supply and Monitoring... 125 17. Device Power Modes... 133 18. Backup System... 145 19. Clocking System... 153 20. Reset System... 169 21. I/O System... 173 22. Watchdog Timer... 195 23. Trigger Multiplexer Block... 205 24. Energy Profiler... 211 Section D: Digital Subsystem 219 25. Serial Communications Block (SCB)... 221 26. Serial Memory Interface (SMIF)... 267 27. Timer, Counter, and PWM... 283 28. Inter-IC Sound Bus... 317 29. PDM-PCM Converter... 329 PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No. 002-18176 Rev. *D 3
30. Universal Serial Bus (USB) Device Mode... 337 31. Universal Serial Bus (USB) Host... 355 32. LCD Direct Drive... 371 33. Universal Digital Blocks (UDB)... 383 Section E: Analog Subsystem 425 34. Analog Reference Block... 427 35. Low-Power Comparator... 429 36. Continuous Time Block mini (CTBm)... 435 37. Continuous Time DAC... 441 38. SAR ADC... 451 39. Temperature Sensor... 471 40. Analog Routing... 475 41. CapSense... 479 Section F: BLE Subsystem (BLESS) 481 42. Bluetooth Low Energy Subsystem (BLESS)... 483 4 PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No. 002-18176 Rev. *D
Contents Section A: Overview 19 Document Revision History...19 1. Introduction 21 1.1 Top Level Architecture...22 1.2 CPU Subsystem (CPUSS)...22 1.2.1 CPU...22 1.2.2 DMA Controllers...22 1.2.3 Flash...22 1.2.4 SRAM...22 1.2.5 SROM...22 1.2.6 OTP efuse...22 1.2.7 Program and Debug...22 1.3 System Resources Subsystem (SRSS)...23 1.3.1 Power System...23 1.3.2 Clocking System...23 1.3.3 GPIO...23 1.4 Analog Subsystem...24 1.4.1 12-bit SAR ADC...24 1.4.2 Temperature Sensor...24 1.4.3 12-bit Digital-to-Analog Converter...24 1.4.4 Continuous Time Block (CTBm)...24 1.4.5 Low-Power Comparators...24 1.4.6 CapSense...24 1.5 Programmable Digital...24 1.5.1 Smart I/O...24 1.5.2 Universal Digital Blocks (UDBs) and Port Interfaces...24 1.6 Digital Subsystem...25 1.6.1 Timer/Counter/PWM Block...25 1.6.2 Serial Communication Blocks (SCB)...25 1.6.3 Serial Memory Interface (SMIF)...25 1.6.4 Audio Subsystem...25 1.7 BLE Subsystem (BLESS)...25 2. Getting Started 27 2.1 Support...27 2.2 Product Upgrades...27 2.3 Development Kits...27 2.4 Application Notes...27 3. Document Construction 29 3.1 Major Sections...29 3.2 Documentation Conventions...29 PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No. 002-18176 Rev. *D 5
3.2.1 Register Conventions...29 3.2.2 Numeric Naming...29 3.2.3 Units of Measure...30 3.2.4 Acronyms...30 Section B: CPU Subsystem 33 Top Level Architecture...33 4. CPU Subsystem (CPUSS) 35 4.1 Features...35 4.2 Block Diagram...35 4.3 How It Works...36 4.4 Address and Memory Maps...36 4.5 Registers...37 4.6 Operating Modes and Privilege Levels...39 4.7 Instruction Set...40 4.8 Fault Reporting...40 5. Inter-Processor Communication 43 5.1 Features...43 5.1.1 IPC Channel...43 5.1.2 IPC Interrupt...44 5.1.3 IPC Channels and Interrupts...44 5.2 Implementing Locks...45 5.3 Message Passing...45 6. Fault Monitoring 47 6.1 Features...47 6.2 Block Diagram...47 6.3 How It Works...48 6.3.1 Fault Report...48 6.3.2 Signaling Interface...50 6.3.3 Monitoring...50 6.3.4 Low-power Mode Operation...51 6.3.5 Using a Fault Structure...51 6.3.6 CPU Exceptions Versus Fault Monitoring...51 6.4 Fault Sources...52 6.5 Register List...53 7. Interrupts 55 7.1 Features...55 7.2 How It Works...56 7.3 Interrupts and Exceptions - Operation...57 7.3.1 Interrupt/Exception Handling...57 7.3.2 Level and Pulse Interrupts...57 7.3.3 Exception Vector Table...58 7.4 Exception Sources...59 7.4.1 Reset Exception...59 7.4.2 Non-Maskable Interrupt Exception...59 7.4.3 HardFault Exception...59 7.4.4 Memory Management Fault Exception...60 7.4.5 Bus Fault Exception...60 7.4.6 Usage Fault Exception...60 7.4.7 Supervisor Call (SVCall) Exception...60 6 PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No. 002-18176 Rev. *D
7.4.8 PendSupervisory (PendSV) Exception...60 7.4.9 System Tick (SysTick) Exception...60 7.5 Interrupt Sources...61 7.6 Interrupt/Exception Priority...65 7.7 Enabling and Disabling Interrupts...65 7.8 Interrupt/Exception States...66 7.8.1 Pending Interrupts/Exceptions...66 7.9 Stack Usage for Interrupts/Exceptions...67 7.10 Interrupts and Low-Power Modes...67 7.11 Interrupt/Exception Initialization and Configuration...67 7.12 Registers...68 8. Protection Units 69 8.1 Bus Master Attributes...71 8.2 Protection Context...71 8.3 Protection Context 0...71 8.4 Protection Structure...72 8.4.1 Protection Violation...74 8.4.2 MPU...74 8.4.3 SMPU...75 8.4.4 PPU...75 8.4.5 Protection of Protection Structures...76 8.4.6 Protection Structure Types...76 9. DMA Controller 79 9.1 Description...79 9.2 Channels...80 9.3 Descriptors...81 9.3.1 Address Configuration...82 9.3.2 Transfer Size...84 9.3.3 Descriptor Chaining...84 9.4 DMA Controller...85 9.4.1 Trigger Selection...85 9.4.2 Pending Triggers...85 9.4.3 Output Triggers...85 9.4.4 Interrupts...85 9.4.5 DMA Performance...86 10. Cryptographic Function Block (Crypto) 87 10.1 Architecture...87 10.2 Definitions of Terms...88 10.3 Crypto Block Functions...89 10.3.1 Symmetric Key Functions...89 10.3.2 Hash Functions...89 10.3.3 Message Authentication Code (MAC) Functions...90 10.3.4 Cyclic Redundancy Code (CRC)...90 10.3.5 Random Number Generator (RNG)...90 10.4 Module Configuration and Initialization...90 11. Program and Debug Interface 91 11.1 Features...91 11.2 Functional Description...91 11.2.1 Debug Access Port (DAP)...93 11.2.2 ROM Tables...93 PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No. 002-18176 Rev. *D 7
11.2.3 Trace...93 11.2.4 Embedded Cross Triggering...94 11.3 Serial Wire Debug (SWD) Interface...94 11.3.1 SWD Timing Details...95 11.3.2 ACK Details...95 11.3.3 Turnaround (Trn) Period Details...96 11.4 JTAG Interface...96 11.5 Programming the PSoC 6 MCU...99 11.5.1 SWD Port Acquisition...99 11.5.2 SWD Programming Mode Entry...99 11.5.3 SWD Programming Routines Executions...99 11.6 Registers...99 12. Nonvolatile Memory Programming 101 12.1 Functional Description...101 12.2 System Call Implementation...102 12.2.1 System Call via CM0+ or CM4...102 12.2.2 System Call via DAP...102 12.2.3 Exiting from a System Call...102 12.3 SROM API Library...103 12.4 System Calls...103 12.4.1 Silicon ID...103 12.4.2 Blow Fuse Bit...105 12.4.3 Read Fuse Byte...106 12.4.4 Write Row...107 12.4.5 Program Row...108 12.4.6 Erase All... 110 12.4.7 Checksum... 111 12.4.8 Compute Hash... 112 12.4.9 Erase Sector... 113 12.4.10 Soft Reset... 113 12.4.11 Erase Row... 114 12.4.12 Erase Sub Sector... 115 12.5 System Call Status...116 13. efuse Memory 117 13.1 Features...117 13.2 Operating Principles...117 14. Chip Operational Modes 119 14.1 Boot...119 14.2 User...119 14.3 Trusted...119 14.4 Debug...120 15. Device Security 121 15.1 Features...121 15.2 How It Works...121 15.2.1 Life Cycle Stages and Protection States...121 15.2.2 Flash Security...122 15.2.3 Hardware-Based Encryption...122 Section C: System Resources Subsystem (SRSS) 123 Top Level Architecture...123 8 PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No. 002-18176 Rev. *D
16. Power Supply and Monitoring 125 16.1 Features...125 16.2 Block Diagram...126 16.3 How it Works...126 16.4 Power Supply...127 16.4.1 Regulators Summary...127 16.4.2 Power Pins and Rails...128 16.4.3 Power Sequencing Requirements...129 16.4.4 Backup Domain...129 16.4.5 Power Supply Sources...129 16.5 Voltage Monitoring...130 16.5.1 Power-On-Reset (POR)...130 16.5.2 Brownout-Detect (BOD)...130 16.5.3 Low-Voltage-Detect (LVD)...130 16.5.4 Over-Voltage Protection (OVP)...131 16.6 Register List...131 17. Device Power Modes 133 17.1 Features...133 17.2 Device Power Modes...134 17.2.1 Active and Sleep Modes...134 17.2.2 Low-Power Active/Sleep Modes...134 17.2.3 Deep-Sleep Mode...135 17.2.4 Hibernate Mode...135 17.2.5 Other Operation Modes...135 17.3 Power Mode Transitions...136 17.3.1 Power-up Transitions...138 17.3.2 Low-power Mode Transitions...139 17.3.3 Wakeup Transitions...141 17.4 Summary...142 17.5 Register List...143 18. Backup System 145 18.1 Features...145 18.2 Block Diagram...146 18.3 Power Supply...146 18.4 Clocking...147 18.4.1 WCO with External Clock/Sine Wave Input...147 18.4.2 Calibration...147 18.5 Reset...148 18.6 Real-Time Clock...148 18.6.1 Reading RTC User Registers...148 18.6.2 Writing to RTC User Registers...148 18.7 Alarm Feature...149 18.8 PMIC Control...150 18.9 Backup Registers...151 18.10 Register List...151 19. Clocking System 153 19.1 Block Diagram...153 19.2 Clock Sources...154 19.2.1 Internal Main Oscillator (IMO)...154 19.2.2 External Crystal Oscillator (ECO)...154 PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No. 002-18176 Rev. *D 9
19.2.3 External Clock (EXTCLK)...155 19.2.4 Alternate High-Frequency Clock (ALTHF)...155 19.2.5 Internal Low-speed Oscillator (ILO)...155 19.2.6 Precision Internal Low-speed Oscillator (PILO)...155 19.2.7 Watch Crystal Oscillator (WCO)...156 19.3 Clock Generation...156 19.3.1 Phase-Locked Loop (PLL)...156 19.3.2 Frequency Lock Loop (FLL)...156 19.4 Clock Trees...162 19.4.1 Path Clocks...162 19.4.2 High-Frequency Root Clocks...162 19.4.3 Low-Frequency Clock...162 19.4.4 Timer Clock...163 19.4.5 CTBm Alternate Pump Clock...163 19.4.6 Group Clocks (clk_sys)...163 19.5 CLK_HF[0] Distribution...164 19.5.1 CLK_FAST...164 19.5.2 CLK_PERI...164 19.5.3 CLK_SLOW...164 19.6 Peripheral Clock Dividers...164 19.6.1 Fractional Clock Dividers...164 19.6.2 Peripheral Clock Divider Configuration...164 19.7 Clock Calibration Counters...167 20. Reset System 169 20.1 Reset Sources...169 20.1.1 Power-on Reset...169 20.1.2 Brownout Reset...169 20.1.3 Watchdog Timer Reset...170 20.1.4 Software Initiated Reset...170 20.1.5 External Reset...170 20.1.6 Logic Protection Fault Reset...170 20.1.7 Clock-Supervision Logic Reset...170 20.1.8 Hibernate Wakeup Reset...170 20.2 Identifying Reset Sources...170 20.3 Register List...171 21. I/O System 173 21.1 Features...173 21.2 GPIO Interface Overview...173 21.3 I/O Cell Architecture...175 21.3.1 Digital Input Buffer...175 21.3.2 Digital Output Driver...176 21.4 High-Speed I/O Matrix...179 21.5 I/O State on Power Up...180 21.6 Behavior in Low-Power Modes...181 21.7 Input and Output Synchronization...181 21.8 Interrupt...181 21.9 Peripheral Connections...183 21.9.1 Firmware-Controlled GPIO...183 21.9.2 Analog I/O...183 21.9.3 LCD Drive...183 21.9.4 CapSense...183 10 PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No. 002-18176 Rev. *D
21.9.5 Serial Communication Block (SCB)...183 21.10 Smart I/O...184 21.10.1 Overview...184 21.10.2 Block Components...184 21.10.3 Routing...192 21.10.4 Operation...192 21.11 Registers...194 22. Watchdog Timer 195 22.1 Features...195 22.2 Block Diagram...195 22.3 Free-running WDT...196 22.3.1 Overview...196 22.3.2 Watchdog Reset...197 22.3.3 Watchdog Interrupt...198 22.4 Multi-Counter WDTs...198 22.4.1 Overview...198 22.4.2 How it Works...199 22.4.3 Enabling and Disabling WDT...202 22.4.4 Watchdog Cascade Options...203 22.4.5 Watchdog Reset...203 22.4.6 Watchdog Interrupt...203 22.5 Reset Cause Detection...204 22.6 Register List...204 23. Trigger Multiplexer Block 205 23.1 Features...205 23.2 Description...205 23.3 Trigger Multiplexer Architecture...206 23.3.1 Trigger Multiplexer Group...206 23.3.2 Trigger Multiplexer Block Architecture...206 23.3.3 Trigger Multiplexer Routing...207 23.3.4 Software Triggers...207 23.4 PSoC 6 MCU Trigger Multiplexer Block...208 23.5 Register List...210 24. Energy Profiler 211 24.1 Features...211 24.2 Block Diagram...212 24.3 Profiler Design...212 24.4 Available Monitoring Sources...213 24.5 Counter Value Weighting (Energy Coefficients)...213 24.6 Reference Clocks...214 24.7 Using the Profiler...214 24.7.1 Enable or Disable the Profiler...215 24.7.2 Configure and Enable a Counter...215 24.7.3 Start and Stop Profiling...216 24.7.4 Handle Counter Overflow...216 24.7.5 Get the Results...216 24.7.6 Exit Gracefully...217 Section D: Digital Subsystem 219 Top Level Architecture...219 PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No. 002-18176 Rev. *D 11
25. Serial Communications Block (SCB) 221 25.1 Features...221 25.2 Operation Modes...221 25.2.1 Buffer Modes...221 25.2.2 Clocking Modes...222 25.3 Serial Peripheral Interface (SPI)...223 25.3.1 Features...223 25.3.2 General Description...223 25.3.3 SPI Modes of Operation...224 25.3.4 SPI Buffer Modes...228 25.3.5 Clocking and Oversampling...233 25.3.6 Enabling and Initializing SPI...235 25.3.7 I/O Pad Connection...236 25.3.8 SPI Registers...238 25.4 UART...239 25.4.1 Features...239 25.4.2 General Description...239 25.4.3 UART Modes of Operation...239 25.4.4 Clocking and Oversampling...249 25.4.5 Enabling and Initializing UART...249 25.4.6 I/O Pad Connection...250 25.4.7 UART Registers...252 25.5 Inter Integrated Circuit (I2C)...253 25.5.1 Features...253 25.5.2 General Description...253 25.5.3 Terms and Definitions...254 25.5.4 I2C Modes of Operation...254 25.5.5 I2C Buffer Modes...256 25.5.6 Clocking and Oversampling...259 25.5.7 Enabling and Initializing the I2C...262 25.5.8 I/O Pad Connections...263 25.5.9 I2C Registers...263 25.6 SCB Interrupts...264 25.6.1 SPI Interrupts...265 25.6.2 UART Interrupts...265 25.6.3 I2C Interrupts...266 26. Serial Memory Interface (SMIF) 267 26.1 Block Diagram...267 26.1.1 TX and RX FIFOs...269 26.1.2 MMIO Mode...270 26.1.3 XIP Mode...270 26.1.4 Cache...271 26.1.5 Arbitration...271 26.1.6 Cryptography...271 26.2 Memory Device Signal Interface...273 26.2.1 Specifying Memory Devices...273 26.2.2 Connecting SPI Memory Devices...273 26.2.3 SPI Data Transfer...278 26.2.4 Example of Setting up SMIF...280 26.3 Triggers...282 26.4 Interrupts...282 12 PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No. 002-18176 Rev. *D
27. Timer, Counter, and PWM 283 27.1 Features...283 27.2 Block Diagram...284 27.2.1 Enabling and Disabling Counters in TCPWM Block...284 27.2.2 Clocking...284 27.2.3 Trigger Inputs...285 27.2.4 Trigger Outputs...286 27.2.5 Interrupts...286 27.2.6 PWM Outputs...286 27.2.7 Power Modes...287 27.3 Operation Modes...288 27.3.1 Timer Mode...289 27.3.2 Capture Mode...295 27.3.3 Quadrature Decoder Mode...298 27.3.4 Pulse Width Modulation Mode...301 27.3.5 Pulse Width Modulation with Dead Time Mode...311 27.3.6 Pulse Width Modulation Pseudo-Random Mode (PWM_PR)...313 27.4 TCPWM Registers...316 28. Inter-IC Sound Bus 317 28.1 Features...317 28.2 Block Diagram...317 28.3 Digital Audio Interface Formats...318 28.3.1 Standard I2S Format...318 28.3.2 Left Justified (LJ) Format...320 28.3.3 Time Division Multiplexed (TDM) Format...320 28.4 Clocking Polarity and Delay Options...321 28.5 Interfacing with Audio Codecs...322 28.6 Clocking Features...322 28.7 FIFO Buffer and DMA Support...324 28.8 Interrupt Support...326 28.9 Watchdog Timer...327 29. PDM-PCM Converter 329 29.1 Features...329 29.2 Block Diagram...329 29.3 PDM-PCM Converter Features...330 29.3.1 Enable/Disable Converter...330 29.3.2 Clocking Features...330 29.3.3 Over-Sampling Ratio...330 29.3.4 Mono/Stereo Microphone Support...331 29.3.5 Hardware FIFO Buffers and DMA Controller Support...332 29.3.6 Interrupt Support...333 29.3.7 Digital Volume Gain...334 29.3.8 Smooth Gain Transition...334 29.3.9 Soft Mute...334 29.3.10 Word Length and Sign Bit Extension...335 29.3.11 High-Pass Filter...335 29.3.12 Enable/Disable Streaming...335 29.3.13 Power Modes...335 29.4 Operating Procedure...335 29.4.1 Initial Configuration...335 29.4.2 Interrupt Service Routine (ISR) Configuration...335 PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No. 002-18176 Rev. *D 13
29.4.3 Enabling / Disabling Streaming...336 30. Universal Serial Bus (USB) Device Mode 337 30.1 Features...337 30.2 Block Diagram...338 30.2.1 USB Physical Layer (USB PHY)...338 30.2.2 Serial Interface Engine (SIE)...338 30.2.3 Arbiter...338 30.3 How it Works...339 30.3.1 Functions of USB PHY...339 30.3.2 Endpoints...340 30.3.3 Transfer Types...340 30.3.4 Interrupt Sources...340 30.3.5 DMA Support...343 30.4 Logical Transfer Modes...343 30.4.1 Manual Memory Management with No DMA Access...345 30.4.2 Manual Memory Management with DMA Access...346 30.4.3 Automatic DMA Mode...347 30.4.4 Control Endpoint Logical Transfer...349 30.5 USB Power Modes...351 30.6 USB Device Registers...352 31. Universal Serial Bus (USB) Host 355 31.1 Features...355 31.2 Block Diagram...355 31.2.1 USB Physical Layer (USB PHY)...356 31.2.2 Clock Control Block...356 31.2.3 Interrupt Control Block...356 31.2.4 Endpoint n (n=1, 2)...356 31.2.5 DREQ Control...356 31.3 USB Host Operations...356 31.3.1 Detecting Device Connection...356 31.3.2 Obtaining Transfer Speed of the USB Device...356 31.3.3 USB Bus Reset...357 31.3.4 USB Packets...358 31.3.5 Retry Function...362 31.3.6 Error Status...362 31.3.7 End of Packet (EOP)...363 31.3.8 Interrupt Sources...363 31.3.9 DMA Transfer Function...364 31.3.10 Suspend and Resume Operations...368 31.3.11 Device Disconnection...369 31.4 USB Host Registers...370 32. LCD Direct Drive 371 32.1 Features...371 32.2 LCD Segment Drive Overview...371 32.2.1 Drive Modes...372 32.2.2 Recommended Usage of Drive Modes...380 32.2.3 Digital Contrast Control...380 32.3 Block Diagram...381 32.3.1 How it Works...381 32.3.2 High-Speed and Low-Speed Master Generators...381 14 PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No. 002-18176 Rev. *D
32.3.3 Multiplexer and LCD Pin Logic...382 32.3.4 Display Data Registers...382 32.4 Register List...382 33. Universal Digital Blocks (UDB) 383 33.1 Features...383 33.2 How It Works...384 33.2.1 PLDs...384 33.2.2 Datapath...386 33.2.3 Status and Control Module...405 33.2.4 Reset and Clock Control Module...412 33.2.5 UDB Addressing...419 33.2.6 System Bus Access Coherency...420 33.3 Port Adapter Block...421 33.3.1 PA Data Input Logic...421 33.3.2 PA Port Pin Clock Multiplexer Logic...422 33.3.3 PA Data Output Logic...422 33.3.4 PA Output Enable Logic...423 33.3.5 PA Clock Multiplexer...424 33.3.6 PA Reset Multiplexer...424 Section E: Analog Subsystem 425 Top Level Architecture...425 34. Analog Reference Block 427 34.1 Features...427 34.2 Architecture...427 34.2.1 Bandgap Reference Block...428 34.2.2 Zero Dependency To Absolute Temperature Current Generator (IZTAT)...428 34.2.3 Reference Selection Multiplexers...428 34.2.4 Startup Modes...428 34.2.5 Low-Power Modes...428 34.3 Registers...428 35. Low-Power Comparator 429 35.1 Features...429 35.2 Block Diagram...429 35.3 How It Works...430 35.3.1 Input Configuration...430 35.3.2 Output and Interrupt Configuration...430 35.3.3 Power Mode and Speed Configuration...431 35.3.4 Hysteresis...432 35.3.5 Wakeup from Low-Power Modes...432 35.3.6 Comparator Clock...433 35.4 Register Summary...433 36. Continuous Time Block mini (CTBm) 435 36.1 Features...435 36.2 Block Diagram...435 36.3 How It Works...436 36.3.1 Power Mode and Output Strength Configuration...436 36.3.2 Compensation...437 36.3.3 Switching Matrix...438 36.3.4 Sample and Hold...438 PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No. 002-18176 Rev. *D 15
36.3.5 Comparator Mode...439 36.3.6 Deep-Sleep Operation...439 36.4 Register Summary...440 37. Continuous Time DAC 441 37.1 Features...441 37.2 Block Diagram...442 37.3 How it Works...442 37.3.1 CTDAC Core...443 37.3.2 CTDAC Control Interface...447 37.3.3 Using CTDAC...448 37.4 Register List...449 38. SAR ADC 451 38.1 Features...451 38.2 Block Diagram...452 38.3 How it Works...452 38.3.1 SAR ADC Core...452 38.3.2 SARMUX...456 38.3.3 SARREF...462 38.3.4 SARSEQ...463 38.3.5 SAR Interrupts...466 38.3.6 Trigger...467 38.3.7 SAR ADC Status...468 38.4 Registers...469 39. Temperature Sensor 471 39.1 Features...471 39.2 How it Works...471 39.3 Temperature Sensor Configuration...473 39.4 Algorithm...473 39.5 Registers...473 40. Analog Routing 475 40.1 Features...475 40.2 Block Diagram...475 40.3 How It Works...476 40.3.1 AMUBUS Splitting...476 40.4 Register Summary...477 41. CapSense 479 Section F: BLE Subsystem (BLESS) 481 42. Bluetooth Low Energy Subsystem (BLESS) 483 42.1 Features...483 42.2 Block Diagram...483 42.3 How it Works...484 42.3.1 Link Layer Controller...484 42.3.2 Clocks...485 42.3.3 Power States...485 42.3.4 Bluetooth LE 4.2 Feature Data Length Extension486 42.3.5 Bluetooth LE 4.2 Feature Privacy 1.2486 16 PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No. 002-18176 Rev. *D
42.3.6 Multiple Connections...486 42.3.7 External PA/LNA Support...488 42.4 Register Details...489 PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No. 002-18176 Rev. *D 17
18 PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No. 002-18176 Rev. *D
Section A: Overview This section encompasses the following chapters: Introduction chapter on page 21 Getting Started chapter on page 27 Document Construction chapter on page 29 Document Revision History Revision Issue Date Origin of Change Description of Change *C August 18, 2017 NIDH Initial version for public release *D October 04, 2017 NIDH Updated CTDAC chapter diagrams. Minor update to the Backup System and USB Device Mode chapters PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No. 002-18176 Rev. *D 19
20 PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No. 002-18176 Rev. *D
1. Introduction PSoC is a scalable and reconfigurable platform architecture that supports a family of programmable embedded system controllers with ARM Cortex CPUs (single and multi-core). The PSoC 63 with BLE product family is a combination of a dual-core microcontroller with a Bluetooth Low Energy (Bluetooth Smart) subsystem in a single package. It incorporates integrated low-power flash technology, digital programmable logic, high-performance analog-to-digital and digital-to-analog conversion, low-power comparators, touch sensing, serial memory interface with encryption, and standard communication and timing peripherals. PSoC 6 MCUs have these characteristics: 32-bit dual core (ARM Cortex-M4 and ARM Cortex M0+) CPU subsystem Integrated (on-chip) flash memory Bluetooth Smart BT 4.2 subsystem Audio subsystem with I 2 S interface and two PDM channels Serial memory interface with on-the-fly encryption and decryption Low-power operation 1.7 V to 3.6 V Configurable digital blocks Programmable digital logic High-performance analog system Flexible and programmable interconnect Capacitive touch sensing (CapSense ) Energy profiler for software energy profiling and optimizing energy consumption Programmable GPIOs This document describes each function block of the PSoC 63 with BLE device in detail. In this document, PSoC 6 MCU refers to PSoC 63 with BLE unless explicitly mentioned otherwise. PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No. 002-18176 Rev. *D 21
Introduction 1.1 Top Level Architecture Figure 1-1 shows the major components of the PSoC 63 with BLE architecture. There are five major subsystems: CPU subsystem, BLE subsystem, system resources, peripheral blocks, and I/O subsystem. CPU Subsystem Figure 1-1. PSoC 6 MCU Architecture Block Diagram System Resources Power Sleep Control POR BOD OVP LVD REF SWJ/ETM/ITM/CTI Cortex M4 FPU, NVIC, MPU, BB Cache FLASH FLASH Controller SRAM SRAM Controller ROM ROM Controller SWJ/MTB/CTI Cortex M0+ MUL, NVIC, MPU Cache DMA Initiator/MMIO System Interconnect (Multi Layer AHB, MPU/SMPU, IPC) CRYPTO DES/TDES, AES,SHA,CRC, TRNG,RSA/ECC Accelerator Initiator/MMIO PWRSYS-LP/ULP Buck Clock Clock Control ILO WDT IMO ECO FLL CSV PLL Reset Reset Control XRES Backup Backup Control BREG RTC WCO IOSS GPIO PCLK SAR ADC (12-bit) SARMUX Programmable Analog DAC (12-bit) CTBm Programmable Digital UDB... UDB Peripheral Interconnect (MMIO, PPU) LP Comparator CapSense TCPWM (TIMER,CTR,QD, PWM) Serial Comm (SCB) (I2C,SPI,UART,LIN,SMC) Port Interface & Digital System Interconnect (DSI) Serial Comm (SCB) (I2C,SPI, Deep Sleep) LCD Audio Subsystem I2S Master/Slave PDM/PCM Bluetooth Low Energy Subsystem BLE 4.2 Programmable Link Layer Digital Interface BLE 2 Mbps Radio Energy Profiler EFUSE Serial Memory I/F (QSPI with OTF Encryption/Decryption)) DMA MMIO USB-FS Host + Device Power Modes Active/Sleep LowePowerActive/Sleep DeepSleep Hibernate Backup IO Subsystem High Speed I/O Matrix, Smart I/O, Boundary Scan GPIO FS/LS PHY The block diagram shows the device subsystems and gives a simplified view of their interconnections. The color-code shows the lowest power mode where the particular block is still functional (for example, LP comparator is functional in Deep-Sleep mode). 1.2 CPU Subsystem (CPUSS) 1.2.1 CPU The CPU subsystem in PSoC 6 MCUs consists of two ARM Cortex cores and their associated buses and memories: M4 with floating-point unit and memory protection units (FPU and MPU) and M0+ with an MPU. The Cortex M0+ provides a secure, uninterruptible boot function. This guarantees that post-boot, system integrity is checked and privileges enforced. Shared resources can be accessed through the normal ARM multi-layer bus arbitration. Exclusive accesses are supported by an inter-processor communication (IPC) scheme, which implements hardware semaphores and protection. 1.2.2 DMA Controllers PSoC 6 MCUs have DMA controllers that support independent access to peripherals using the AHB multilayer bus. 1.2.3 Flash PSoC 6 MCUs have a flash module with one block that can be used for EEPROM emulation for longer retention. It also has a block of flash that can be securely locked and is accessible only via a key lock that cannot be changed (onetime programmable). The flash block supports Read-While- Write (RWW) operation so that flash updates may be performed while the CPU is active. 1.2.4 SRAM PSoC 6 MCUs have an SRAM module, which can be retained in Deep-Sleep mode either fully or in increments of user-designated blocks. 1.2.5 SROM PSoC 6 MCUs have a supervisory ROM that contains boot and configuration routines. This ROM guarantees secure boot if authentication of user flash is required. 1.2.6 OTP efuse The OTP memory can provide a unique and unalterable identifier on a per-chip basis. This unalterable key can be used to access the secured flash. 1.2.7 Program and Debug PSoC 6 MCUs have extensive support for programming, testing, debugging, and tracing both hardware and firmware. Complete debug-on-chip functionality enables full device debugging in the final system using the standard production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the standard programming connections are required to fully support 22 PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No. 002-18176 Rev. *D
Introduction debug. The PSoC Creator integrated development environment (IDE) provides fully-integrated programming and debug support for PSoC 6 MCUs. The SWJ (SWD and JTAG) interface is fully compatible with industry-standard third-party probes. With the ability to disable debug features, with robust flash protection, and by allowing customerproprietary functionality to be implemented in on-chip programmable blocks, the PSoC 6 MCU family provides a high level of security. Additionally, all device interfaces can be permanently disabled (device security) for applications concerned about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and interrupting flash programming sequences. All programming, debug, and test interfaces are disabled when maximum device security is enabled. 1.3 System Resources Subsystem (SRSS) 1.3.1 Power System The power system confirms that voltage levels meet the requirements for the respective mode and will either delay mode entry (on power-on reset, for example) until voltage levels meet requirements or generate resets (brownout detect) when the power supply drops below specified levels. The design guarantees safe chip operation between power supply voltage dropping below specified levels and the reset. There are no voltage sequencing requirements. The VDD core logic supply feeds an on-chip LDO, which produces the core logic supply. In addition, the device includes an on-chip buck regulator that can be used to power the core. 1.3.2 Clocking System The PSoC 6 MCU clock system provides clocks to subsystems that require clocks and switches between different clock sources without glitches. In addition, the clock system ensures that no metastable conditions occur. The clock system for PSoC 6 MCU consists of the internal main oscillator (IMO), the internal low-speed oscillator (ILO), the precision internal low-speed oscillator (PILO), the external crystal oscillator, and the watch crystal oscillator (WCO). One phase-locked loop (PLL) and one frequency-locked loop (FLL) are used to generate high-speed clocks from either the IMO or the crystal oscillator or from an external clock supplied from a pin. The PLL and FLL enable independent clock frequencies for peripherals. Clocks may be buffered and brought out to a pin on a smart I/O port. 1.3.2.1 IMO Clock Source The IMO is the primary source of internal clocking in the PSoC 6 MCU. It is trimmed during testing to achieve the specified accuracy. The IMO may be locked to a more accurate clock source to obtain higher accuracy. 1.3.2.2 ILO Clock Source The ILO is a very low-power oscillator, which may be used to generate clocks for peripheral operation in Deep-Sleep mode. ILO-driven counters can be calibrated to the IMO to improve accuracy. Cypress provides a software component, which does the calibration. 1.3.2.3 Watchdog Timer A watchdog timer is implemented in the clock block running from the ILO. This allows watchdog operation during deep sleep and hibernate, and generates a watchdog reset if not serviced before the timeout occurs. The watchdog reset is recorded in the Reset Cause register. 1.3.2.4 Clock Dividers Integer and fractional clock dividers are provided for peripheral use and timing purposes. The clock dividers are 16 and 24 bits in length to allow very fine clock control. 1.3.2.5 Reset PSoC 6 MCUs can be reset from a variety of sources including a software reset. Reset events are asynchronous and guarantee reversion to a known state. The reset cause is recorded in a register, which allows the software to determine the cause of the reset. An XRES pin is reserved for external reset to avoid complications with configuration and multiple pin functions during power-on or reconfiguration. 1.3.3 GPIO The GPIO pins are organized in logical entities called ports, which are eight bits in width. During power-on and reset, the blocks are forced to the disable state so as not to crowbar any inputs and/or cause excess turn-on current. A multiplexing network known as a high-speed I/O matrix (HSIOM) is used to multiplex between various signals that may connect to an I/O pin. Data output and pin state registers store, respectively, the values to be driven on the pins and the states of the pins themselves. Every I/O pin can generate an interrupt if so enabled and each I/O port has an interrupt request (IRQ) and interrupt service routine (ISR) vector associated with it. Four GPIO pins are capable of overvoltage tolerant (OVT) operation where the input voltage may be higher than VDD (these may be used for I 2 C functionality to allow powering the chip off while maintaining physical connection to an operating I 2 C bus without affecting its functionality). GPIO pins can be ganged to sink 16 ma or higher values of sink current. GPIO pins may not be pulled up higher than 3.6 V. PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No. 002-18176 Rev. *D 23
Introduction 1.4 Analog Subsystem 1.4.1 12-bit SAR ADC PSoC 6 MCUs have a 12-bit SAR ADC. The SAR is connected to a fixed set of pins through an eight-input sequencer. The sequencer cycles through the selected channels autonomously (sequencer scan) and does so with zero switching overhead (that is, the aggregate sampling bandwidth remains the same whether it is for a single channel or distributed over several channels). The sequencer switching is effected through a state machine or through firmware-driven switching. The sequencer supports the buffering of each channel to reduce CPU interruptservice requirements. To accommodate signals with varying source impedances and frequencies, different sample times can be programmed for each channel. Also, the signal range specification through a pair of range registers (low- and high-range values) is implemented with a corresponding out-of-range interrupt if the digitized value exceeds the programmed range; this allows fast detection of out-of-range values without having to wait for a sequencer scan to be completed and the CPU to read the values and check for out-of-range values in software. The SAR is able to digitize the output of the on-chip temperature sensor for calibration and other temperaturedependent functions. The SAR is not available in Deep- Sleep and Hibernate modes because it requires a highspeed clock. 1.4.2 Temperature Sensor The PSoC 6 MCU has an on-chip temperature sensor. This consists of a diode, which is biased by a current source that can be disabled to save power. The temperature sensor is connected to the ADC, which digitizes the reading and produces a temperature value by using a Cypress-supplied software that includes calibration and linearization. 1.4.3 12-bit Digital-to-Analog Converter The PSoC 6 MCU has a 12-bit voltage mode DAC, which may be driven by the DMA controllers to generate userdefined waveforms. The DAC output from the chip can either be the resistive ladder output (highly linear near ground) or a buffered output. 1.4.4 Continuous Time Block (CTBm) This block consists of two opamps, which have their inputs and outputs connected to fixed pins and have three power modes and a comparator mode. The outputs of these opamps can be used as buffers for the SAR inputs. The noninverting inputs of these opamps can be connected to either of two pins, thus allowing independent sensors to be used at different times. The pin selection can be made via firmware. The opamps can be set to one of the four power levels; the lowest level allowing operation in Deep-Sleep mode to preserve low performance continuous-time functionality in Deep-Sleep mode. The DAC output can be buffered through an opamp. 1.4.5 Low-Power Comparators PSoC 6 MCUs have a pair of low-power comparators, which can operate in Deep-Sleep and Hibernate modes. This allows the analog system blocks to be disabled while retaining the ability to monitor external voltage levels in Deep-Sleep and Hibernate modes. The comparator outputs are normally synchronized to avoid metastability unless operating in an asynchronous power mode (Hibernate) where the system wake-up circuit is activated by a comparator-switch event. 1.4.6 CapSense The CapSense system, used primarily for touch sensing, can measure the self-capacitance of an electrode or the mutual capacitance between a pair of electrodes. CapSense provides industry's best-in-class signal-to-noise ratio (SNR), high touch sensitivity, low-power operation, and superior EMI performance. CapSense touch sensing also supports liquid-tolerant operation using a driven shield signal. Any analog-capable GPIO can be used as a sensor or shield electrode. In addition to capacitive sensing, the CapSense system can function as an ADC to measure voltage on any GPIO pin that supports the CapSense functionality. Moreover, If the CapSense block is not used for touch sensing or ADC functionality, a CapSense comparator and the two 8-bit IDACs can be used as general-purpose analog blocks. 1.5 Programmable Digital 1.5.1 Smart I/O The PSoC 6 MCU has two smart I/O blocks, which allow Boolean operations on signals going to the GPIO pins from the device subsystems or on signals coming into the device. Operation can be synchronous or asynchronous and the blocks operate in low-power modes, such as Deep-Sleep and Hibernate. This allows, for example, detection of logic conditions that can indicate that the CPU should wake up instead of waking up on general I/O interrupts, which consume more power and can generate spurious wakeups. 1.5.2 Universal Digital Blocks (UDBs) and Port Interfaces The PSoC 6 MCU supports custom programmable digital functions using UDBs, which also provide a switched digital system interconnect (DSI) fabric that allows signals from 24 PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No. 002-18176 Rev. *D
Introduction peripherals and ports to be routed to and through the UDBs for communication and control. 1.6 Digital Subsystem 1.6.1 Timer/Counter/PWM Block The timer/counter/pwm block consists of counters with user-programmable period length. It has a capture register, which records the count value of an event (such as an I/O event), a period register, which is used to either stop or auto-reload the counter when its count is equal to the period register, and compare registers to generate compare value signals, which are used as PWM duty cycle outputs. The block also provides true and complementary outputs with programmable offset between them to allow the use as deadband programmable complementary PWM outputs. It also has a kill input to force outputs to a predetermined state; for example, this is used in motor-drive systems when an overcurrent state is indicated and the PWMs driving the FETs must be shut off immediately with no time for software intervention. 1.6.2 Serial Communication Blocks (SCB) PSoC 6 MCU SCBs can implement communication interfaces such as I 2 C, UART, or SPI. 1.6.2.1 I 2 C Mode The hardware I 2 C block implements a full multimaster and slave interface (it is capable of multimaster arbitration). This block has flexible buffering options to reduce the interrupt overhead and latency for the CPU. It also supports EzI2C, which creates a mailbox address range in the PSoC 6 MCU memory and effectively reduces the I 2 C communication to reading from and writing to an array in the memory. In addition, the block supports an eight-deep FIFO for receive and transmit, which, by increasing the time given for the CPU to read the data, reduces the need for clock stretching caused by the CPU not having read the data on time. The FIFO mode is available in all channels and is useful in the absence of DMA. The I 2 C peripheral is compatible with I 2 C Standard-mode, Fast-mode, and Fast-mode Plus devices as defined in the NXP I 2 C-bus specification and user manual (UM10204). The I 2 C bus I/O is implemented with GPIO in open-drain modes. 1.6.2.2 UART Mode This is a full-feature UART that supports automotive singlewire interface (LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols, all of which are minor variants of the basic UART protocol. In addition, it supports the multiprocessor mode that allows the addressing of peripherals connected over common RX and TX lines. Common UART functions such as parity error, break detect, and frame error are supported. An eight-deep FIFO tolerates much greater CPU service latencies. 1.6.2.3 SPI Mode The SPI mode supports full Motorola SPI, TI Secure Simple Pairing (SSP) (essentially adds a start pulse that is used to synchronize SPI codecs), and National Microwire (halfduplex form of SPI). The SPI block can use the FIFO and supports an EzSPI mode in which the data interchange is reduced to reading and writing an array in memory. 1.6.3 Serial Memory Interface (SMIF) A serial memory interface has selectable 1-, 2-, or 4-bit widths. This block also supports on-the-fly encryption and decryption to support Execute-In-Place operation. 1.6.4 Audio Subsystem This subsystem consists of an I 2 S block and two PDM channels. The PDM channels interface to a PDM microphone's bit-stream output. 1.7 BLE Subsystem (BLESS) The PSoC 6 MCU incorporates a Bluetooth Smart subsystem that contains the Physical Layer (PHY) and Link Layer (LL) engines with an embedded security engine. The physical layer consists of the digital PHY and the RF transceiver that transmits and receives Gaussian frequency shift keying (GFSK) packets at 1 Mbps over a 2.4-GHz ISM band, which is compliant with Bluetooth Smart Bluetooth Specification 4.2. The baseband controller is a composite hardware and firmware implementation that supports both master and slave modes. Key protocol elements, such as human computer interface (HCI) and link control, are implemented in firmware. Time-critical functional blocks, such as encryption, CRC, data whitening, and access code correlation, are implemented in hardware (in the LL engine). The RF transceiver contains an integrated balun, which provides a single-ended RF port pin to drive a 50- antenna via a matching/filtering network. In the receive direction, this block converts the RF signal from the antenna to a digital bit stream after performing GFSK demodulation. In the transmit direction, this block performs GFSK modulation and then converts a digital baseband signal to a radio frequency before transmitting it to air through the antenna. Key features of BLESS are as follows: Master and slave single-mode protocol stack with logical link control and adaptation protocol (L2CAP), attribute (ATT), and security manager (SM) protocols API access to generic attribute profile (GATT), generic access profile (GAP), and L2CAP PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No. 002-18176 Rev. *D 25
Introduction L2CAP connection-oriented channel (Bluetooth 4.1 feature) Broadcaster, Observer, Peripheral, and Central roles User-defined advertising data Multiple bond support GATT client and server Supports GATT sub-procedures 32-bit universally unique identifier (UUID) (Bluetooth 4.1 feature) Supports all SIG-adopted BLE profiles Security Manager (SM) Pairing methods: Just works, Passkey Entry, and Out of Band LE Secure Connection Pairing model Authenticated man-in-the-middle (MITM) protection and data signing 26 PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No. 002-18176 Rev. *D
2. Getting Started 2.1 Support Free support for PSoC 6 MCUs is available online at www.cypress.com/psoc6. Resources include training seminars, discussion forums, application notes, PSoC consultants, CRM technical support email, knowledge base, and application support engineers. For application assistance, visit www.cypress.com/support/. 2.2 Product Upgrades Cypress provides scheduled upgrades and version enhancements for PSoC Creator free of charge. Upgrades are available at www.cypress.com/psoccreator. Critical updates to system documentation are also provided in the Documentation section. 2.3 Development Kits The Cypress Online Store contains development kits, C compilers, and the accessories you need to successfully develop PSoC projects. Visit the Cypress Online Store website at www.cypress.com/cypress-store. Under Products, click Programmable System-on-Chip to view a list of available items. Development kits are also available from Digi-Key, Avnet, Arrow, and Future. 2.4 Application Notes Refer to application note AN210781 - Getting Started with PSoC 6 MCU with BLE for additional information on PSoC 6 MCU capabilities and to quickly create a simple PSoC application using PSoC Creator and PSoC 6 MCU development kits. PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No. 002-18176 Rev. *D 27
Getting Started 28 PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No. 002-18176 Rev. *D
3. Document Construction This document includes the following sections: Section B: CPU Subsystem on page 33 Section C: System Resources Subsystem (SRSS) on page 123 Section D: Digital Subsystem on page 219 Section E: Analog Subsystem on page 425 Section F: BLE Subsystem (BLESS) on page 481 3.1 Major Sections For ease of use, information is organized into sections and chapters that are divided according to device functionality. Section Presents the top-level architecture, how to get started, and conventions and overview information of the product. Chapter Presents the chapters specific to an individual aspect of the section topic. These are the detailed implementation and use information for some aspect of the integrated circuit. Glossary Defines the specialized terminology used in this technical reference manual (TRM). Glossary terms are presented in bold, italic font throughout. Registers Technical Reference Manual Supplies all device register details summarized in the technical reference manual. This is an additional document. 3.2 Documentation Conventions This document uses only four distinguishing font types, besides those found in the headings. The first is the use of italics when referencing a document title or file name. The second is the use of bold italics when referencing a term described in the Glossary of this document. The third is the use of Times New Roman font, distinguishing equation examples. The fourth is the use of Courier New font, distinguishing code examples. 3.2.1 Register Conventions Register conventions are detailed in the PSoC 63 with BLE Registers TRM. 3.2.2 Numeric Naming Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase h (for example, 14h or 3Ah ) and hexadecimal numbers may also be represented by a 0x prefix, the C coding convention. Binary numbers have an appended lowercase b (for example, 01010100b or 01000011b ). Numbers not indicated by an h or b are decimal. PSoC 6 MCU: PSoC 63 with BLE Architecture TRM, Document No. 002-18176 Rev. *D 29