Midterm LAST NAME FIRST NAME PERM Number Instructions Please turn off all pagers, cell phones and beepers. Remove all hats & headphones. Place your backpacks, laptops and jackets at the front. Sit in every other seat. Nothing may be placed in the no fly zone spare seat/desk between students. You have 75 minutes to complete this exam. This exam is closed book, closed notes, no computers, PDAs or calculators. WRITE YOUR NAME on EACH PAGE OF THIS TEST. You will be deducted -1 points you can not finish this task. n 2 n n 2 n 1 2 17 131072 2 4 18 262144 3 8 19 524288 4 16 20 1048576 5 32 21 2097152 6 64 22 4194304 7 128 23 8388608 8 256 24 16777216 9 512 25 33554432 10 1024 26 67108864 11 2048 27 134217728 12 4096 28 268435456 13 8192 29 536870912 14 16384 30 1073741824 15 32768 31 2147483648 16 65536 32 4294967296
Important please note: The MIPS instructions shown in this table are the ones that you must use on the entire exam. Do not use any instructions that are not in this table. If you use any instructions not listed below, you will lose points. Name Syntax Meaning add add rd, rs, rt rd=rs+rt sub sub rd, rs, rt rd=rs-rt and and rd, rs, rt rd=rs AND rt or or rd, rs, rt rd=rs OR rt sll sll rd, rt, shamt rd=logic shift rt left shamt bits srl srl rd, rt, shamt rd=logic shift rt right shamt bits sra sra rd, rt, shamt rd=arithmetic shift rt right shamt bits slt slt rd, rs, rt If rs<rt, rd=1, else rd=0 slti slti rd, rs, imm If rs<imm, rd=1, else rd=0 jr jr rs jump to the instruction held by the memory location indicated by rs addi addi rt, rs, imm rt=rs+imm andi andi rt, rs, imm rt=rs AND imm ori ori rt, rs, imm rt=rs OR imm lw lw rt, imm(rd) rt=memory[rd+imm] sw sw rt, imm(rd) MEMORY[rd+imm]=rt beq beq rs, rt, label Branch if rs==rt bne bne rs, rt, label Branch if rs!= rt j j label Jump to label jal jal label Jump to label and link
1. [5pt] Big Ideas We ve discussed two design principles that guide the authors of instruction sets (and played a part in MIPS design). Choose the corresponding item from below and map it to the right design principle (one answer per principle) Design Principle Simple is faster Smaller is faster How was the MIPS design affected a c a) Each MIPS native instruction performs one function and requires one cycle to run b) Each MIPS native instruction requires multiple cycles to run c) MIPS has 32 registers, rather than many more d) MIPS instructions only work with hexadecimal numbers 2. [5pt] Number representation, assuming a 8-bit system Consider the following bit pattern 11111111 What is the (decimal) value of this bit pattern assuming that it is in two s complement format a) 0 b) -255 c) 255 d) -1 e) Can t tell since this representation has the property of a dirty zero d 3. [15pt] Write the value of each of these binary integer numbers in DECIMAL (assuming 8-bit system) (in sign magnitude format) 10000000 0 (in one s complement format) 10000000-127 (in two s complement format) 10000000-128
(in one s complement format) 10000001-126 (in two s complement format) 10000001-127 4. [5pt] Number representation, assuming a 32-bit system What is the smallest two s complement format number that can be stored in one 32- bit word? Express your answer in both decimal (base 10) and hex (base 16) format. -2^31 0x80000000 5. [20pt] MIPS Arithmetic and Logic Instructions Assume that Register $a0 contains 0x00000FFF Register $a1 contains 0x10001011 Register $a2 contains 0x00FFFFFF at the beginning of each of the following instructions. For each instruction, give the contents of the destination register in hex format a) and $s0, $a0, $a1 0x00000011 b) add $s1, $a0, $a1 0x10002010 c) addi $s2, $a1, 0xFFFF 0x10001010 (note: oxffff is sign extended to oxffffffff) d) or $s3, $a1, $a2 0x10FFFFFF
6. [20pt] Assembly Programming Decoding Assembly Code: The following piece of MIPS code tries to reverse the contents of an array of words (base address of the array in register $a0, length of the array in register $a1). Fill in the blanks. reverse: add $t0, $zero, $a0 add $t1, $zero, $a1 addi $t1, $t1, -1 # t1 = a1-1 sll $t1, $t1, _2 # Now t1= t1 x 4 add $t1, $a0, $t1 # $t1 points to the end of the array loop: lw $t2, 0($t0) # First element of array pointed to by $t0 lw $t3, 0($t1) # Last element of the array pointed to by $t1 sw _$t2, 0($t1) sw _$t3, 0($t0) # Loads first - then do the stores addi $t1, $t1, _-4 addi $t0, $t0, _4 # Update first and last element addresses bgt $t1, $t0, loop # Go on till $t0 >= $t1
7. [25pt] Implementing RightRotate in MIPS Imagine that there is a MIPS instruction: sllv rd, rt, rs that causes the bits in register rt to be left-shifted by the amount indicated in register rs, and the result is put into register rd. Likewise, imagine that there is a similar instruction called "srlv", i.e. shift to the right by the amount indicated in register rs. For srlv, when shifting to the right, the content of rt is zero-extended. Using these new variable shift instructions, write a MIPS FUNCTION called "RightRotate" by filling the blanks. It accepts two arguments: $a0 contains the bit string to be rotated. $a1 contains the number of bits by which to rotate the string. (Assume that $a1 contains a positive integer between 0 and 31: 0 <= $a1 <= 31.) The bits that are rotated out of the number are again inserted to the beginning of the results. For example, rotating to the right by a single bit is shown in the diagram below: In this case, the last 0 was inserted to the beginning of the result. Your function should adhere to all function conventions and return properly with the rotated result in the proper register. RightRotate: srlv $t0, $a0, $a1 # shift to the right by the amount defined by $a1. addi $t1, $0, 32 sub $t1, $t1, $a1 sllv $v0, $a0, _$t1 # shift to the left by some amount together or $v0, _$v0, _$t0 # combine two results jr $ra # function returns
8.[5pt] Assembly Programming Instructions to perform divisions Assume that we want to divide the number contained in register $s0 by 16 and save the result in register $s1. Choose the right instruction(s) to do that ( Select all that apply) a) addi $t0, $zero, 16 div $s0, $t0 mflo $s1 a) & d) b) sll $s1, $s0, 4 c) sra $s1, $s0, 2 d) sra $s1, $s0, 4 e) none of the above