Lecture 6. Digital Design Laboratory. Copyright 2007, 2009, 2010, 2014 Thomas R. Collins, Kevin Johnson

Lecture 6 Digital Design Laboratory Copyright 2007, 2009, 2010, 2014 Thomas R. Collins, Kevin Johnson

Recent changes We updated the train simulator, lecture slides, and lab manual in Fall 2014 and again this semester Updated lecture slides and lab manual pages are available on the website Changes are fairly minor, but to avoid confusion, be sure to use the updated versions.

Train scenario Two electric trains Four switches (sw1-sw6) Six sensors (S1-S6)

Lab 6: General Textbook describes an older track setup! Lecture slides which follow apply to either old or new setup (new features aren t used) Lab Manual instructions are generic, allowing for different train patterns Download the specific assignment from the web site (Lab 6 download page)

Train enhancements in lab Track 4 extends all the way across the network, whereas the textbook has just a stub. A fourth switch (Sw4) makes the new connection to the right side of Track 4. An additional sensor (S6) monitors trains near switch Sw3. Track graphics more closely resemble the shape of the network. Switch graphics show the switch position. Train speeds have a larger range than the textbook version (1, 2, 4, 8, 16 instead of just 1, 2, 3, 4). A switch connecting outside track to inside track A switch connecting the outside track

Image from train simulation New sensor (S6) New track segment and switch (Sw4)

Train problem formulation You know Initial positions of two trains When something passes over sensors You control Direction of movement (or stoppage) for each train How tracks are connected Therefore, a state machine can always keep track of where each train is At least to the extent of knowing which sensors it is between

State machine interface This is what you build the controller Based on sensors S1-S6, it must control train directions and track switch positions

State machine I/O definitions Sensor (Sn) = 1 Train on sensor n = 0 Train not on sensor n Switch (Swn) = 0 Switch n connected to outside track ( straight ) = 1 Switch n connected to inside track ( angled ) Direction A (DA[1..0]) = 00 No power (stopped) for Train A = 01 Train A moves forward (counterclockwise) = 10 Train A moves backward (clockwise) Direction B (DB[1..0]) = same as for Direction A, but applies to Train B

Train direction Each of the two trains can move forward, reverse, or stop The trains are placed such that forward is counterclockwise and reverse is clockwise Forward directions are shown below

Train speed State machine does NOT control speed Only forward/reverse/off The speed of each train is controlled by slide switches You can change them to test your design TAs will change them to make sure your design is not speed-dependent SW17-SW14 for Train A SW3-SW0 for Train B

EXAMPLE problem (Not your problem) Train A moves CCW on Tracks 1 and 2 Train B moves CCW on Tracks 2 and 3 First one to reach Sensor 1 or Sensor 2 moves into Track 2 without either train stopping If the other train reaches Sensor 1 or Sensor 2 while the first train is still in Track 2, it waits until the shared track is clear before moving into it.

Working diagrams of train positions To solve the problem, start by drawing the UNIQUE states that can occur Use provided worksheets (printable from website) Worksheets are parts of required lab results, so don t throw them away

Inside/Outside terminology of textbook Textbook describes trains (in example problem) as either being In the shared track (Track 2) or Out of the shared track Terminology like this makes it easier to verbally describe states You are not confined to this terminology for your assignment Use words that make sense for your train path state Ain

Example problem state: ABout This is the reset position: Train A on Track 1 and Train B on Track 3. If Train A reaches Sensor 1, it moves into Track 2, and the state becomes Ain. Same logic for Train B, Sensor 2, and state Bin. A A B ABout S1 Ain S2 Bin S1+S2 Ain

Without two-sensor transitions An incorrect state can be reached if two-sensor cases are not handled and the state machine clock is not very fast relative to the train speed For example, state ABout will transition to Ain because S1 is active, but Train B might move past S2 before the next state machine clock Fixed by transitioning directly from ABout to Bstop when S1&S2= 11 ABout => Ain Ain => Ain

Example problem state: Ain Train A has moved into Track 2. Train B is still on Track 3, and has NOT reached S2. If Train B does reach Sensor 2, it must stop: state Bstop. If Train A reaches S4, then it is back on Track 1, which is state ABout again. B A Ain S2 Bstop S4 ABout S2+S4 Bin

Example problem solution Compare this to textbook drawing of 5 states (Figure 8.7)

State machine outputs States Outputs About Ain Astop Bin Bstop Sw1-0 1 1 0 Sw2-0 1 1 0 Sw3 0 - - 0 - Sw4 0 - - 0 - DA[1..0] 01 01 00 01 01 DB[1..0] 01 01 01 01 00 Create from working diagrams Although don t care values are included here, you can specify values for all cases if desired

tcontrol: UML statechart Reminder: Out means outside of the common track, not in the outer loop In means using the common track

VHDL implementation notes Variable names change S1-6 Sensor1-6 Sw1-4 Switch1-4 DA DirA DB DirB Your state machine works in parallel with a much more complex state machine (TrainSetSimulator)

tcontrol.vhd ENTITY LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; Do not change ENTITY statement given to you in download! ENTITY Tcontrol IS PORT(reset, clock, sensor1, sensor2 : IN std_logic; sensor3, sensor4, sensor5, sensor6 : IN std_logic; switch1, switch2, switch3, switch4 : OUT std_logic; dira, dirb : OUT std_logic_vector(1 DOWNTO 0) ); END Tcontrol;

tcontrol.vhd ARCHITECTURE ARCHITECTURE a OF Tcontrol IS TYPE STATE_TYPE IS (ABout,Ain,Bin,Astop,Bstop); SIGNAL state : STATE_TYPE; SIGNAL sensor12, sensor13, sensor24 : std_logic_vector(1 DOWNTO 0); BEGIN PROCESS (clock, reset) BEGIN IF reset = '1' THEN -- Reset to this state state <= ABout; ELSIF clock'event AND clock = '1' THEN Concatenation of sensor bits compare with state diagram to see why this is done

tcontrol.vhd CASE for states CASE state IS WHEN ABout => CASE Sensor12 IS WHEN "00" => state <= About; WHEN "01" => state <= Bin; WHEN "10" => state <= Ain; WHEN "11" => state <= Bstop; WHEN OTHERS => state <= ABout; END CASE;

State Ain WHEN Ain => CASE Sensor24 IS WHEN "00" => WHEN "01" => WHEN "10" => WHEN "11" => WHEN OTHERS => END CASE; state <= Ain; state <= ABout; state <= Bstop; state <= Bin; state <= ABout;

State Bin WHEN Bin => CASE Sensor13 IS WHEN "00" => WHEN "01" => WHEN "10" => WHEN "11" => WHEN OTHERS => END CASE; state <= Bin; state <= ABout; state <= Astop; state <= Ain; state <= ABout;

States Astop and Bstop, and ENDs WHEN Astop => IF Sensor3 = '1' THEN state <= Ain; ELSE state <= Astop; END IF; WHEN Bstop => IF Sensor4 = '1' THEN state <= Bin; ELSE state <= Bstop; END IF; END CASE; END IF; END PROCESS;

Internal signals and constant outputs sensor12 <= sensor1 & sensor2; sensor13 <= sensor1 & sensor3; sensor24 <= sensor2 & sensor4; Concatenation, not AND Switch3 <= '0'; Switch4 <= '0'; Outputs that are not state-dependent

Switch outputs as Moore outputs WITH state SELECT Switch1 <='0' WHEN ABout, '0' WHEN Ain, '1' WHEN Bin, '1' WHEN Astop, '0' WHEN Bstop; WITH state SELECT Switch2 <='0' WHEN ABout, '0' WHEN Ain, '1' WHEN Bin, '1' WHEN Astop, '0' WHEN Bstop;

Dir outputs and END of ARCHITECTURE WITH state SELECT DirA <= "01" WHEN ABout, "01" WHEN Ain, "01" WHEN Bin, "00" WHEN Astop, "01" WHEN Bstop; WITH state SELECT DirB <= "01" WHEN ABout, "01" WHEN Ain, "01" WHEN Bin, "01" WHEN Astop, "00" WHEN Bstop; END a;

OPTIONAL alternate format WITH state SELECT DirA <= "00" WHEN Astop, "01" WHEN OTHERS; WITH state SELECT DirB <= "00" WHEN Bstop, "01" WHEN OTHERS; Only makes sense when there are values that only occur in a limited number of cases

Quartus Project: TrainTop.bdf tcontrol Switches TrainSetSimulator Sensors DirA Clock DirB Reset Other inputs Other outputs TrainSetSimulator is a black box it takes care of simulating and displaying the trains and tracks without you needing to learn all the details.

Prelab Follow all instructions in manual: Read Chapter 8 of textbook Download assignment Build UML statechart No need to get train files (VHDL, etc.) yet But if you do, use the ones on web site, not the textbook s CD Work alone and produce your own worksheets and UML statechart for a prelab checkoff