Laboratory Exercise 3 Comparative Analysis of Hardware and Emulation Forms of Signed 32-Bit Multiplication

Laboratory Exercise 3 Comparative Analysis of Hardware and Emulation Forms of Signed 32-Bit Multiplication Introduction All processors offer some form of instructions to add, subtract, and manipulate data. Other operations, such as multiplication, division, square root, or trigonometric functions can be synthesized in software, or implemented in hardware using a variety of algorithms; however, the choice of which implementation to use depends on the performance requirements of the processor. It is also fairly common to implement computing systems in devices that are not themselves dedicated processors. (Remember the title of this course!) In systems, such as communication systems, some specialized forms of scientific calculation or video processing, that require handling large quantities of data in real time but that do not support the cost of dedicated integrated circuit design, FPGAs (Field Programmable Gate Arrays) offer a way to build a processor through software, embed it in custom logic and translate this design into hardware. In this lab, you will be asked to implement a signed 32-bit integer multiplier in an FPGA and to explore the tradeoffs in whether to include dedicated multiplier hardware at all. We have several Altera evaluation boards with Cyclone II FPGAs. They offer the HDL (Hardware Description Language) code to instantiate any of three versions of a small general purpose processor they call the NIOS II. One version of this macro has a hardware multiplier but it can be turned off to see what the performance degradation is. There is also a procedure by which you can add an instruction to the instruction set and test how the program performs by counting the number of clock cycles that it takes to execute a large number of multiplications. You will set up the NIOS II processor to do multiplication four ways. First, to make sure you understand the results, you will write a C program to do the multiplication without using the multiply * operator. Second you do the same program using the multiply operator but with the hardware multiplication turned off. In this configuration the compiler emulates the same multiplication you did in C, but it uses in-line assembly language to improve efficiency. Third you will use the hardware multiplier supplied in the NIOS II HDL model. Finally, you will write a Verilog file to make an array multiplier of your choice, subject to the requirements that it be efficient on its own terms (no unnecessary propagation delays) and have no wasted code or gates. Altera offers a way to add an instruction to their processor that will route the operands through your multiplier. A peculiarity of this assignment is that it recognizes and exploits the limited precision often implicit in C coding. ANSI/ISO C only requires that the int type be at least a signed 16-bit size and that long be a signed 32-bit size. Commonly compilers make both 1

types 32-bit. For example, in Microsoft C/C++ the int is a 32-bit data type but so is long and its variants. The result of the following code is for y to be the 32 least significant bits of the true 64-bit product: /* simple multiply coding */ long y; int x, z; y = x*z; This is fine as long as the operands result in a product within the 32-bit integer range. If one just accumulates a number of such operations, the answer is still correct so long as the sum is within the range expressed by 32-bit integers. The test code for this lab is written to stay within this constraint and your software and hardware should only produce the low-order product word and the HDL should use only the minimum number of gates. NIOS II Processor Overview Nios II is a soft processor that has a number of features that can be configured by the user to meet the demands of a desired system. The processor can be implemented in three different configurations, a fast version, a standard version with a hardware multiplier, and an economy version without the multiplier. We have no need for the cache and other extended attributes of the NIOS II/f but to want to test the hardware multiplier that Altera designed. Therefore we will use the NIOS II/s version of the processor for all parts of the experiment. The Nios II processor has a Reduced Instruction Set Computer (RISC) architecture. Its arithmetic and logic operations are performed only on operands in a large general purpose register set. (There are 32 GPRs.) The data moves between the memory and these registers by means of Load and Store instructions. The wordlength of the Nios II processor is 32 bits. All registers are 32 bits long. 32-bit words must be word-aligned and may be in either little-endian or big-endian style. In little-endian fashion, the wordaligned address A will contain byte 0 of a 32-bit word, address A+1 will contain byte 1, and so on, while for big endian, addressing A will contain byte 3 and address A+3 will contain byte 0. We use the little-endian convention. Requirements Compare four different ways of implementing a 32-bit multiplication. The performance measurement is the number of clock cycles to do a set number of multiply-adds. There is a cycle counter in the same FPGA as the processor, and it can be reset, run and stopped in software. We are supplying a set of test programs that will display the run time for the program and a run time for the same procedure without multiplication so that you can back out the actual time for a multiply. All test programs use the same set of operands and so should reach the same answer for the accumulated sum. Please look at the test code to see what we have set up. (There is only a single main.c program but you force it 2

to do the four tests by setting a #define compiler directive at the top of the code. See comments in the code.) You instantiate the soft processor (Nios II/s) into the FPGA and add sufficient I/O support for the board by using Altera s SOPC builder. We recommend that you add your Verilog-based multiplier instruction to the processor before you run any code, so that all four tests are done on exactly the same processor. You may wish to proceed by running a couple of tests on the baseline processor to get used to working with it and then add your multiplication instruction, but, if so, rerun all the code. See the notes below on how to create such a project. Compiler optimizations can affect run time substantially. There are two optimization flags that can be set as discussed below. The first, -O0, turns off optimization primarily to allow debugging code by making the relation of C-instructions to blocks of assembler more straightforward for the debugger. The second, -O2, turns on most of the GNU compiler optimizations. (See http://gcc.gnu.org/onlinedocs/gcc-3.4.6/gcc/optimize- Options.html for an explanation of the optimizing process.) You must run your code for each of the four systems twice, once with each compiler option. In your writeup you are asked to comment on the effect of optimization on speed and code length. Important: How setup compiler optimizations in Nios2IDE -) Select Project->Properties -) Set the optimization levels to O0 (i.e. no optimizations) or O2 -) Remember to rebuild the project every time you change the optimization level! 1 2 3 3

Part 1 of your lab does multiplication in C-software. For this, you will need to choose the appropriate soft processor (NIOS II/s with a compiler directive to build no hardware multiplier) as you build your project. Instructions on how to turn off the hardware multiplier with a compiler directive are given below. Once you build your project, you can run our test program to evaluate the performance of your algorithm. This application is a simple C program that does a series of multiplications in a for loop. It has a line marked by a comment where you add your own C-code to do the actual multiply. The rules are: No use of the * operator No conversion of signed to unsigned type. No type conversion at all or any change to our code. All working variables must be of type int. The NIOS design is register-rich (32-GPRs), so you may experiment with using the register storage class attribute to speed the code. The test program also includes a couple of functions that count the number of cycles it takes to do for loops with and without the multiply operation. Part 2 allows the compiler to emulate multiplication by your using the * multiplication operator in the C-code but with the hardware multiplier still turned off. The test code for this part is just a change of a #define directive. You run this code on the same soft processor as Part 1. Part 3 of your project will implement the 32-bit multiplier in Altera s version of the hardware. Once again you just run the processor with the test code as set up for part 2 but with a compiler directive that instantiates the NIOS II/s hardware multiplier. In Part 4 you build and instantiate a custom 32-bit unpipelined multiplier in structural Verilog. As discussed in class, a 32-bit multiplier can be implemented in a number of ways in hardware. For example, a serial multiplier can use a single 32-bit ripple-carry adder, a 32-bit register for the multiplier, and one 64-bit product-multiplier register and implement a series of shift and add operations to produce the 64-bit result. This is an inexpensive, simple and straightforward implementation, but it is also very slow. For this assignment, you will design an unpipelined array multiplier. There are points for doing this with efficiency and speed. You will get points off for attempting to instantiate more adders than you need. Note you have to write your Verilog code as structural code, that is, write it at the gate-level. To program your hardware design onto the FPGA, you will first need to describe the hardware algorithm using Verilog. The array multiplier is composed of 1-bit full and half adders. Half adders take two inputs a i and b i and produce two outputs, c i+1 and s i, while full adders takes three inputs a i, b i, c i and produce c i+1 and s i. These need to be described in Verilog and then can be instantiated in an appropriate way to produce the array multiplier. A template for your Verilog can be downloaded from the class website. 4

Note that to build a 32-bit array multiplier requires several hundred full adder cells. It is very tedious and error-prone to instantiate each of these cells separately and connect inputs and outputs appropriately. Instead, you can use a generate loop construct in Verilog to describe repeated hardware instantiations and connections. (See a Verilog reference manual for more information on the use of this instruction. I recommend www.eecs.harvard.edu/cs141/resources/verilog-tutorial.pdf to get started with Verilog if you have had no prior exposure to it.) Once you build your project, you again run the application on the processor to evaluate the performance of the multiplier implementation. You may need to slow down the clock to make the unpipelined instruction work properly because of logic propagation delays. Software and Hardware Description: Building your NIOS II system Altera s Nios II is a soft processor, defined in a hardware description language, which can be implemented in Altera s FPGA devices by using the Quartus II CAD system. To implement a useful system it is necessary to add other functional units such as memories, input/output interfaces, timers, and communications interfaces. To facilitate the implementation of such systems, it is useful to have computer-aideddesign (CAD) software for implementing a system-on-a-programmable-chip (SOPC). Altera s SOPC Builder is the software needed for this task. To implement a system using NIOS, we have to instantiate the following functional units: Nios II processor, which is referred to as a Central Processing Unit (CPU) On-chip memory, which consists of the memory blocks in the Cyclone II chip; we will specify a 30-Kbyte memory arranged in 32-bit words JTAG UART interface for communication with the host computer A performance counter: This is a hardware counter that monitors cycles and can be read and reset from software. To define the desired system, start the Quartus II software and perform the following steps: 1. Create a new Quartus II project for your system. Save your project in a directory called proj-dir, and assign the name project-name to both the project and its toplevel design entity. You can choose any directory or project name, but be aware that the SOPC Builder software does not permit the use of spaces in file names. In your project, choose the EP2C35F672C6 chip (from Cyclone II family) as the target device, because this is the FPGA on the DE2 board. 2. Select Tools > SOPC Builder. Enter nios_system as the system name; this will be the name of the system that the SOPC Builder will generate. Choose Verilog as the target HDL, in which the system module will be specified. Click OK. 3. The figure below displays the System Contents tab of the SOPC Builder, which is used to add components to the system and configure the selected components to 5

meet the design requirements. The available components are listed on the left side of the window. Before choosing the components, examine the area in the figure labeled Target. Make sure that you Cyclone II option in device family part. 4. The Nios II processor runs under the control of a clock. For this lab we will make use of the 50-MHz clock that is provided on the DE2 board. As shown in the above, it is possible to specify the names and frequency of clock signals in the SOPC Builder display. If not already included in this list, specify a clock named clk with the source designated as External and the frequency set to 50.0 MHz. 5. On the left side of the window in the above figure select Nios II Processor and click Add. Choose the Nios II/s and click Finish. There may be some warnings or error messages displayed in the SOPC Builder Messages window (at the bottom of the screen), because some parameters have not yet been specified. Ignore these messages. IMPORTANT: For part 4 of your lab you will be adding a custom instruction to your processor. This must be done when you specify your Nios core. Instead of just clicking finish click the Custom Instructions tab when you add your processor. Click the Import button. Next click add in the design file section and select your Verilog file for the multiplier that you designed. Make sure it uses the 6

same ports as the template provided. Next click the Read port-list from files button and make sure it recognizes your signals. Finally click the Add to System button. Now you can hit Finish on your CPU configuration wizard. 6. To specify the on-chip memory perform the following: Select Memories and Memory Controllers > On-Chip > On-Chip Memory (RAM or ROM) and click Add In the On-Chip Memory Configuration Wizard window set the memory width to 32 bits and the total memory size to 30 Kbytes Do not change the other default settings Click Finish, which returns to the System Contents tab 7. Go back to the CPU module again and edit it. For Reset and Exception Vector options choose onchip_mem (see figure below) For Parts 1 and 2, you will select None (i.e., disable the embedded hardware multiplier). 7

8. We wish to connect to a host computer and provide a means for communication between the Nios II system and the host computer. This can be accomplished by instantiating the JTAG UART interface as follows: Select Interface Protocols > Serial > JTAG UART and click Add to reach the JTAG UART ConfigurationWizard. Do not change the default settings Click Finish to return to the System Contents tab 9. We also want to monitor our processor s performance without any software overhead. To do this we will add a performance counter: Select Peripherals > Debug and Performance > Performance Counter Unit and click Add Do not change the default settings Click Finish to return to the System Contents tab 10. The base and end addresses of the various components in the designed system can be assigned by the user, but they can also be assigned automatically by the SOPC Builder. We will choose the latter possibility. Select the command: System > Auto-Assign Base Addresses using the menus at the top of the SOPC Builder window. 11. Having specified all components needed to implement the desired system, generate it. Select the System Generation tab. Click Generate on the bottom of the SOPC Builder window. The generation process produces the messages displayed in the figure. When the message SUCCESS: SYSTEM GENERATION COMPLETED appears, click Exit. This returns to the main Quartus II window. Integrating the Nios II System into a Quartus II Project To complete the hardware design, we have to perform the following: Instantiate the module generated by the SOPC Builder into the Quartus II project Assign the FPGA pins Compile the circuit into device programming data Program and configure the Cyclone II device on the DE2 board The Verilog module generated by the SOPC Builder is in the file nios_system.v in the directory of the project. Note that the name of the Verilog module is the same as the system name specified when first using the SOPC Builder. The Verilog code is quite large. Don t mess with it. To use the Nios II system, we need a Verilog module that instantiates the Nios II system. This module must have the same name as the top-level design entity in the Quartus II project. Download this Verilog code from the class website. Make sure you rename it 8

appropriately. Add this file and all the *.v files produced by the SOPC Builder to your Quartus II project. Normally, a Nios II module is likely to be a part of a larger design. However, in our case there is no other circuitry needed. All we need to do is instantiate the Nios II system in our top-level Verilog file, and connect the clock and reset inputs, to the appropriate pins on the Cyclone II device. The clock and reset signals are called clk and reset_n, respectively. Note that the reset signal is added automatically by the SOPC Builder; it is called reset_n because it is active low. Add the necessary pin assignments on the DE2 board to your project by importing the assignments given in the file called DE2_pin_assignments.csv also on the class website. NOTE: Your multiplier implementation might not be fast enough to be able to handle the 50 Mhz clock frequency. If your Verilog module fails in Part4, run your multiplier at a slower frequency of 25Mhz. If this works, then you know your design is correct but its propagation delay is long. Programming and Configuration Program and configure the Cyclone II FPGA in the JTAG programming mode as follows: 1. Connect the DE2 board to the host computer by means of a USB cable plugged into the USB-Blaster port. Turn on the power to the DE2 board. Ensure that the RUN/PROG switch is in the RUN position. 2. Select Tools > Programmer. 3. If not already chosen by default, select JTAG in the Mode box. Also, if the USB- Blaster is not chosen by default, press the Hardware Setup... button and select the USB-Blaster in the window that pops up. 4. The configuration file for your project should be listed in the window. If the file is not already listed, then click Add File and select it. 5. Click the box under Program/Configure to select this action. 6. Press Start to configure the FPGA. Running the Application Program Having configured the required hardware in the FPGA device, it is now necessary to create and execute an application program that performs the desired operation. To create the program: Download the main.c program from the Laboratory Exercises page of the class web site. Using a text editor, set the #define compiler directive at the top of the C-code to activate the code for the part of the lab you are trying to test. (See comments in the code.) If you are testing part 1, enter your C-code in the body of the test_function() block where the comments direct you. To create your test code, open the Nios II EDS program under Altera in the program menu. This is a full featured IDE based on the eclipse project. Go to File > New > Project. Now select Nios II C/C++ Application. This will bring you to a new project 9

wizard. Give your project a name. Next click browse next to SOPC Builder System. Go to your project directory and make sure to select the nios_system.ptf for your system. Without the right file your code will not run! Finally select the Hello World Small template and hit finish. The first thing you should do is delete all the code in the template file! We just want the compiler optimizations it does. Copy and paste the C application you have just copied from the class web site and edited as needed with your own C-code for part 1. Name the program appropriately. On the project navigation bar on the left, right click your project and its syslib project and make sure that Active Build Configuration is set to 2 Release. This will let you include system.h (with #include <system.h>) which you must do. In order to see this file you must compile your program once by clicking build project. Then expand the syslib and go to Release > system_description > system.h. Take a look at the file and make sure you find the appropriate definitions. You will need the ALT_CI_XXXX function to use your custom instruction and the performance counter pointer with the base address. Now you are ready to run the code. To run your program right click your program s project and click Run As > Nios II Hardware. To inspect the assembly code of a project right click your program s project and click Debug As > Nios II Hardware. It should ask you to switch to the debug perspective. If it doesn t, go to Window > Open Perspective > Debug. Now when you debug your code there will be a tab on the right where you can click disassembly. This will show you the assembly code as you debug your program like any other standard debugger. Laboratory Report Requirements The laboratory report should contain the following sections: Introduction Describe the purpose of the lab and what you were attempting to do. Also write no more than one page with your understanding of what an FPGA is and does. Please supply a reference (not Wikipedia!) for the source of that understanding. Procedure Describe the procedure needed to obtain the appropriate results. For example, specify how you approached the assignment, what types of problems you had, and how you solved them. You should also reference parts of your code and describe how they operate. How did you solve any problems with the hardware? Experimental Results Describe and tabulate the results you obtained with your laboratory code and setup. (There will be 8 sets of raw data, including the 4 ways of performing the multiplication and each way compiled with and without optimization. Each data set has two cycle counts, a final sum and 10

a length for the project executable.) Estimate the machine cycles and clock time for each of the 4 forms of multiplication with and without compiler optimization after correcting for the cost of setting up the loops and summations. Comment on: How close the C-code comes to the efficiency of the compiler s assembler version of multiplication. What is most affected by compiler optimization? How close does the Altera multiplier of part 2 come to its expected speed limit? (What is that limit based on the Altera documentation?) Did you have to slow the clock for your Verilog-based multiplier to work properly? If it were necessary to speed up the multiply, would it be easy to pipeline your multiplier should it be desirable? Did the results of your measurements match what you expected to happen? Did any of those results impress you? Questions Answer the following: 1. This is a signed arithmetic multiplier using 2 s compliment integers. Since the most significant bit of the multiplier has negative weight, you must subtract the final partial product rather than add it. In your case, the final partial product affects the msb of your answer. How did you handle that problem? 2. What is the critical path through your multiplier? In terms of the full-adder delay, what is the propagation time for the array? (Assume that the formation of a partial product bit and its propagation through a half-adder takes about the same amount of time as a full-adder delay.) 3. Give an example of two operand pairs such that presenting the one after the other would test the worst case propagation. Commented Code Append a section containing your (well-commented) code for both the * -less C-code and the structural Verilog. 11