EECS 140 Laboratory Exercise 4 3-to-11 Counter Implementation

EECS 140 Laboratory Exercise 4 3-to-11 Counter Implementation 1. Objectives A. To apply knowledge of combinatorial design. B. Gain expertise in designing and building a simple combinatorial circuit This laboratory will run over two weeks. First, during lab in week 1, you will design, implement and test a 4-bit binary counter circuit. Between week 1 and week 2, you will design a circuit to recognize the decimal value 11 and use the circuit to develop a 3 to 11 counter. Finally, during lab in week 2, you will implement and test your circuit. Note that your TA will check to make certain you have completed your design prior to entering lab during week 2. 2. Discussion In this laboratory, you will design and build a circuit that modifies a standard 4-bit counter to count from 3 to 11. The basic outline of the circuit will be given to you, but you will have the opportunity to design part of the circuit yourself. In this circuit you will use the oscillator circuit from your second laboratory, a 4 bit binary counter to cycle through all the entries in a four (4) variable truth table, and some NAND gates and INVERTERS. You will use either a 74LS161 or similar counter to generate a sequence of binary numbers. Logic devices such as the 74LS161 are identified by a naming convention that indicates the technology used to implement the device along with the logic function of the device. In the name 74LS161, the 74LS prefix indicates the implementation technology (TTL if you re curious), and the 161 suffix tells us that this device is a counter. In our work, we usually only need to know the function of a device. Therefore, we will use the abbreviated name 161 to identify the device. The symbol and pinout for the 161 are shown below: (Note that you may use a counter other than a 161, but it will be similar.) 7 4 L S 1 6 1 6 5 4 3 7 10 2 9 D C B A E n b P E n b T C l k L o a d C l r Q D 11 12 Q C 13 Q B 14 Q A 1

This circuit is a typical 4-bit counter that counts input pulses on the CLK (clock) pin. On receiving each pulse the value stored in the counter increments by 1 and output via pins QA through QD. Thus, the 4-bit counter s outputs follow the sequence 0000 -> 0001 -> 0010 ->... -> 1110 -> 1111 - > 0000. By definition, this sequence generates all rows in a 4-variable truth table (all minterms). Note that the counter is also circular. When binary 15 is reached, the counter goes back to binary 0. In addition to counting, this circuit has features that allow loading an arbitrary initial value (between 0-15), and resetting the counter any time during a counting sequence. Many features of this device will not be used in this laboratory. However all of the device s functionality will be described here for completeness. The outputs QA through QD represent the current value of the counter. QA is the least significant bit and QD is the most significant bit. The inputs A through D allow the user to specify an initial value for the counter while the LOAD input signals the counter to load the initial value. Note that LOAD is a negative logic (low true) input (represented by the bubble). Thus, the counter will load its initial value when the LOAD signal is 0. The CLK signal is called the clock signal and causes the valued stored in the counter to be incremented. When the CLK signal becomes 1, the counter adds 1 to its current value and outputs the result. You can think of the counter as a circuit that counts the number of times the clock signal changes from 0 to 1. The CLR input resets all outputs to zero. Like the LOAD input, the CLR input is negative logic, zeroing the counter when a logic 0 is applied. The ENBP and ENBT signals are enable inputs that enable various features of the counter that we will not use in this laboratory. Please be assured that if you haven t seen negative logic yet, it will be covered in class before you complete the design section for this lab. 3. Tasks Design a counter that counts from 3 to 11 in binary repeatedly. Specifically, the outputs QA through QD should count 3, 4, 5, 6, 7, 8, 9, 10, 11, 3, 4, 5,... To build this counter you need to add circuitry that watches the 74LS161 output, recognizes when the output is 11, and resets the counter to 3. This will be achieved by using the LOAD signal and initial value inputs A through D to load 3 into the counter when 11 is detected. To design your counter circuit, you will implement and test a 4-bit counter in Week 1 and implement an 11 detection circuit that you will design in Week 2. Week 1: Step 1 Build a your counter circuit. First, you will construct a 0-15 counter using the 74LS161. To construct this counter you need to insert the following parts into your PCB as shown in Figure 1. Qty Item 8 Resistors, 10 k

5 Pairs of wirewrap posts 1 16-pin IC socket, solder tail 6 Pairs of wirewrap posts 1 0.01 µf capacitor 1 Pair of wirewarp posts 8 Re sist o rs 1 0 k 0.0 1 µf C a p (no t sho wn) 1-2 Po st W ir e w r a p p i n s 5-2 Po st W ir e w r a p p i n s 1 6 -p in IC So ck e t fo r 7 4 L S1 6 1 o r 7 4 L S1 6 3 6-2 Po st W ir e w r a p p i n s Figure 1 illustrates the counter area of the PCB. Once you have soldered the components in place, insert the 74LS161 (or equivalent) into the IC socket. Make sure that you have the chip oriented in the proper direction. Typically, your chip will have a notch at the end associated with pin 0. For the first part of this exercise we want the counter to continuously cycle through 16 states corresponding to the 16 rows of a four variable truth table. First connect all inputs, labeled A, B, C, and D, to Power (+5 VDC) through 10 k pull-up resistors. Then, connect the Clear, ENBP, LOAD, and ENBT inputs to Power through 10 k pull-up resistors. The clock input (CLK) should be connected to your 123 oscillator output. These connections are made by wirewrapping the 4

pairs of posts on the left or using jumpers, depending on the version of the prototype board you are using. Ask your TA if you have questions. Be certain to connect the counter s power and ground to the appropriate inputs on your board. For now, the counter outputs are not connected. When a pin is connected through a resistor to Power, we say this pin is pulled-up to a high value. Likewise, a pin connected to ground through a resistor is pulled-down. Think carefully about why CLEAR and LOAD are pulled-up. Does this cause the circuit to continuously clear its value and load a new value? Think about negative logic and what it means with respect to these inputs. Why don t we connect the pins directly to power and ground instead of including a resistor? Wouldn t leaving the resistors out make the circuit cheaper? Think about this from a physics or circuits perspective. Check the operation of your circuit. A. Verify that your oscillator is operating correctly. Note the frequency of your oscillator. B. Verify that your counter is counting. Check QA, the least significant output. At what frequency is it oscillating? What is the relationship to your oscillator frequency? C. Check the remaining counter outputs, QB, QC, QD. What is the frequency of oscillation for each output? Demonstrate your counter for your lab TA. A report will not be required for the first week s work. However, save your materials they will be necessary in preparing next week s report. Week 2: Please note that your TA will check to make certain you have completed steps 2-5 before your lab session begins. You need not have a perfect design, but you must have a completed design before the second week of lab begins. You must complete these steps prior to coming to your lab or points will be deducted. Visit with the TAs during office hours for assistance if you have difficulties. Step 2 - Design your 3-to-11 counter (This step must be done before lab.) Design a combinational circuit to recognize the decimal value 11. The circuit should have the four counter outputs (QA-QD) as inputs and compute one output that is true when the counter outputs the decimal value 11. Specifically, follow these steps: 1. Generate a truth table for a value 11 recognition function. Your circuit should have four inputs and a single output that is 1 when the four inputs represent the binary equivalent of 11. For each possible input combination, specify what the respective output should be in the truth table. Remember that we will treat QA as the 1 s bit, QB as the 2 s bit, QC as the 4 s bit and QD as the 8 s bit.

2. From the truth table, generate a Boolean algebra expression for this function using sum of products notation. How many product terms will there be? 3. Convert your function into a two level logic circuit. Using techniques shown in class, convert your circuit to a design that uses only NAND gates and INVERTERS. Having completed your recognizer circuit, it must be connected to the counter and used to control the LOAD input. Recall that the counter cycles through values from 0 to 15 repeatedly. Assuming that you connect the inputs of your recognizer to the outputs of your counter, it will output a 1 whenever the counter hits 11. To implement your 3-11 counter, you must use this output to tell the counter to start counting again at 3. Think carefully about how to perform this function. Remember that the counter has a LOAD signal that loads values from inputs A through D when asserted. Think about how to use the LOAD signal and the A through D inputs to cause the counter to go back to 3 when 11 is detected. It may be necessary to change the values input to the counter on A through D from your Week 1 implementation. Step 3 - Select your components. (This step must be done before lab.) Use the following devices to build your value 11 recognizer: For the INVERT function, use 74LS04 or equivalent For 4-input NAND function, use 74LS20 or equivalent Step 4 Draw a schematic for your 3-to-11 counter (This must be done before lab.) Draw a schematic that shows your 3-to-11 counter. Part of the schematic showing the 3-to-11 counter circuit has been provided on the last page of this write-up. You may add your new circuit to this schematic, or entirely re-draw the schematic. Schematics are the authoritative database from which subsequent design documents are derived. A Schematic shows the connections of components in a graphical manner. The schematic reflects the logic devices in the circuit, not the physical location or physical wiring of physical components. Schematics do not serve as an explanation of how the design works, but show instead how it is to be constructed. Schematics should be drawn in a neat, uncluttered manner using a logic template. Paper is not expensive. Schematics should also be drawn so the flow of information is from left to right, just as you read. Components shall be drawn in a standard manner. Components should be drawn as the function they perform, not the physical chip in place. For example, a low input, low output AND gate should be drawn as:

Each gate or component must have a unique identifier. Identifiers consist of a letter and a number. The letter indicates the type of component, R for resistor, C for capacitor, L for inductor, S for switch, Q for transistor, J for connector, I (or U or Z) for integrated circuit. The unique identifier is a handle or name for referring to the component. Each component must have its type indicated, e.g. 74LS00, 7408. The pin-out of every component must be drawn clearly on the schematic page. For low scale integrated circuits (ANDs, NANDS, etc.) draw the pin-outs of each gate below the line connecting to the gate. For medium scale integrated circuits (counters, shift registers, etc.) make sure at least one component of each type has the pin-outs labeled on each schematic page the type is used. A component should be labeled as follows: I29 74LS32 1 2 (A5) 3 A5 names the gate, I29 identifies the chip used to implement the gate, 74LS32 identifies the type of chip used to implement the gate, and numbers next to inputs and outputs identify pin numbers on the chip package. At this point in your design, only the gate and gate name should be present as you have not decided what specific chip will be used to implement each gate. Thus, a negative logic AND gate would appear in your schematic as: (A5) We will add pin and chip information later when we have identified chips to be used in the implementation. Schematics must be complete and fully connected on the page. Specifically, there should be no disconnected networks of signals with indicators, such as, A, B, and C attempting to show connectivity. Input signals to the page shall enter the page on the left and output signals from the page should exit the page on the right. All off page signals must be labeled with a signal name, an active level (H or L), and the source or destination page number or numbers (should you have more than one page). Signals shall be named according to their active meaning. For example, a signal that resets a circuit should be called RESET. That signal may exist in two forms, RESET L (reset active low) and RESET H (reset active high). Do not use bars over the signals or minus signs, or tildes in front of the signals to indicate complement. If more than one signal is grouped together (e.g. counter outputs, data bus) clearly indicate the least or most significant bit of the group with the label "LSB" or "MSB", respectively. For documentation purposes, each schematic page must have a complete title block that includes: the design name, the name of the logic represented on the page, the designer's initials, the draftsperson s initials, the data, the class, the schematic page number, and revision history.

Draw a schematic that indicates connections between components in your 3-11 counter. This should minimally include the 161 counter and NAND gates implementing your 11 recognizer. You may also include INVERTERs if necessary. Use the counter diagram from the previous figure to represent the 76LS161 (or equivalent) in your system. If you are not using a 161, your TA will provide information on the replacement counter. In a schematic, individual gates and devices are included, not the physical chips that contain the gates. Each gate or device is shown independently from the chip where they reside. Your schematic need not indicate power and ground connections. Step 5 Develop a netlist and layout for your circuit (This step must be done before lab.) After you have designed your circuit, you need to specify how to wire your implementation. A netlist is a list of connections between components you intend to solder or wirewrap together to implement your circuit. The netlist serves as a guide for implementing and debugging the circuit. In industry, automated fabrication devices that implement your circuit use the netlist. For this lab, your netlist serves as a set of instructions for soldering or wirewrapping components together. Each component in your schematic will be associated with a device on a chip that implements the associated component function. To develop a netlist, you must: (i) identify the chips needed to implement your circuit; and (ii) associate a device on a chip with each component in your schematic. Start by identifying the chips you will need to implement your circuit. Take each device from your schematic and identify a chip that implements the device. For this lab, you will need a 74LS161 to implement your circuit as well as chips implementing NAND and INVERTER functions. These chips will be identified for you or datasheets provided for you to select from. In future labs you will be responsible for finding the chips you need to construct your circuit. Note that many chips implement multiple devices. For example, a quad AND chip implements 4 AND gates. It is important that you use all devices on a chip before using another chip of the same type. Give each chip you have selected a unique identifier. As noted earlier, the name is typically a letter indicating the package type and a number uniquely identifying the chip. Integrated circuits are identified by a name beginning with I, thus you might name your counter chip I1 and your NAND package I2. With each chip named, it is now possible to uniquely identify any pin on any chip by giving a chip name and pin number. It is important that you write down all of the chips and names assigned to them. Your next task is to assign the components you have drawn in your schematic to actual chips. On your schematic, label each device with the name of the chip used to implement the device. Next, label the inputs and outputs associated with each gate with the associated pin numbers on the chip as follows:

I29 74LS32 1 2 (A5) 3 Pin numbers (frequently called pin-outs) and functions for chips are specified on a datasheet that is provided by the manufacturer. You will be provided with datasheets for your chips in lab or you can easily find them on the web. In this example A5 names the gate and I29 identifies the chip. Pins I29-1 and I29-2 are the inputs to the gate and I29-3 is the output from the gate. It is not sufficient to simply identify which chip implements the gate because chips may implement many gates. By labeling each gate input and output with its associated pin numbers from the chip, the specific device on chip is uniquely identified. Now we are ready to construct the netlist. For each connection on your schematic, specify a connection in your net list as a pair of pin identifiers. Assume that you choose an 74LS10 and name it I2 and name your 74LS161 I1. If the output of the counter pin OD is needed on pin 2 of I2, the connection I1-11 to I2-2 will appear in your netlist. Systematically step through your wiring diagram making a list of each connection by indicating the pair of pins being connected. It is handy to make a copy of your schematic and then highlight each connection on your copy as you write the connection on the netlist. Note that power and ground are not explicitly shown on the schematic. However, you must make sure power and ground are connected to each IC in your circuit. The easiest way to ensure that this occurs is to show the connections in your device netlist. The simplest way to do this is to include connections like I15-power or I15-5V. Finally, you need to lay your chips out and decide how to route physical connections on your board. In digital design, this process is called floor planning. For very small circuits such as your counter, floor planning is not difficult. For large systems, floor planning can limit options in your implementation. To perform this task, you need to draw a picture of your board showing all chips with their associated names and pin numbers labeled. Note that this is different from your schematic where each gate or device is shown. This drawing should indicate where your chips appear relative to each other and the rest of your circuit. You can now draw your pin connections on the layout diagram if you choose. For this lab, you can simply stop with the chip layout and use it as a guide when wiring your system. Step 6 Build your combinatorial circuit To build your circuit, you will need to obtain the chips you selected and wirewrap sockets from the EECS Shop. Make a list of the components and for each chip obtain a 14-pin or 16-pin wirewrap socket. Do not use 16-pin sockets for 14-pin packages. Take your list to the EECS Shop and obtain the parts you need. You must be specific in asking for the circuits you need. Build your combinatorial circuit by stepping through each connection listed in your netlist and perform the indicated connection. Your TA should show you how to use the wirewrap tool to

make a connection between pins. Ask your TA if you have any questions. As you make each connection, place a check mark by that connection in your netlist. When you have completed your wiring, step through the netlist again checking the integrity of each connection using a digital multimeter in Ohms or resistance mode. Connect one lead to the first pin of a connection and the second lead to the second pin of the connection and verify that you wired the connection correctly. If a connection is wire correctly, the multimeter should measure 0 Ohms. This process of checking each connection is call ringing out an implementation. If your design is correct and rings out correctly, you should have a correct circuit. Step 7 - Verify operation After wiring and ringing out your circuit, it is time to check the operation of your implementation. First, verify that your counter is still operating. This process is called regression testing and assures that you did not accidentally damage your counter circuit from week 1. Regression testing is extremely important and can save significant time. Perform the following operations: A. Verify that your oscillator is operating. Note the frequency of your oscillator. B. Verify that your counter is counting. Check QA, the least significant output. What is the oscillation frequency? What is the relationship to your oscillator frequency? C. Check the remaining counter outputs, QB, QC, QD. What is the frequency of oscillation for each output? Second, verify that your 3-to-11 counter circuit is correct: D. Check that your circuit is generating a TRUE output (low) every 9 clock pulses. Verify that when the LOAD input is low and the CLK raises, the counter loads a value of 3. Ideally, your circuit will work the first time. In practice, this is usually not the case. If your circuit is not functioning properly, first make certain you have performed regression testing to determine the counter is still functioning. Then, make certain your circuit rings out correctly. If these checks don t reveal a problem, it may be that your design has an error. To debug a design, work backwards from your outputs to your inputs checking to make certain each stage is producing correct outputs. For example, explicitly tie inputs of your 11 detector circuit to specific values and make certain it generates a correct output based on your truth table. Your TAs are very familiar with this process and can provide assistance. Step 8 - Write your lab report Write your lab report per instructions from your TA. Make certain you include all of your drawings and netlists with your lab. You do not need to generate your drawings on the computer. If you do them by hand, you must use a logic template and a straightedge to draw your circuit. Neatness in your report and implementation are vital.