Experiment # 5 Debugging via Simulation using epd
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- Justin Owens
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1 1. Synopsis: Experiment # 5 Debugging via Simulation using epd In this lab you will be debugging an arbitrary design. We have introduced different kinds of errors in the design purposefully to demonstrate various common errors made during schematic entry. You will find these errors by incrementally simulating the design and fixing the errors as they are revealed during the simulation. 2. Common Errors: There are several errors in the design. This section should help you in understanding what sort of errors to look for in the design given to you. Each one of these errors falls into one of the following broad categories: 2.1 Wiring/drawing/labeling errors: These are errors made during the drawing of the circuit. Examples are unconnected pins, dangling wires (wires are also called nets ) and misconnected wires (e.g., a wire that should be connected to VDD might be connected to GND). 2.2 Logical errors: The logic implemented to achieve a certain operation could be improper. Especially, watch out for such errors in simple basic building blocks. The building blocks (components) themselves may be erroneous! Note that you have to exhaustively test a circuit to locate such errors as it is possible that an erroneous circuit would work ok for a certain input pattern but not for another. 2.3 Bit ordering errors: In components such as adders, subtractors and comparators, the order of bit labels [position of bits from the most significant bit (MSB) to the least significant bit (LSB)] is very crucial. Watch the bus pin labels and make sure inputs are connected properly (with proper Bus labels). 3. Description of the circuit: This is an arbitrary circuit with no meaningful function. There are five 4-bit inputs: A, B, Q, X and Y. The 1-bit output "Result" is equal to "R2" when the sum of P (which, in turn, is selected from A or B) and Q is greater than the difference of X and Y. Else, "Result" equals "R1". R1 and R2 are set in the command file as high and low, respectively. Following is the explanation of the desired working of various components in the circuit: ee201l_debugging.fm [Revised: 11/27/05] 1/5
2 3.1 Inverting Demux (demux_inv): The demux needed in this design should invert the input ( EN ) and present it to the selected output. The unselected output(s) should take a value bit Wide TriState Buffer (buftri4): Spartan tri-state buffers are active-high disable. This means, that the output of the buffer is tristated when the tri-state control input T is HIGH bit wide Cascadable Comparator(compare4): The 4-bit wide cascadable comparator (compare4) has the same functionality as 74LS85 comparator. The three cascade inputs (IALTB, IAEQB and IAGTB) can be used to cascade multiple comparators to generate wider comparator. In our case, we do not need these inputs, but they have to be disabled sensibly bit wide Substractor(subtractor4): This component uses the Spartan ADSU4 library component, which is a 4-bit adder/subtractor. To use this component as a subtractor, we have connected the ADD input to 0. Note: A - B = A + (-B) = A + B + 1. ee201l_debugging.fm [Revised: 11/27/05] 2/5
3 4. Prelab: After reading the lab assignment, please read the top level schematic (ee201l_debugging.1) carefully and answer the following questions. Q 4. 1: The tri-state buffers (Buftri4) conduct when T is (HIGH/LOW). (5pts) Q 4. 2: In order for the design to work, EN should be connected to (0/1/SEL). (5 pts) Q 4. 3: When the SEL line is 0, P[3:0] gets (A[3:0]/B[3:0]). (5 pts) Q 4. 4: How would you cascade two Compare4 chips to make an 8-bit wide comparator? (5pts) Q 4. 5: Complete the truth table of a three input XOR gate. (5 pts) A B C XOR Q 4. 6: Write the simplified boolean equation for a Full Adder (FA) assuming that the inputs are A, B and Cin. (5 pts) Sum (S) = Carry_out (Cout) = ee201l_debugging.fm [Revised: 11/27/05] 3/5
4 5. Procedure: 5.1 Import the necessary files into your account: cd ~/pv/ee201l ~eeview/ee201l_debugging.shar This brings the following 14 files to your account: sch/ee201l_debugging.1 sch/compare4.1 sch/adder4.1 sch/subtractor4.1 sch/buftri4.1 sch/demux_inv.1 sch/fa.1 cmd/ee201l_debugging.cmd sym/compare4.1 sym/adder4.1 sym/subtractor4.1 sym/buftri4.1 sym/demux_inv.1 sym/fa Open the top level schematic (ee201l_debugging) and try to understand the design. 5.3 Complete the command file (cmd/ee201l_debugging.cmd) by following the hints given in the same file. Following is the pattern of inputs you have to specify (using the pat key word) for various inputs in the command file. Cycle Sel A B B B A A B A B A B Q X Y Once you have completed the command file, simulate the top level design (ee201l_debugging), incrementally. Use the cycle command at the sim prompt to simulate the design for one or more cycles. (Example given below) sim> cycle 1 sim> cycle 3 Important: Simulate the design incrementally, i.e., simulate for 1 cycle, observe the waveform and fix the errors. Then resimulate and if the error(s) is (are) fixed, simulate for another cycle and debug again. This systematic debugging will help you a lot. If a component seems to misbehave, open the underlying schematic and debug as needed. ee201l_debugging.fm [Revised: 11/27/05] 4/5
5 6. Lab Report: Name: Lab Session: Date: TA s Signature: For TAs: Prelab (out of 30): Report (out of 70): Comments: Q 6. 1: Q 6. 2: Debug the design and attach the printout of all the schematic files that you modified and the final waveform showing the working design. Highlight or circle the modifications you made. (40 pts) What happens when all the three cascade inputs (IALTB, IAEQB and IAGTB) of the comparator are connected to GND? Is the behavior reasonable? Explain. (10 pts) Q 6. 3: Here we used two 4-bit wide tri-state buffers controlled by a demux. The same can be replaced by a 4-bit wide 2x1 Mux. Here it appears that we have two equally good solutions to performing the muxing operation. However, if you were to perform muxing action between the 32-bit outputs from two data-generator chips, would you use a separate (stand-alone) 32-bit wide, 2x1 Mux or specify tri-state outputs (with enable control) for the two data-generator chips? i.e. do you rather prefer that tri-state buffers are embedded in the output stage of the two data-generator chips? (10 pts) Q 6. 4: The ADSU4 library component subtractor has CO (carry out) and OFL (overflow) outputs. What is the difference between them? Explain with the help of an example. (10 pts) A useful resource to read about the functionality of Xilinx Library components is the Xilinx Support Website. => Support => Documentation => Software Manuals (this take you to ) => 7.1i Software Manuals => HTML Collection => expand Libraries Guide (on the left panel) => Design Elements). Expand the ACC1 to BUFT4,8,16 section and select ADSU4,8,16 to find the answer to this question. PLEASE DO NOT COPY & PASTE. Give an answer in your own words. Also Functional Categories under Libraries Guide is a good information resource. ee201l_debugging.fm [Revised: 11/27/05] 5/5
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