Power Matters. TM RISC-V based core as a soft processor in FPGAs Chowdhary Musunuri Sr. Director, Solutions & Applications Microsemi chowdhary.musunuri@microsemi.com RIC217 1
Agenda A brief introduction to FPGAs A few examples of applications built on FPGAs RISCV as a soft processor core in FPGAs Power Matters. TM 2
What is an FPGA? An FPGA is an integrated circuit that can be configured to emulate any digital circuit as long as there are enough resources An FPGA can be seen as an array of configurable logic elements connected through programmable routing interconnect Programmable Logic Element Programmable Interconnects Programmable I/Os Power Matters. TM 3
Simplified Logic Element Structure Look-Up Table (LUT) D SET Q MUX A B C O CLR Q D A B C D O 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A B C D 1 D SET CLR Q Q MUX O 1 1 1 1 1 1 Configuration bits 1 1 1 1 1 Power Matters. TM 4
Translating a design to an FPGA Develop Design in RTL Example: Verilog/VHDL Compile Design Synthesis, Timing, P&R Program design in FPGA Design is captured in RTL code and/or in vendor provided design entry tools Design is run through vendor provided CAD tools Program design in FPGA Reconfigurable FPGAs can be programmed multiple times for different functionality or fixing bugs Power Matters. TM 5
Performance Vs. Flexibility General Purpose Microprocessors FPGA ASIC ASIC gives high performance at the cost of flexibility A general purpose Processor is very flexible but not tuned to the application An FPGA gives a nice compromise between application tuned performance and re-programmable flexibility Power Matters. TM 6
Modern FPGA Architecture Power Matters. TM 7
SoC FPGA Design Suite Power Matters. TM 8
A few SOC FPGA application examples Power Matters. TM 9
Ethernet Access RISCV soft processor can be used for configuration of peripherals and internal functional IP blocks Microsemi PolarFire FPGA 1 to 16 GE/FE Enet MACs Queuing 1588 Packet Timing & Synchronization Packet Processing & Switching, QoS 1 x 1 GE Fiber MDIO RISCV SubSystem I2C for configuring SFP modules 12G QoS Switching in FPGA with Hierarchical Queues 3% Lower total power Instant ON FPGA can also be used for system management Power Matters. TM 1
Wireless HetNet: RRH & BBU RISCV soft processor subsystem can be used for configuration of peripherals and internal functional blocks Microsemi PolarFire FPGA Microsemi PolarFire FPGA To AFE JESD 24B DPD CFR DUC DDC CPRI framer CPRI CPRI CPRI framer BB Processing, Bridging, Control, Switching To Backhaul, Cloud 1GbE, OTN, GbE SPI & I2C to Configure External ADCs RISCV SubSystem RISCV SubSystem I2C for configuring SFP modules Signal processing capabilities with hardened preadders ideal for supporting low/mid bandwidth DFE (4x4x6MHz) and Baseband Processing Ideal for up to 12.5G CPRI and JESD24b interfacing Up to 5% lower total power Best Security and SEU immune FPGA fabric Power Matters. TM 11
Power Generation Control Microsemi PolarFire FPGA 2 x 1G Ethernet HSR PRP RISCV SubSystem RS232/RS485 bus SPI, GPIO MAC Control Loops & PWM Actuator i/f Driver & Isolating circuit Solar Water Wind Power DC/DC Converter & DC/AC Inverter Smart grid Lowest power Instant on control functions Security Power Matters. TM 12
Imaging/Video/Camera Applications Microsemi PolarFire FPGA Image aggregation and blending Format conversion to PCIe PCIe Interface (Capture Card) CMOS Image CMOS Sensor Image CMOS Sensor Image CMOS Sensor Image Sensor CMOS sensor interfaces Image Processing IP HDMI Out I2C Sensor Configuration RISCV SubSystem LPDDR3 Memory controller LPDDR3 Image Processing is done in the FPGA logic hardware Embedded FPGA Mathblocks, PCIe Subsystem & DDR support Soft RISCV processor subsystem is used for configuration of peripherals and internal functional blocks Power Matters. TM 13
RV32IM RISCV Soft processor RISCV soft processor on Microsemi PolarFire FPGA Power Matters. TM 14
What is RISC-V A New free and open ISA developed at UC Berkeley RISC-V is Instruction Set Architecture (ISA). Not a processor The micro architecture implementations can be open or proprietary Goal is to encourage both open-source & proprietary implementations of the RISC-V ISA specification Designed for Research, Education & Commercial use Four base integer ISA variants RV32I, RV64I, RV32E, RV128I (32,64,128bit machines) Standard Extensions M: Integer Multiply/Divide A: Atomic Memory Operations F: Single Precision FP D: Double Precision FP G: IMAFD, General Purpose ISA Q: Quad Precision Floating Point C: 16-bit compressed instruction (RV32C, RV64C) Power Matters. TM 15
RISC-V Soft Processor on PolarFire FPGA CoreRISCV_AXI4 Supports the RISC-V standard RV32IM ISA Integrated 8Kbytes instruction cache and 8Kbytes data cache Two external AXI interfaces for IO and memory Supports up to 31 programmable interrupts Debug unit with a JTAG interface Best suited for low to mid range microcontroller applications Power Matters. TM 16
CoreRISCV_AXI4 Processor Core Based on the E31 Coreplex core by SiFive Provides a single hardware thread Machine-mode privileged architecture Supports the RISCV standard RV32IM ISA Two External AXI Interfaces AXI memory Interface Cached access to instruction & data memory AXI I/O interface Un-Cached access to I/O peripherals Memory System First level Instruction Cache Platform-Level Interrupt Controller (PLIC) 8KB, Direct Mapped with 64 bytes line size, single clock cycle access latency First Level Data Cache 8KB, Direct Mapped with 64 bytes line size Access Latency is two clock cycles for full words and three clock cycles for smaller quantities Un-Cached memory access for I/O TAPC Single Step AXI X Uncached TileLink 5 Stage Pipeline RV32IM Integer Mul/Div I and D Cache AXI X E31 Core Power Matters. TM 18
CoreRISCV_AXI4 Interrupt Sources Local Interrupts Wired directly to the CPU internally Standard Software Interrupts (Traps, Exceptions) Timer Interrupt Global Interrupts Routed via Platform Level Interrupt Controller Supports up to 31 external interrupt sources Platform-Level Interrupt Controller (PLIC) TAPC Single Step Uncached TileLink All external interrupts are single priority level at priority 1 (External interrupts in the system can be connected here) JTAG Interface Industry standard 1149.1 JTAG interface Supports Interactive debug Supports Hardware Breakpoints (Max:2) Accessible via Microsemi FlashPro5 JTAG programmer/debugger AXI X 5 Stage Pipeline RV32IM Integer Mul/Div I and D Cache AXI X E31 Core Power Matters. TM 19
SoftConsole IDE Softconsole 5./5.1(beta) SC5./SC5.1 works with Flashpro5. JTAG debugger SC5. supports specific versions of Ubuntu, Red hat/centos and OpenSuse SC5.1(beta) supports windows 7 Firmware project structure riscv-hal startup code, hardware abstraction layer, interrupt management Drivers - Drivers for peripherals e.g. UART, I2C and SPI riscv_hal is available on github Power Matters. TM 2
CoreRISCV_AXI system CoreBootStrap is configurable hardware boot loader At POR CoreBootStrap asserts PROC_RESET and holds RISCV in reset Copies executable binary from SPI Flash memory to internal RAM and releases the PROC_RESET Image can reside in external SPI flash or internal NVM memory RISCV executes the code from internal RAM Power Matters. TM 21
Microsemi RISCV on GitHub https://github.com/riscv-on-microsemi-fpga Documentation Example Design Projects Power Matters. TM 22
Questions? Power Matters. TM 23
Thank You Power Matters. TM 24