19-5293; Rev 1; 3/11 EVALUATION KIT AVAILABLE Host Charger Identification General Description The are second-generation devices that combine Hi-Speed analog switches with a host charger (dedicated charger) identification circuit. These devices support both the latest Battery Charging Specification Revision 1.2 including data contact detection and a set resistor bias for Apple-compliant devices as well as legacy D+/Dshort detection using data line pullup. The MAX14566E has a pmosfet open-drain control output () and the MAX14566AE has an nmosfet open-drain control output () to restart the peripheral connected to the host. These devices feature high-performance Hi-Speed switches with low 4pF (typ) on-capacitance and low 4.I (typ) on-resistance. In addition, the devices feature a single digital input () to switch between pass-through mode and autodetection charger mode. The host charger identification circuit allows a host port to support chargers with shorted /DM detection and to provide support for Apple-compliant devices using a resistor bias on data lines. When an Applecompliant device is attached to the port in autodetection charger mode, the devices supply the voltage to the and DM lines from the internal resistor-divider. If a Revision 1.2-compliant device is attached, the devices short and DM to allow correct charger detection. The MAX14566BE features an additional digital input (1) to allow forced charger mode. These devices have enhanced, high electrostatic discharge (ESD) protection on the and DM inputs up to Q15kV Human Body Model (HBM). All the devices are available in an 8-pin (2mm x 2mm) TDFN package, and are specified over the -4NC to +85NC extended temperature range. S Hi-Speed Switching S Low 4.pF (typ) On-Capacitance S Low 4.I (typ) On-Resistance Features S Ultra-Low.1I (typ) On-Resistance Flatness S +2.8V to +5.5V Supply Range S Ultra-Low 3µA (typ) Supply Current S Automatic Current-Limit Switch Control S Automatic Charger Identification Circuit S ±15kV High ESD HBM Protection On /DM S 2mm x 2mm, 8-Pin TDFN Package S -4NC to +85NC Operating Temperature Range Laptops Netbooks Applications Universal Charger including ipodm/iphonem Chargers PART Ordering Information/ Selector Guide PIN- PACKAGE CLS CONTROL TOP MARK MAX14566EETA+ 8 TDFN-EP* ADJ MAX14566AEETA+ 8 TDFN-EP* ADK MAX14566BEETA+ 8 TDFN-EP* BMR Note: All devices are specified over the -4 C to +85 C operating temperature range. +Denotes a lead(pb)-free/rohs-compliant package. *EP = Exposed pad. Typical Operating Circuit EXTERNAL POWER SUPPLY Li+ BATTERY 5V SWITCHING POWER SUPPLY OVERCURRENT PROTECTOR A APPLE DOCK CONNECTOR APPLE DOCK ipod OR iphone LAPTOP CHIPSET TRANSCEIVER STANDBY TDM DM D- T MAX14566E D+ A CONNECTOR PHONE OR MP3 PLAYER A MICRO B MICRO- CONNECTOR iphone and ipod are registered trademarks of Apple, Inc. Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim s website at www.maxim-ic.com.
ABSOLUTE MAXIMUM RATINGS (All voltages referenced to.), T, TDM,,, DM, /, 1...-.3V to +6. Continuous Current into any Terminal... Q3mA Continuous Power Dissipation (T A = +7NC) TDFN (derate 11.9mW/NC above +7NC)...954mW Operating Temperature Range... -4NC to +85NC Junction Temperature...+15NC Storage Temperature Range... -65NC to +15NC Lead Temperature (soldering, 1s)...+3NC Soldering Temperature (reflow)...+26nc Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PACKAGE THERMAL CHARACTERISTICS (Note 1) TDFN Junction-to-Ambient Thermal Resistance (q JA )...84 C/W Junction-to-Case Thermal Resistance (q JC )...37 C/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. ELECTRICAL CHARACTERISTICS ( = 2.8V to 5.5V, T A = T MIN to T MAX, unless otherwise noted. Typical values are at = 5., T A = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER SUPPLY (MAX14566E/MAX14566AE) Power-Supply Range V > V IH 2.8 5.5 V V = (Note 3) 4.75 5.25 V Supply Current I CC V = V = = 3.3V 2 = 5.5V 7 = 4.75V 11 2 = 5.25V 12 2 Supply Current Increase DI CC P V P V IL or V IH P V P 2 FA POWER SUPPLY (MAX14566BE) Power-Supply Range V = and V 1 = or V = and V 1 = or V = and 2.8 5.5 V V 1 = V = and V 1 = (Note 3) 4.75 5.25 V FA Supply Current I CC V = and V 1 = or V = and V 1 = V = and V 1 = = 3.3V 2 = 5.5V 7 = 4.75V 11 2 = 5.25V 12 2 ma V = and V 1 = = 5. for TYP = 5.5V for MAX 3 7 Supply Current Increase DI CC V 1 = ; V V IL and V IH V (Note 4) V = ; V 1 V IL and V IH V 1 (Note 4) 1 1 ma 2
ELECTRICAL CHARACTERISTICS (continued) ( = 2.8V to 5.5V, T A = T MIN to T MAX, unless otherwise noted. Typical values are at = 5., T A = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ANALOG SWITCH Analog-Signal Range V,V DM V On-Resistance T/TDM Switch R ON V = V DM = to, I = I DM = 1mA 4. 6.5 I On-Resistance Match Between Channels T/TDM Switch On-Resistance Flatness T/ TDM Switch DR ON = 5., V = V DM = 4mV, I = I DM = 1mA R FLAT = 5., V = V DM = to, I = I DM = 1mA.1 I.1 I On-Resistance of /DM Short R SHORT V =, V = 1V, I = IDM = 1mA 4 7 I Off-Leakage Current On-Leakage Current DYNAMIC PERFORMANCE I TOFF, I TDMOFF = 3.6V, V = V DM =.3V to 3.3V, V T = V TDM = 3.3V to.3v, V = -25 +25 na I ON,I DMON = 3.6V, V = V DM = 3.3V to.3v, V = -25 +25 na Turn-On Time t ON V T or V TDM = 1.5V, R L = 3I, C L = 35pF, Figure 1 Turn-Off Time t OFF V T or V TDM = 1.5V, R L = 3I, C L = 35pF, Figure 1 T, TDM Switch Propagation Delay 2 1 Fs 1 5 Fs t PLH, t PHL RL = R S = 5I 6 ps Output Skew t SK(O) connected to T and TDM, Skew between and DM when R L = R S = 5I, Figure 2 4 ps T, TDM Off-Capacitance C OFF f = 1MHz 2. pf, DM On-Capacitance (Connected to T, TDM) C ON f = 24MHz 4. 5.5 pf -3dB Bandwidth BW R L = R S = 5I (Note 4) 1 MHz Off-Isolation V ISO V T, V = dbm, R L = R S = 5I, f = 25MHz, Figure 3 (Note 4) Crosstalk V CT V T, V = dbm, R L = R S = 5I, f = 25MHz, Figure 3 (Note 4) INTERNAL RESISTORS -2 db -25 db /DM Short Pulldown R PD 335 5 71 ki RP1/RP2 Ratio RT RP 1.485 1.5 1.515 Ratio RP1 + RP2 Resistance R RP 95 126 176 ki RM1/RM2 Ratio RT RM.843.85.865 Ratio RM1 + RM2 Resistance R RM 7 94 132 ki COMPARATORS DM1 Comparator Threshold V DM1F DM falling 45 46 47 % DM1 Comparator Hysteresis 1 % DM2 Comparator Threshold V DM2F DM falling 6.31 7 7.6 % DM2 Comparator Hysteresis 1 % Comparator Threshold V R rising 45 46 47 % 3
Host Charger Identification ELECTRICAL CHARACTERISTICS (continued) ( = 2.8V to 5.5V, T A = T MIN to T MAX, unless otherwise noted. Typical values are at = 5., T A = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Comparator Hysteresis 1 % LOGIC INPUT (, 1) /1 Input Logic-High V IH 1.4 V /1 Input Logic-Low V IL.4 V = 5.5V, P V P V IL or /1 Input Leakage Current I IN V IH P V P -1 +1 FA / OUTPUTS Toggle Time (MAX14566E/ MAX14566AE) Output Logic-High Voltage Output Leakage Current Output Logic-Low Voltage Output Leakage Current ESD PROTECTION ESD Protection Level ( and DM Only) ESD Protection Level (All Other Pins) Note 2: All units are 1% production tested at T A = +25NC. Specifications over temperature are guaranteed by design. Note 3: The part is operational from +2.8V to +5.5V. However, in order to have the valid Apple resistor-divider network, the supply must stay within the range of +4.75V to +5.25V. Note 4: Guaranteed by design. Test Circuits/Timing Diagrams t VBT = logic to logic 1 or logic 1 to logic.5 1 2 s = logic to logic 1, I SOURCE = 2mA (MAX14566E only) = 5.5V, V =, deasserted (MAX14566E only) = logic to logic 1, I SINK = 2mA (MAX14566AE only) = V = 5.5V, deasserted (MAX14566AE only) -.4 V 1 FA.4 V 1 FA V ESD HBM Q15 kv V ESD HBM Q2 kv V IN TD_ MAX14566E MAX14566AE MAX14566BE D_ V OUT LOGIC INPUT V IH V IL 5% t OFF t r < 5ns t f < 5ns LOGIC INPUT R L C L SWITCH OUTPUT V OUT t ON.9 x V UT.9 x V OUT C L INCLUDES FIXTURE AND STRAY CAPACITANCE. R L V OUT = V IN R L + R ON IN DEPENDS ON SWITCH CONFIGURATION; INPUT POLARITY DETERMINED BY SENSE OF SWITCH. Figure 1. Switching Time 4
V IN+ V IN- V OUT+ R S R S t PLHX T TDM 5% 5% 5% MAX14566E MAX14566AE MAX14566BE tphlx Test Circuits/Timing Diagrams (continued) DM 5% 5% 5% R L R L OUT+ IN+ IN- V+ V+ V+ V+ OUT- t INRISE t OUTRISE RISE-TIME PROPAGATION DELAY = t PLHX OR t PLHY FALL-TIME PROPAGATION DELAY = t PHLX OR t PHLY t SK(O) = t PLHX - t PLHY OR t PHLX - t PHLY t SK(P) = t PLHX - t PHLX OR t PLHY - t PHLY 9% 1% 1% 9% 9% 9% t INFALL t OUTFALL 1% 1% V OUT- 5% 5% t PHLY tplhy Figure 2. Output Signal Skew 5
Figure 3. Off-Isolation and Crosstalk ( = 5V, T A = +25NC, unless otherwise noted.) RON (I) 4.5 4. 3.5 3. 2.5 2. 1.5 1..5 OR T/TDM ON-RESISTANCE vs. SUPPLY VOLTAGE = 2.8V = 5.5V.5 1. 1.5 2. 2.5 3. 3.5 4. 4.5 5. 5.5 6. V T (V) MAX14566E MAX14566AE MAX14566BE T * MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS. OFF-ISOLATION IS MEASURED BETWEEN TD_ AND "OFF" D_ TERMINAL ON EACH SWITCH. CROSSTALK IS MEASURED FROM ONE CHANNEL TO THE OTHER CHANNEL. MAX14566E toc1 RON (I) 5. 4.5 4. 3.5 3. 2.5 2. 1.5 1..5 V IN V OUT Test Circuits/Timing Diagrams (continued) ON-RESISTANCE vs. V T/TDM T A = +85 C MEAS 5Ω T A = +25 C NETWORK ANALYZER 5Ω T A = -4 C Typical Operating Characteristics = 3.3V.5 1. 1.5 2. 2.5 3. 3.5 4. V T/TDM (V) 5Ω 5Ω REF MAX14566E toc2 RON (I) 5 45 4 35 3 25 2 15 1 5 OFF-ISOLATION = 2log V OUT V IN CROSSTALK = 2log V OUT V IN *FOR CROSSTALK THIS PIN IS DM. /DM SHORT ON-RESISTANCE vs. SUPPLY VOLTAGE = 2.8V V (V) = 5.5V.5 1. 1.5 2. 2.5 3. 3.5 4. 4.5 5. 5.5 6. MAX14566E toc3 6
Typical Operating Characteristics (continued) ( = 5V, T A = +25NC, unless otherwise noted.) LEAKAGE CURRENT (na) ICC (µa) LOGIC-INPUT THRESHOLD (V) 45 4 35 3 25 2 15 1 T/ LEAKAGE CURRENT vs. TEMPERATURE = 3.6V, V T = 3.3V ON-LEAKAGE 5 OFF-LEAKAGE -45-3 -15 15 3 45 6 75 9 16 14 12 1 8 6 4 2 TEMPERATURE ( C) SUPPLY CURRENT vs. LOGIC LEVEL LOGIC LEVEL (V) = 5.5V.3.6.9 1.2 1.5 1.8 2.1 2.4 2.7 3. 3.3 1.2 1.1 _RISING 1..9.8.7.6.5.4.3.2.1 LOGIC-INPUT THRESHOLD vs. SUPPLY VOLTAGE _FALLING 2.8 3.1 3.4 3.7 4. 4.3 4.6 4.9 5.2 5.5 (V) MAX14566E toc4 MAX14566E toc6 MAX14566E toc8 ICC (µa) TURN-ON/TURN-OFF TIME (µs) 6 5 4 3 2 1 = SUPPLY CURRENT vs. SUPPLY VOLTAGE 2.8 3.1 3.4 3.7 4. 4.3 4.6 4.9 5.2 5.5 (V) T A = +25 C T A = -4 C TURN-ON/TURN-OFF TIME vs. SUPPLY VOLTAGE (V) T A = +85 C 24 22 2 18 16 14 12 1 t ON 8 6 t OFF 4 2 2. 2.5 3. 3.5 4. 4.5 5. 5.5 6. AUTODETECTION MODE MAX14566E toc9 = 5., /DM HIGH IMPEDANCE, LOGIC 1 TO LOGIC 1µs/div MAX14566E toc5 MAX14566E toc7 1V/div DM 1V/div 2V/div 7
Typical Operating Characteristics (continued) ( = 5V, T A = +25NC, unless otherwise noted.) AUTODETECTION MODE MAX14566E toc1 = 5., /DM HIGH IMPEDANCE TO.5V AT DM MAX14566AE 1ms/div AUTO RESET 2s/div MAX14566E toc12 5mV/div DM 5mV/div 2V/div 5mV/div DIFFERENTIAL SIGNAL (V).5.4.3.2.1 -.1 -.2 -.3 -.4 -.5 MAX14566E AUTO RESET 2s/div EYE DIAGRAM HI-SPEED TRANSMIT TEMPLATE MAX14566E toc11.2.4.6.8 1. 1.2 1.4 1.6 1.8 2. TIME (x 1 n - 9)s MAX14566E toc13 2V/div 2V/div 8
TOP VIEW TDM T 8 7 6 5 MAX14566E MAX14566AE 1 2 3 4 () DM TDFN (2mm 2mm) Host Charger Identification ( ) FOR MAX14566AE ONLY *CONNECT EP TO. PIN *EP MAX14566E MAX14566AE MAX14566BE NAME 1 1 TOP VIEW TDM T 8 7 6 5 MAX14566BE 1 2 3 4 1 DM TDFN (2mm 2mm) Pin Configuration *EP FUNCTION Pin Description nmosfet Open-Drain Output, Current-Limit Switch (CLS) Control Output. If changes from logic to logic 1 or from logic 1 to logic, is low for 1s (typ). Active-Low pmosfet Open-Drain Output, Current-Limit Switch (CLS) Control Output. If changes from logic to logic 1 or logic 1 to logic, is high for 1s (typ). 1 1 Switch Control Bit. See Table 2. 2 2 2 DM Connector D- Connection 3 3 3 Connector D+ Connection 4 4 4 Ground 5 5 5 Power Supply. Connect a.1ff capacitor between and as close as possible to the device. 6 6 6 T Host Transceiver D+ Connection 7 7 7 TDM Host Transceiver D- Connection 8 8 8 Switch Control Bit. See Table 1. = logic, charger mode = logic 1 (PM), pass-through mode active, /DM connected to T/TDM EP Exposed Pad. Connect EP to ground. Do not use EP as the only ground connection. 9
T TDM 1* RP1 RP2 ( ) FOR MAX14566AE ONLY *FOR MAX14566BE ONLY RM1 RM2 Detailed Description The are Hi-Speed analog switches that support hosts to identify the port as a charger port when the host is in a low-power mode and cannot enumerate devices. These devices feature high-performance Hi-Speed switches with low 4pF (typ) on-capacitance and low 4I (typ) on-resistance. and DM can handle signals between and 6V with any supply voltage. Resistor-Dividers All the devices feature an internal resistor-divider for biasing data lines to provide support for Apple-compliant devices. When these devices are not operated with the resistor-divider, they disconnect the resistor-dividers.46 DM1 CONTROL LOGIC ONE SHOT MAX14566E MAX14566AE MAX14566BE.46 DM2 1s.7 Functional Diagram 5kI V BIAS from the supply voltage to minimize supply current requirements. The resistor-dividers are not connected in pass-through mode. Switch Control The MAX14566E/MAX14566AE feature a single digital input,, for mode selection (Table 1). Connect to a logic-level low voltage for autodetection charger mode (AM). See the Autodetection section for more information. Connect to a logic-level high voltage for normal high-speed pass-through mode (PM). The MAX14566BE features dual digital inputs, and 1, for mode selection (Table 2). Connect to a logic-level high for normal high-speed pass-through mode (PM). Connect to a logic-level low for different charger-mode selection DM () 1
with 1. Connect 1 to a logic-level low for auto mode (AM) or connect 1 to a logic-level high for forced dedicated-charger mode (FM). Autodetection All the devices feature autodetection charger mode for dedicated chargers and masters. must be set low to activate autodetection charger mode. In autodetection charger mode, the MAX14566E monitors the voltages at DM and to determine the type of the device attached. If the voltage at DM is +2.3V (typ) or higher and the voltage at is +2.3V (typ) or lower, the voltage stays unchanged. If the voltage at DM is forced below the +2.3V (typ) threshold, the internal switch disconnects DM and Table 1. Digital Input State (MAX14566E/MAX14566AE) from the resistor-divider and and DM are shorted together for dedicated charging mode. If the voltage at is forced higher than the +2.3V (typ) threshold, the internal switch disconnects DM and from the resistor-divider and and DM are shorted together for dedicated charging mode. Once the charging voltage is removed, the short between and DM is disconnected for normal operation. Automatic Peripheral Reset The MAX14566E/MAX14566AE feature automatic currentlimit switch control output. This feature resets the peripheral connected to VBUS in the event the host switches to or from standby mode. / provide a 1s (typ) pulse on the rising or falling edge of (Figures 4, 5, and 6). MODE /DM COMMENT INTERNAL RESISTOR-DIVIDER AM Autodetection Circuit Active Auto Mode Connected 1 PM Connected to T/TDM Traffic Active Not Connected Table 2. Digital Input State (MAX14566BE) 1 MODE STATUS AM Auto Mode 1 FM Forced Dedicated-Charger Mode: /DM Shorted 1 X PM Pass-Through () Mode: Connect /DM to T/TDM X = Don't care. PERIPHERAL STANDBY AM ATTACH PM AM PM t VBT 5V CONNECTION CHARGING CURRENT 1mA 5mA 1mA 5mA 1mA Figure 4. MAX14566E Peripheral Reset Timing Diagram 11
TRANSCEIVER TDM T MAX14566E Figure 5. MAX14566E Peripheral Reset Applications Diagram PERIPHERAL STANDBY DM.1µF ATTACH 15µF PM D+ D- CONNECTION CURRENT-LIMIT SWITCH EN 1kI CLS EN SYSTEM CONTROL STANDBY PM +5V POWER SUPPLY AM AM t VBT 5V CONNECTION CHARGING CURRENT 1mA 5mA 1mA 5mA 1mA Figure 6. MAX14566AE Peripheral Reset Timing Diagram 12
TRANSCEIVER TDM T MAX14566AE Figure 7. MAX14566AE Discharge Circuit Bus Voltage Discharge The MAX14566AE automatic current-limit switch control output can be used to discharge the VBUS during VBUS reset. When the system controls the current-limit switch for VBUS toggle, the output capacitor can be discharged slowly depending upon the load. If fast discharge of the VBUS capacitor is desired, the output can be used to achieve the fast discharge as shown in Figure 7. Data Contact Detect All the devices support devices that require detecting the data lines prior to charging. When a Revision 1.2-compliant device is attached, the data lines and DM are shorted together. The short remains until it is detected by the device. This feature guarantees appropriate charger detection if a Revision 1.2-compliant device is attached. The autodetection charger mode is activated after the data contact detect DM.1µF 1kI 15µF D+ D- CONNECTION CURRENT-LIMIT SWITCH EN 1kI CLS EN SYSTEM CONTROL STANDBY +5V POWER SUPPLY is established. must be set low to activate data contact detect. ESD Test Conditions ESD performance depends on a variety of conditions. Contact Maxim for a reliability report that documents test setup, test methodology, and test results. Extended ESD Protection (Human Body Model) ESD-protection structures are incorporated on all pins to protect against electrostatic discharges up to Q2kV (HBM) encountered during handling and assembly. and DM are further protected against ESD up to Q15kV (HBM) without damage. The ESD structures withstand high ESD both in normal operation and when the device is powered down. After an ESD event, the device continues to function without latchup (Figure 8). 13
Host Charger Identification HIGH- VOLTAGE DC SOURCE R C 1MΩ CHARGE-CURRENT- LIMIT RESISTOR C S 1pF R D 1.5kΩ DISCHARGE RESISTANCE STORAGE CAPACITOR TRANSCEIVER TDM TDM T T MAX14566BE DM 1 Typical Application Circuit (MAX14566BE).1µF DEVICE UNDER TEST 15µF D+ D- CURRENT-LIMIT SWITCH AM/FM PM CONNECTION I PEAK (AMPS) 1% 9% 36.8% 1% SYSTEM CONTROL t RL +5V POWER SUPPLY EN EN I r t DL PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE) TIME Figure 8a. Human Body ESD Test Model Figure 8b. Human Body Current Waveform PROCESS: BiCMOS Chip Information Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a +, #, or - in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 8 TDFN-EP T822+1 21-168 9-64 14
REVISION NUMBER REVISION DATE DESCRIPTION Revision History PAGES CHANGED 1/1 Initial release 1 3/11 Changed the Battery Charging Specification Revision 1.1 to Revision 1.2 1, 13 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated Products, 12 San Gabriel Drive, Sunnyvale, CA 9486 48-737-76 15 211 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.