ECE 2035 Programming HW/SW Systems Fall problems, 7 pages Exam Two 23 October 2013

Similar documents
ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam Two 23 October Your Name (please print clearly) Signed.

ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam Two 21 October 2016

ECE 2035 Programming HW/SW Systems Spring problems, 6 pages Exam Two 11 March Your Name (please print) total

ECE 2035 Programming Hw/Sw Systems Fall problems, 10 pages Final Exam 9 December 2013

Q1: /30 Q2: /25 Q3: /45. Total: /100

ECE 2035 Programming HW/SW Systems Spring problems, 6 pages Exam One 4 February Your Name (please print clearly)

ECE 2035 A Programming Hw/Sw Systems Fall problems, 8 pages Final Exam 8 December 2014

ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam One 19 September 2012

ECE 2035 A Programming Hw/Sw Systems Fall problems, 10 pages Final Exam 14 December 2016

ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam One 22 September Your Name (please print clearly) Signed.

ECE 2035 A Programming Hw/Sw Systems Spring problems, 8 pages Final Exam 29 April 2015

ECE 2035 Programming HW/SW Systems Spring problems, 6 pages Exam Three 10 April 2013

ECE 2035 A Programming Hw/Sw Systems Fall problems, 8 pages Final Exam 9 December 2015

MIPS Instruction Reference

F. Appendix 6 MIPS Instruction Reference

Question 0. Do not turn this page until you have received the signal to start. (Please fill out the identification section above) Good Luck!

MIPS Reference Guide

Assembly Programming

Reduced Instruction Set Computer (RISC)

Week 10: Assembly Programming

Computer Architecture. The Language of the Machine

The MIPS Instruction Set Architecture

Reduced Instruction Set Computer (RISC)

TSK3000A - Generic Instructions

MIPS Instruction Set

SPIM Instruction Set

EEM 486: Computer Architecture. Lecture 2. MIPS Instruction Set Architecture

Computer Architecture. MIPS Instruction Set Architecture

MIPS ISA. 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support

101 Assembly. ENGR 3410 Computer Architecture Mark L. Chang Fall 2009

ECE 15B Computer Organization Spring 2010

CPS311 - COMPUTER ORGANIZATION. A bit of history

ECE232: Hardware Organization and Design. Computer Organization - Previously covered

Mips Code Examples Peter Rounce

Overview. Introduction to the MIPS ISA. MIPS ISA Overview. Overview (2)

MIPS Instruction Format

MIPS%Assembly% E155%

ECE Exam I February 19 th, :00 pm 4:25pm

MIPS Assembly Language. Today s Lecture

Today s Lecture. MIPS Assembly Language. Review: What Must be Specified? Review: A Program. Review: MIPS Instruction Formats

CS 61c: Great Ideas in Computer Architecture

Mark Redekopp, All rights reserved. EE 357 Unit 11 MIPS ISA

Instruction Set Architecture of. MIPS Processor. MIPS Processor. MIPS Registers (continued) MIPS Registers

Arithmetic for Computers

Outline. EEL-4713 Computer Architecture Multipliers and shifters. Deriving requirements of ALU. MIPS arithmetic instructions

ECE 2035 A Programming Hw/Sw Systems Fall problems, 10 pages Final Exam Solutions 14 December 2016

ENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5

Programming the processor

5/17/2012. Recap from Last Time. CSE 2021: Computer Organization. The RISC Philosophy. Levels of Programming. Stored Program Computers

Recap from Last Time. CSE 2021: Computer Organization. Levels of Programming. The RISC Philosophy 5/19/2011

M2 Instruction Set Architecture

Midterm. Sticker winners: if you got >= 50 / 67

CSc 256 Midterm 2 Spring 2012

Examples of branch instructions

Lec 10: Assembler. Announcements

CSc 256 Midterm 2 Fall 2011

CISC 662 Graduate Computer Architecture. Lecture 4 - ISA MIPS ISA. In a CPU. (vonneumann) Processor Organization

Flow of Control -- Conditional branch instructions

Chapter 2. Computer Abstractions and Technology. Lesson 4: MIPS (cont )

CSc 256 Midterm (green) Fall 2018

CISC 662 Graduate Computer Architecture. Lecture 4 - ISA

Part II Instruction-Set Architecture. Jan Computer Architecture, Instruction-Set Architecture Slide 1

MACHINE LANGUAGE. To work with the machine, we need a translator.

Concocting an Instruction Set

University of California at Santa Barbara. ECE 154A Introduction to Computer Architecture. Quiz #1. October 30 th, Name (Last, First)

CS61c MIDTERM EXAM: 3/17/99

ICS DEPARTMENT ICS 233 COMPUTER ARCHITECTURE & ASSEMBLY LANGUAGE. Midterm Exam. First Semester (141) Time: 1:00-3:30 PM. Student Name : _KEY

MIPS Assembly Language

A General-Purpose Computer The von Neumann Model. Concocting an Instruction Set. Meaning of an Instruction. Anatomy of an Instruction

INSTRUCTION SET COMPARISONS

Review. Lecture #9 MIPS Logical & Shift Ops, and Instruction Representation I Logical Operators (1/3) Bitwise Operations

ECE468 Computer Organization & Architecture. MIPS Instruction Set Architecture

EE 109 Unit 13 MIPS Instruction Set. Instruction Set Architecture (ISA) Components of an ISA INSTRUCTION SET OVERVIEW

Review of Activation Frames. FP of caller Y X Return value A B C

CSc 256 Final Fall 2016

Computer Architecture Experiment

CSCI 402: Computer Architectures. Instructions: Language of the Computer (3) Fengguang Song Department of Computer & Information Science IUPUI.

We will study the MIPS assembly language as an exemplar of the concept.

CMPE324 Computer Architecture Lecture 2

Assembly Language. Prof. Dr. Antônio Augusto Fröhlich. Sep 2006

Computer Architecture Instruction Set Architecture part 2. Mehran Rezaei

Review: MIPS Organization

Concocting an Instruction Set

MIPS ISA and MIPS Assembly. CS301 Prof. Szajda

Number Systems and Their Representations

ece4750-parc-isa.txt

ECE 30 Introduction to Computer Engineering

Computer Organization & Design

EE 109 Unit 8 MIPS Instruction Set

Mark Redekopp, All rights reserved. EE 352 Unit 3 MIPS ISA

MIPS Coding Snippets. Prof. James L. Frankel Harvard University. Version of 9:32 PM 14-Feb-2016 Copyright 2016 James L. Frankel. All rights reserved.

Exam in Computer Engineering

CSc 256 Final Spring 2011

Instruction Set Architecture part 1 (Introduction) Mehran Rezaei

2. dead code elimination (declaration and initialization of z) 3. common subexpression elimination (temp1 = j + g + h)

CS3350B Computer Architecture MIPS Instruction Representation

Branch Addressing. Jump Addressing. Target Addressing Example. The University of Adelaide, School of Computer Science 28 September 2015

Announcements. EE108B Lecture MIPS Assembly Language III. MIPS Machine Instruction Review: Instruction Format Summary

CS 351 Exam 2 Mon. 11/2/2015

Kernel Registers 0 1. Global Data Pointer. Stack Pointer. Frame Pointer. Return Address.

Transcription:

Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate the pages of the exam. For maximum credit, show your work. Good Luck! Your Name (please print) 1 2 3 4 total 28 20 16 36 100 1

Problem 1 (2 parts, 28 points) Storage Allocation and Pointers In the following problems, assume all data types are word aligned. Pay attention to the word size, which is different in each part. Part A (8 points) Assuming a 64-bit operating system, show how the following global variables map into static memory. Assume they are allocated starting at address 3000. For each variable, draw a box showing its size and position in memory. Label the box with the variable name. Label each element of an array (e.g., Name[0]). 3000 float f = 2.0; double B[] = {3.14, 6.28; float *fp = &f; double *dp = B; 3004 3008 3012 3016 3020 3024 3028 3032 3036 3040 3044 3048 Part B (20 points) For this part, assume a 32-bit operating system. Suppose the following variables are allocated beginning at address 4000. Complete the table below, listing the value of the expression following this definition. int x = 8; int y = 9; double D = 6.25; double E = 9.33; int A[3] = {17, 6, 5; int *P = A+1; double *Q = &D; float w = 7.5; *(P-1) *(A+2) P+1 &(A[1]) A Q Q++ &w 2

Problem 2 (1 part, 20 points) Parameter Passing Consider the following C code fragment. Foo is called by main. int main() { int x = 100, V[] = {10, 3, 5, 6; float F[] = {3.14, 5.25; int y=25, d; int *z = &y; <more code here> d = Foo(x, F, F[0], V, z); <more code here> int Foo (int a, float *b, float c, int *S, int *g) { <Foo's code goes here> For each statement from Foo below, list the resulting value. If the result is an address, just list address. Also determine if it affects Foo s activation frame variables, main s activation frame variables, or both. Consider each statement independently and non-cumulatively (i.e., as if it is the only statement in Foo). statement in Foo result (assigned value) modify Foo s AF variables modify main s AF variables c = *b + 3.0; Yes No Yes No a *= 3; Yes No Yes No *g = *g + S[2]; Yes No Yes No S[1] += 2; Yes No Yes No b++; Yes No Yes No 3

Problem 3 (2 parts, 16 points) Array Access Part A (4 points) Suppose a 64x64 image array is stored in memory as in Project 1: each pixel is represented by 1 byte of storage. Each row of pixels is stored contiguously, one after another. Suppose register $4 holds the linear offset into the array (i.e., it would be added to the base address of the image array to access a particular pixel). Write a MIPS code fragment that computes the row and column number and places the row number into $5 and the column number into $6. For 3 bonus points, use only 2 instructions. Label Instruction Comment Part B (12 points) Write the MIPS code implementation of the dynamically allocated array access below in the smallest number of instructions. A pointer to the array (declared below) is stored in $3. Variables X, Y, Z, and R reside in $4, $5, $6, and $2 respectively. Modify only registers $1 and $2. int Array[4][3][32]; /* array declaration */ R = Array[Z][Y][X]; /* implement this */ Label Instruction Comment 4

Problem 4 (2 parts, 36 points) Consider the following C code fragment: typedef struct { int x; int y; pair; Activation Frames int Bar() { int M = 3; int N = 4; pair P; int Q[] = {10, 20, 30; int Foo(int, pair *, int *); P.x = 5; P.y = 6; N = Foo(M, &P, Q); return(n); int Foo(int A, pair *B, int *C) { int D = 25; int E; C[2] = C[1] + A; E = B->y + D; return(e); Part A (20 points) Describe the current state of the stack just before Foo returns to Bar. Fill in the unshaded boxes to show Bar s and Foo s activation frames. Include a symbolic description and the actual value (in decimal). For return addresses, show only the symbolic description; do not include a value. Label the frame pointer and stack pointer. address description Value 9900 RA of Bar s caller 9896 FP of Bar s caller SP, Bar s FP 9892 9888 9884 9880 9876 9872 9868 9864 9860 9856 9852 9848 9844 9840 9836 9832 5

Part B (16 points) Write MIPS code fragments to implement the subroutine Foo by following the steps below. Do not use absolute addresses in your code; instead, access variables relative to the frame pointer. Assume no parameters are present in registers (i.e., access all parameters from Foo s activation frame). First, write code to properly set Foo s frame pointer and to allocate space for Foo s local variables and initialize them if necessary. C[2] = C[1] + A; E = B->y + D; return(e); (compute return value, deallocate locals, and return) 6

MIPS Instruction Set (core) instruction example meaning arithmetic add add $1,$2,$3 $1 = $2 + $3 subtract sub $1,$2,$3 $1 = $2 - $3 add immediate addi $1,$2,100 $1 = $2 + 100 add unsigned addu $1,$2,$3 $1 = $2 + $3 subtract unsigned subu $1,$2,$3 $1 = $2 - $3 add immediate unsigned addiu $1,$2,100 $1 = $2 + 100 set if less than slt $1, $2, $3 if ($2 < $3), $1 = 1 else $1 = 0 set if less than immediate slti $1, $2, 100 if ($2 < 100), $1 = 1 else $1 = 0 set if less than unsigned sltu $1, $2, $3 if ($2 < $3), $1 = 1 else $1 = 0 set if < immediate unsigned sltui $1, $2, 100 if ($2 < 100), $1 = 1 else $1 = 0 multiply mult $2,$3 Hi, Lo = $2 * $3, 64-bit signed product multiply unsigned multu $2,$3 Hi, Lo = $2 * $3, 64-bit unsigned product divide div $2,$3 Lo = $2 / $3, Hi = $2 mod $3 divide unsigned divu $2,$3 Lo = $2 / $3, Hi = $2 mod $3, unsigned transfer move from Hi mfhi $1 $1 = Hi move from Lo mflo $1 $1 = Lo load upper immediate lui $1,100 $1 = 100 x logic and and $1,$2,$3 $1 = $2 & $3 or or $1,$2,$3 $1 = $2 $3 and immediate andi $1,$2,100 $1 = $2 & 100 or immediate ori $1,$2,100 $1 = $2 100 nor nor $1,$2,$3 $1 = not($2 $3) xor xor $1, $2, $3 $1 = $2 $3 xor immediate xori $1, $2, 255 $1 = $2 255 shift shift left logical sll $1,$2,5 $1 = $2 << 5 (logical) shift left logical variable sllv $1,$2,$3 $1 = $2 << $3 (logical), variable shift amt shift right logical srl $1,$2,5 $1 = $2 >> 5 (logical) shift right logical variable srlv $1,$2,$3 $1 = $2 >> $3 (logical), variable shift amt shift right arithmetic sra $1,$2,5 $1 = $2 >> 5 (arithmetic) shift right arithmetic variable srav $1,$2,$3 $1 = $2 >> $3 (arithmetic), variable shift amt memory load word lw $1, 1000($2) $1 = memory [$2+1000] store word sw $1, 1000($2) memory [$2+1000] = $1 load byte lb $1, 1002($2) $1 = memory[$2+1002] in least sig. byte load byte unsigned lbu $1, 1002($2) $1 = memory[$2+1002] in least sig. byte store byte sb $1, 1002($2) memory[$2+1002] = $1 (byte modified only) branch branch if equal beq $1,$2,100 if ($1 = $2), PC = PC + 4 + (100*4) branch if not equal bne $1,$2,100 if ($1 $2), PC = PC + 4 + (100*4) jump jump j 10000 PC = 10000*4 jump register jr $31 PC = $31 jump and link jal 10000 $31 = PC + 4; PC = 10000*4 7