Hall Ticket Number: 14 CS/IT 503 November, 2017 Fifth Semester Time: Three Hours Answer Question No.1 compulsorily. Answer ONE question from each unit. II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION Information Technology Microprocessors and Microcontrollers Maximum : 60 Marks (1X12 = 12 Marks) (4X12=48 Marks) 1. Answer all questions (1X12=12 Marks) a) What is the function of the accumulator? b) Why are the program counter and the stack pointer 16-bit registers? c) What is MACRO? d) What is an interrupt? e) What is BHE? f) What is the maximum memory size that can be addressed by 8086? g) Give the additional features of 8259A controller? h) Write about CALL statement in 8051? i) Write a program to perform multiplication of 2 no s using 8051? j) List the addressing modes of 8051? k) What is the difference between the Microprocessors and Microcontrollers? l) List at least 2 features of 8051 microcontroller. UNIT I 2. a) Write an ALP in 8086 to find a maximum number in the array of 10 numbers b) Explain the different string Manipulation instructions of 8086 microprocessor (OR) 3. a) Differentiate between procedures and macros with examples b) Develop a program to arrange ten bytes of data in descending order UNIT II 4. a) Describe the functions of the following pins of 8086 i). NMI ii). CLK iii). BHE/S7 b) With a neat timing diagram explain how a I/O READ operation is performed by 8086 (OR) 5. a) Explain the maximum mode operation of 8086 b) Explain Micro Computer system architecture with a neat diagram. UNIT III 6. a) Explain the internal architecture of 8259 8M b) Discuss the procedure for processing of interrupts by 8259 4M (OR) 7. a) Explain LOOP, JUMP instructions in 8051 b) With a neat block diagram explain the working of 8237 DMA controller. UNIT IV 8. a) Explain the addressing modes of 8051 with suitable examples b) Write about programmable Timers in the MCU s (OR) 9. a) Describe the interrupt structure of the 8051 microcontroller b) Draw the architectural diagram of 8051 microcontroller and explain in detail about each block
14 CS/IT 503 II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION November, 2017 Fifth Semester Time: Three Hours Answer Question No.1 compulsorily. Answer ONE question from each unit. Answer Question No.1 compulsorily. Scheme Information Technology Microprocessors and Microcontrollers Maximum : 60 Marks (1X12 = 12 Marks) (4X12=48 Marks) (1X12 = 12 Marks) a) What is the function of the accumulator? Functionality of Accumulator 1M An accumulator is a register for short-term, intermediate storage of arithmetic and logic data in a computer's CPU (central processing unit).... In a modern computers, any register can function as an accumulator. The most elementary use for an accumulator is adding a sequence of numbers. b) Why are the program counter and the stack pointer 16-bit registers? Explanation 1M Program Counter (PC) and Stack Pointer (SP) are basically used to hold 16-bit memory addresses.pc stores the 16-bit memory address of the next instruction to be fetched.sp can be used to temporarily store the 16-bit memory address as well as data.so PC & SP are 16-bit registers. 8 bit address can only locate/address 256 memory locations. 16 bit address can locate up to 64kb. Even if 8 bit system can have more than 256 bytes of Ram/Rom/Flash (say whatever). And hence the need of 16 bit PC & SP instead of 8 bits. Data registers or data bus could be just 8 bits still. c) What is MACRO? Definition 1M When the repeated group of instruction is too short or not suitable to be implemented as a procedure,we use a MACRO. A macro is a group of instructions to which a name is given. Each time a macro is called in a program, the assembler will replace the macro name with the group of instructions. d) What is an interrupt? Definition 1M Interrupt is a signal send by an external device to the processor, to the processor to perform a particular task or work. Mainly in the microprocessor based system the interrupts are used for data transfer between the peripheral and the microprocessor. e) What is BHE? Definition 1M BUS HIGH ENABLE : During T1 the bus high enable signal (BHE) should be used to enable data onto the most significant half of the data bus, pins D15±D8. Eight-bit oriented devices tied to the upper half of the bus would normally use BHE to condition chip select functions. BHE is LOW during T1 for read, write, and interrupt acknowledge cycles when a byte is to be transferred on the high portion of the bus. The S7 status information is available during T2, T3, and T4. The signal is active LOW, and floats to 3-state OFF in `hold''. It is LOW during T1 for the first interrupt acknowledge cycle. f) What is the maximum memory size that can be addressed by 8086? Max memory size 1M All internal registers, as well as internal and external data buses, are 16 bits wide, which firmly established the "16-bit microprocessor" identity of the 8086. A 20-bit external address bus provides a 1 MB physical address space (2 20 = 1,048,576) g) Give the additional features of 8259A controller? At least 2 features 1M The Intel 8259A Programmable Interrupt Controller handles up to eight vectored priority interrupts for the CPU. It is cascadable for up to 64 vectored priority interrupts without additional circuitry. It is packaged in a 28-pin DIP, uses NMOS technology and requires a single a5v supply. Circuitry is static, requiring no clock input.
h) Write about CALL statement in 8051? CALL statement 1M Another control transfer instruction is the CALL instruction, which is used to call a subroutine. Subroutines are often used to perform tasks that need to be performed frequently. This makes a program more structured in addition to saving memory space. In the 8051 there are two instructions for call: LCALL (long call) and ACALL (absolute call). Deciding which one to use depends on the target address. i) Write a program to perform multiplication of 2 no s using 8051? Program 1M org 00h mov r1,#3h mov r2,#2h mov a,r1 mov b,r2 mul ab end j) List the addressing modes of 8051? List of addressing modes 1M The CPU can access data in various ways, which are called addressing modes 1) Immediate 2) Register 3) Direct 4) Register indirect 5) Indexed k) What is the difference between the Microprocessors and Microcontrollers? At least 2 differences 1M Microprocessor Micro Controller Microprocessor is heart of Computer system. It is just a processor. Memory and I/O components have to be connected externally Micro Controller is a heart of embedded system. Micro controller has external processor along with internal memory and i/o components l) List at least 2 features of 8051 microcontroller. At least 2 features 1M 64KB Program Memory address space 64KB Data Memory address space 4K bytes of on-chip Program Memory 128 bytes of on-chip Data RAM 32 bidirectional and individually addressable I/0 lines Two 16-bit timer/counters
Answer ONE question from each unit. UNIT I (4X12=48 Marks) 2 a) Write an ALP in 8086 to find a maximum number in the array of 10 numbers data segment arr db 5h,4h,3h,2h,1h,Ah,8h,7h,9h,6h max db 1 dup(0) data ends code segment assume cs:code,ds:data start: mov ax,data mov ds,ax xor ax,ax lea si,arr mov cl,09h mov al,[si] mov max,al label1: inc si mov al,[si] cmp max,al jl swap dec cx jne label1 jmp label2 swap: xchg max,al dec cx jne label1 label2: mov ax,4c00h int 21h code ends end start Program b) Explain the different string Manipulation instructions of 8086 microprocessor List of string Manipulation instructions 2M
Explanation 4M (OR) 3 a) Differentiate between procedures and macros with examples At least 6 differences Defining procedures: Assembler provides PROC and ENDP directives in order to define procedures. The directive PROC indicates beginning of a procedure. Its general form is: Procedure_name PROC [NEAR FAR] NEAR FAR is optional and gives the types of procedure. If not used, assembler assumes the proce dure as near procedure. All procedures are defined in code segment. The directive ENDPindicates end of a procedure. Its general form is: Procedure_name ENDP For example, Factorial PROC NEAR...... Factorial ENDP
Defining macros: Before using macros, we have to define them. Macros are defined before the definition of segments.assembler provides two directives for defining a macro: MACRO and ENDM.MACRO directive informs the assembler the beginning of a macro. The general form is: Macro_name MACRO argument1, argument2, Arguments are optional. ENDM informs the assembler the end of the macro. Its general form is : ENDM b) Develop a program to arrange ten bytes of data in descending order Program DATA SEGMENT LIST DB 98H,52H,68H,32H,72H DATA ENDS CODE SEGMENT ASSUME CS:CODE,DS:DATA START: MOV AX,DATA MOV DS,AX XOR AX,AX MOV SI,OFFSET LIST MOV CL,04H L1: MOV DL,CL MOV SI,OFFSET LIST L2: MOV AL,[SI] CMP AL,[SI+1] JA L3 XCHG AL,[SI+1] XCHG AL,[SI] L3: INC SI DEC DL JNZ L2 DEC CL JNZ L1 INT 21H CODE ENDS END START Unit II 4 a) Describe the functions of the following pins of 8086 i). NMI ii). CLK iii). BHE/S7 i). NMI It stands for non-maskable interrupt and is available at pin 17. It is an edge triggered input, which causes an interrupt request to the microprocessor. This signal is like wait state and is available at pin 23. When this signal is high, then the processor has to wait for IDLE state, else the execution continues. ii). CLK Clock signal Clock signal is provided through Pin-19. It provides timing to the processor for operations. Its frequency is different for different versions, i.e. 5MHz, 8MHz and 10MHz. iii). BHE/S7 BHE stands for Bus High Enable. It is available at pin 34 and used to indicate the transfer of data using data bus D8-D15. This signal is low during the first clock cycle, thereafter it is active. 2M 2M 2M
b) With a neat timing diagram explain how a I/O READ operation is performed by 8086 Explanation of I/O READ operation 3M Asserts M/IO for reading from Memory or Port. Asserts ALE High to enable Address Latches. Sends desired address on A0-A19 pins. Asserts ALE Low to latch address on external latches. Removes the address from A0-A19 Asserts RD Low to output data into data bus. Assets READY Low to send 8086 into wait state. In Wait State, 8086 will wait for addressed memory or port to output data. Asserts Ready High to specify that addressed memory or port has placed data on data bus. DT/R is Low to specify that 8086 is receiving the data. DEN is Low to enable data buffers for transfer data from addressed memory or port to 8086. Timing diagram 3M (OR) 5 a) Explain the maximum mode operation of 8086 The following pin function descriptions are for the microprocessor 8086 in either minimum or maximum mode. AD0 - AD15 (I/O): Address Data Bus:These lines constitute the time multiplexed memory/io address during the first clock cycle (T1) and data during T2, T3 and T4 clock cycles. A0 is analogous to BHE for the lower byte of the data bus, pins D0-D7. A0 bit is Low during T1 state when a byte is
to be transferred on the lower portion of the bus in memory or I/O operations. 8-bit oriented devices tied to the lower half would normally use A0 to condition chip select functions. These lines are active high and float to tri-state during interrupt acknowledge and local bus "Hold acknowledge". A19/S6, A18/S5, A17/S4, A16/S3 (0): Address/Status :During T1 state these lines are the four most significant address lines for memory operations. During I/O operations these lines are low. During memory and I/O operations, status information is available on these lines during T2, T3, and T4 states.s5: The status of the interrupt enable flag bit is updated at the beginning of each cycle. The status of the flag is indicated through this bus. S6: When Low, it indicates that 8086 is in control of the bus. During a "Hold acknowledge" clock period, the 8086 tri-states the S6 pin and thus allows another bus master to take control of the status bus. S3 & S4: Lines are decoded as follows: A17/S4 A16/S3 Function 0 0 Extra segment access 0 1 Stack segment access 1 0 Code segment access 1 1 Data segment access BHE /S7 (O): Bus High Enable/Status: During T1 state the BHE should be used to enable data onto the most significant half of the data bus, pins D15 - D8. Eight-bit oriented devices tied to the upper half of the bus would normally use BHE to control chip select functions. BHE is Low during T1 state of read, write and interrupt acknowledge cycles when a byte is to be transferred on the high portion of the bus. RD (O): READ: The Read strobe indicates that the processor is performing a memory or I/O read cycle. This signal is active low during T2 and T3 states and the Tw states of any read cycle. This signal floats to tri-state in "hold acknowledge cycle". TEST (I): TEST pin is examined by the "WAIT" instruction. If the TEST pin is Low, execution continues. Otherwise the processor waits in an "idle" state. This input is synchronized internally during each clock cycle on the leading edge of CLK. INTR (I): Interrupt Request:It is a level triggered input which is sampled during the last clock cycle of each instruction to determine if the processor should enter into an interrupt acknowledge operation. NMI (I): Non-Maskable Interrupt: An edge triggered input, causes a type-2 interrupt. A subroutine is vectored to via the interrupt vector look up table located in system memory. NMI is not maskable internally by software. Reset (I): Reset causes the processor to immediately terminate its present activity. Ready (I):Ready is the acknowledgement from the addressed memory or I/O device that it will complete the data transfer. The READY signal from memory or I/O is synchronized by the 8284 clock generator to form READY. This signal is active HIGH. The 8086 READY input is not synchronized. Correct operation is not guaranteed if the setup and hold times are not met. CLK (I): Clock: Clock provides the basic timing for the processor and bus controller. It is asymmetric with 33% duty cycle to provide optimized internal timing. Minimum frequency of 2 MHz is required, since the design of 8086 processors incorporates dynamic cells. MN/MX (I): Maximum / Minimum: This pin indicates what mode the processor is to operate in. In minimum mode, the 8086 itself generates all bus control signals. In maximum mode the three status signals are to be decoded to generate all the bus control signals. Minimum Mode Pins The following 8 pins function descriptions are for the 8086 in minimum mode;
MN/ MX = 1. The corresponding 8 pins function descriptions for maximum mode is explained later. S2, S1, S0 (O): Status Pins: These pins are active during T4, T1 and T2 states and is returned to passive state (1,1,1 during T3 or Tw (when ready is inactive). These are used by the 8288 bus controller to generate all memory and I/O operation) access control signals. Any change by S2, S1, S0 during T4 is used to indicate the beginning of a bus cycle. These status lines are encoded as shown in table 3. S0, QS1 (O): Queue Status: Queue Status is valid during the clock cycle after which the queue operation is performed. QS0, QS1 provide status to allow external tracking of the internal 8086 instruction queue. LOCK :It indicates to another system bus master, not to gain control of the system bus while LOCK is active Low. The LOCK signal is activated by the "LOCK" prefix instruction and remains active until the completion of the instruction. This signal is active Low and floats to tri-state OFF during 'hold acknowledge'. RQ/GT0 and RQ/GT1 (I/O): Request/Grant These pins are used by other processors in a multi-processor organization. Local bus masters of other processors force the processor to release the local bus at the end of the processors current bus cycle. Each pin is bi-directional and has an internal pull up resistors. Hence they may be left unconnected. b) Explain Micro Computer system architecture with a neat diagram. A Microcomputer Fetches, Decodes, and Executes an instruction. Fetch Operation: The CPU sends address of required instruction to Memory (port) through address bus. Then Memory (Port) sends the instruction through data bus to the CPU. Decode: The CPU then decodes the instruction fetched from memory. Determines the set of actions. Selects the sequence of microinstructions to be carried out etc. Execute: Finally CPU performs the operation according to the instruction. Memory Read Memory to CPU. Memory Write CPU to Memory. Port Read I/O Port to CPU Port Write CPU to I/O Port
Unit III 6 a) Explain the internal architecture of 8259 Architectural Diagram of 8259 4M 8M Explanation 4M 1) When 2 interrupts come at a time to 8259 Interrupt inputs (IR0-IR7), the Highest priority will be for IR0 and Lowest priority will be for IR7. 2) Priority of Interrupts is based on the 4 blocks in 8259. They are 3) Interrupt Request Register (IRR): Keeps track of which interrupts are asking for service. 4) Interrupt Mask Register (IMR): Disable or enable individual interrupt inputs. 5) In-Service Register (ISR): Keeps track of which interrupts are being serviced. 6) Priority Resolver: Determines when an interrupt request on one of the IR input gets serviced. 8259 Functional Description 7) CS for enabling the device. 8) IR0-IR7 are Interrupt input pins. 9) WR for accepting command words from 8086. 10) RD for releasing status onto the data bus. 11) Cas2-cas0 are used to connect multiple 8259 devices. 12) INT is used to interrupt 8086 when an interrupt is generated in 8259. 13) INTA is used to enable the interrupt pointer onto the data bus. 14) A0 is connected to 8086 Address line A1. 15) SP /EN is used for Master Slave or Buffer Enable. b) Discuss the procedure for processing of interrupts by 8259 Procedure 4M 4M
(OR) 7 a) Explain LOOP, JUMP instructions in 8051 LOOP instructions 3M Repeating a sequence of instructions a certain number of times is called a loop Loop action is performed by DJNZ reg, Label The register is decremented If it is not zero, it jumps to the target address referred to by the label Prior to the start of loop the register is loaded with the counter for the number of repetitions Counter can be R0 R7 or RAM location. If we want to repeat an action more times than 256, we use a loop inside a loop, which is called nested loop We use multiple registers to hold the count Write a program to (a) load the accumulator with the value 55H, and (b) complement the ACC 700 times MOV A,#55H ;A=55H MOV R3,#10 ;R3=10, outer loop count NEXT: MOV R2,#70 ;R2=70, inner loop count AGAIN: CPL A ; complement A register DJNZ R2,AGAIN ; repeat it 70 times DJNZ R3,NEXT JUMP instructions 3M The unconditional jump is a jump in which control is transferred unconditionally to the target location LJMP (long jump) 3-byte instruction First byte is the opcode Second and third bytes represent the 16-bit target address Any memory location from 0000 to FFFFH SJMP (short jump) 2-byte instruction First byte is the opcode Second byte is the relative target address 00 to FFH (forward +127 and backward -128 bytes from the current PC) Department of Computer Science and Information Engineering National Cheng Kung University, TA
IWAN 8 HANEL b) With a neat block diagram explain the working of 8237 DMA controller. Block diagram of 8237 3M working of 8237 DMA controller 3M When DMA module needs buses it sends HOLD signal to processor CPU responds by HLDA (hold acknowledge) Then DMA module can use buses Steps for transfer data from Memory to I/O Device: 1. Device requests service of DMA by pulling DREQ (DMA request) high 2. DMA puts high on HRQ (hold request), 3. CPU finishes present bus cycle (not necessarily present instruction) and puts high on HDLA (hold acknowledge). HOLD remains active for duration of DMA 4. DMA activates DACK (DMA acknowledge), telling device to start transfer 5. DMA starts transfer by putting address of first byte on address bus and activating MEMR; 6. It then activates IOW to write to peripheral. DMA decrements counter and increments address pointer. Repeat until count reaches zero 7. DMA deactivates HRQ, giving bus back to CPU 8. DMA uses MEMW and IOR for I/O device read. Unit IV 8 a) Explain the addressing modes of 8051 with suitable examples List of addressing modes 2M 1. Immediate Addressing 2. Direct Addressing 3. Register Addressing 4. Register Indirect Addressing 5. Implied Addressing. Explanation 4M 1. IMMEDIATE ADDRESSING : In immediate addressing mode, an 8/16 bit immediate data / constant is specified in the instruction itself. MOV A, #6CH :- Move the immediate data 6CH given in the instruction to A-register. MOV DPTR, #0100H :- Load the immediate 16-bit constant given in the instruction in DPTR (Data pointer). This constant will be an address of data memory location. 2. DIRECT ADDRESSING : In direct addressing mode, the address of the data is directly specified in the instruction. The direct address can be the address of an internal data RAM location (00H to 7FH) or address of special function register (80H to FFH). MOV A, 07 H :- The address of R7 register of bank-0 is 07. This instruction will move the content of R7 register to A-register (Accumulator). 3.REGISTER ADDRESSING : In register addressing mode, the instruction will specify the name of register in which data available. MOV R2,A :- The content of A-register (accumulator) is moved to register R2. 4. REGISTER INDIRECT ADDRESSING : In this mode, the instruction specifies the name of the register in which the address of the data is available. The internal data RAM locations (00H to 7FH) can be addressed indirectly through registers R1 and R0. The external RAM can be addressed indirectly through DPTR. MOV A, @R0 :- The internal RAM Location R0 holds the address of data. The content of RAM location addressed by R0 is moved to A-register (Accumulator).
5. IMPLIED ADDRESSING : In implied addressing mode, the instruction itself specifies the data to be operated by the instruction. CPL C :- Complement carry flag. b) Write about programmable Timers in the MCU s The 8051 has two timers: timer0 and timer1. They can be used either as timers or as counters. Both timers are 16 bits wide. Since the 8051 has an 8-bit architecture, each 16-bit is accessed as two separate registers of low byte and high byte. First we shall discuss about Timer0 registers. Timer0 registers is a 16 bits register and accessed as low byte and high byte. The low byte is referred as a TL0 and the high byte is referred as TH0. These registers can be accessed like any other registers. Timer1 registers is also a 16 bits register and is split into two bytes, referred to as TL1 and TH1. TMOD (timer mode) Register: This is an 8-bit register which is used by both timers 0 and 1 to set the various timer modes. In this TMOD register, lower 4 bits are set aside for timer0 and the upper 4 bits are set aside for timer1. In each case, the lower 2 bits are used to set the timer mode and upper 2 bits to specify the operation. TMOD In upper or lower 4 bits, first bit is a GATE bit. Every timer has a means of starting and stopping. Some timers do this by software, some by hardware, and some have both software and hardware controls. The hardware way of starting and stopping the timer by an external source is achieved by making GATE=1 in the TMOD register. And if we change to GATE=0 then we do no need external hardware to start and stop the timers. The second bit is C/T bit and is used to decide whether a timer is used as a time delay generator or an event counter. If this bit is 0 then it is used as a timer and if it is 1 then it is used as a counter. In upper or lower 4 bits, the last bits third and fourth are known as M1 and M0 respectively. These are used to select the timer mode. Mode 1- It is a 16-bit timer; therefore it allows values from 0000 to FFFFH to be loaded into the timer s registers TL and TH. After TH and TL are loaded with a 16-bit initial value, the timer must be
started. We can do it by SETB TR0 for timer 0 and SETB TR1 for timer 1. Mode0- Mode 0 is exactly same like mode 1 except that it is a 13-bit timer instead of 16-bit. The 13-bit counter can hold values between 0000 to 1FFFH in TH-TL. Therefore, when the timer reaches its maximum of 1FFH, it rolls over to 0000, and TF is raised. Mode 2- It is an 8 bit timer that allows only values of 00 to FFH to be loaded into the timer s register TH. After TH is loaded with 8 bit value, the 8051 gives a copy of it to TL. Then the timer must be started. Mode3- Mode 3 is also known as a split timer mode. Timer 0 and 1 may be programmed to be in mode 0, 1 and 2 independently of similar mode for other timer. This is not true for mode 3; timers do not operate independently if mode 3 is chosen for timer 0. Placing timer 1 in mode 3 causes it to stop counting; the control bit TR1 and the timer 1 flag TF1 are then used by timer0. TCON register- Bits and symbol and functions of every bits of TCON are as follows: (OR) 9 a) Describe the interrupt structure of the 8051 microcontroller Interrupt definition 1M An interrupt is an external or internal event that interrupts the microcontroller to inform it that a device needs its service. interrupt Types 2M Six interrupts are allocated as follows Reset power-up reset Two interrupts are set aside for the timers: one for timer 0 and one for timer 1 Two interrupts are set aside for hardware external interrupts P3.2 and P3.3 are for the external Hardware interrupts INT0 (or EX1), and INT1 (or EX2) Serial communication has a single interrupt that belongs to both receive and transfer Interrupt service routine 3M For every interrupt, there must be an interrupt service routine (ISR), or interrupt handler When an interrupt is invoked, the microcontroller runs the interrupt service routine For every interrupt, there is a fixed location in memory that holds the address of its ISR The group of memory locations set aside to hold the addresses of ISRs is called interrupt vector table
b) Draw the architectural diagram of 8051 microcontroller and explain in detail about each block Architectural diagram of 8051 3M Following is the block diagram of Microcontroller 8051. Let us have a look at each part or block of this Architecture: Microcontroller 8051 - Block Diagram Explanation: 3M Central Processor Unit(CPU): As you may know that CPU is the brain of any processing device. It monitors and controls all operations that are performed in the Microcontroller. User have no control over the work of CPU. It reads program written in ROM memory and executes them and do the expected task. Interrupts: As its name suggests, Interrupt is a subroutine call that interrupts Microcontroller's main operation or work and causes it to execute some another program which is more important at that time. Memory: Microcontroller requires a program which is a collection of instructions. This program tells Microcontroller to do specific tasks. These programs requires a memory on which these can be saved and read by Microcontroller to perform specific operation. The memory which is used to store the program of Microcontroller, is known as code memory or Program memory. It is known as 'ROM'(Read Only Memory). Bus: Basically Bus is a collection of wires which work as a communication channel or medium for transfer of Data. These buses consists of 8, 16 or more wires. Thus these can carry 8 bits, 16 bits simultaneously. Buses are of two types: Address Bus: Microcontroller 8051 has a 16 bit address bus. It used to address memory locations. It is used to transfer the address from CPU to Memory. Data Bus: Microcontroller 8051 has 8 bits data bus. It is used to carry data. Oscillator: As we know Microcontroller is a digital circuit device, therefore it requires clock for its operation. For this purpose, Microcontroller 8051 has an on-chip oscillator which works as a clock source for Central Processing Unit. As the output pulses of oscillator are stable therefore it enables synchronized work of all parts of 8051 Microcontroller. Input/Output Port: As we know that Microcontroller is used in Embedded systems to control the operation of machines. Therefore to connect it to other machines, devices or peripherals we requires I/O interfacing ports in Microcontroller. Timers/Counters: Microcontroller 8051 has 2 16 bit timers and counters. The counters are divided into 8 bit registers. The timers are used for measurement of intervals, to determine pulse width etc.