White Electronic Desig 512Kx8 STATIC RAM CMOS, MODULE FEATURES 512Kx8 bit CMOS Static Random Access Memory Access Times 2 through 1 Data Retention Function (EDI8F8512LP) TTL Compatible Inputs and Outputs Fully Static, No Clocks High Deity Packaging 6 Pin SIP, No. 6 2 Pin DIP, JEDEC Pinout, No. 91 (55-1) 2 Pin DIP, JEDEC Pinout, No. 18 (2-5) Single +5V (±1%) Supply Operation *This product is subject to change without notice. DESCRIPTION The is a 496K bit CMOS Static RAM based on four 128Kx8 or 256Kx4 (high speed) Static RAMs mounted on a multilayered epoxy laminate (FR4) substrate. Functional equivalence to the monolithic four megabit Static RAM is achieved by utilization of an on-board decoder that interprets the higher order address(es) to select one of the128kx8 or 256Kx4 Static RAMs. The 2 pin DIP pinout adheres to the JEDEC stan dard for the four megabit device, to en sure compatibility with future monolithics. A low power version with data retention (EDI8F8512LP) is also available. All inputs and outputs are TTL compatible and op er ate from a single 5V supply. Fully asyn chro nous, the requires no clocks or refreshing for operation. FIG. 1 PIN CONFIGURATIONS NC DQ2 DQ DQ A1 A2 A A4 VSS DQ5 A1 A11 A5 A1 A14 NC A A16 A12 A18 A6 DQ1 VSS A A7 A8 A9 DQ7 DQ4 DQ6 A17 1 2 4 5 6 7 8 9 1 11 12 1 14 16 17 18 19 2 21 22 2 24 25 26 27 28 29 1 2 4 5 6 A18 A16 A14 A12 A7 A6 A5 A4 A A2 A1 A DQ DQ1 DQ2 VSS 1 2 4 5 6 7 8 9 1 11 12 1 14 16 8F8512C Pin Config 2 1 29 28 27 26 25 24 2 22 21 2 19 18 17 A A17 A1 A8 A9 A11 A1 DQ7 DQ6 DQ5 DQ4 DQ PIN NAMES A-A18 Address Inputs Chip Enable Write Enable Output Enable DQ-DQ7 Common Data Input/Output Power (+5V±1%) VSS Ground NC No Connection 8F8512C Pin Config. White Electronic Desig Corp. reserves the right to change products or specifi catio without notice. July 22 1 White Electronic Desig Corporation (62) 47-2 www.whiteedc.com
White Electronic Desig FIG. 2 BLOCK DIAGRAMS A-16 128K x 8 A-17 256K x 4 DQ- 128K x 8 256K x 4 DQ4-7 DQ-7 128K x 8 256K x 4 128K x 8 256K x 4 55-1 2-5 A17-A18 DECODER A18 DECODER 8F8512C Blk Dia 8F8512C Blk Dia2 White Electronic Desig Corp. reserves the right to change products or specifi catio without notice. July 22 2 White Electronic Desig Corporation (62) 47-2 www.whiteedc.com
White Electronic Desig ABSOLUTE MAXIMUM RATINGS* Voltage on any pin relative to VSS -.5V to 7.V Operating Temperature TA (Ambient) Commercial C to +7 C Industrial -4 C to +85 C Storage Temperature -55 C to +125 C Power Dissipation 4 Watt Output Current 2 ma *Stress greater than those listed under Ab so lute Maxi mum Ratings may cause permanent damage to the device. This is a stress rating only and functional op era tion of the device at these or any other conditio greater than those in di cated in the operational sectio of this speci fication is not im plied. Ex po sure to ab so lute maxi mum rating con di tio for ex tended periods may affect re lia bil ity. RECOMMENDED DC OPERATING CONDITIONS Parameter Sym Min Typ Max Units Supply Voltage 4.5 5. 5.5 V Supply Voltage VSS V Input High Voltage VIH 2.2 6. V Input Low Voltage VIL -..8 V AC TEST CONDITIONS Input Pulse Levels VSS to.v Input Rise and Fall Times 5 Input and Output Timing Levels 1.5V Output Load 2-5 1TTL = pf 7-1 1TTL, CL = 1pF (Note: For tehqz, tghqz and twlqz, CL = 5pF) *Typical: TA = 25 C, = 5.V DC ELECTRICAL CHARACTERISTICS Parameter Sym Conditio Min Typ* Max Units 5 55 2-25 5 55-1 Operating Power Supply Current ICC1, = VIL, II/O = ma, Min Cycle 4 7 57 9 1 ma Standby (TTL) Power Supply Current Full Standby Power Supply Current (CMOS) ICC2 ICC VIH, VIN VIL VIN VIH -.2V VIN -.2V or VIN.2V Input Leakage Current ILI VIN = V to ±1 ±1 ±1 μa Output Leakage Current ILO V I/O = V to ±1 ±1 ±1 μa Output High Voltage VOH IOH = -1.mA ( 7), or -4. ( 5) 2.4 V Output Low Voltage VOL IOL = 2.1mA ( 7), or 8.mA ( 5).4.4.4 V DIP SIP C LP 5 5 1 2 4 85 4 85 4 55 5 4 ma ma μa TRUTH TABLE Mode Output Power X H X Standby HIGH Z ICC2/ICC H L H Output Deselect HIGH Z ICC1 L L H Read DOUT ICC1 X L L Write DIN ICC1 CAPACITANCE (f=1.mhz, VIN= or VSS) Parameter Sym Max Unit Address Lines CI pf Data Lines CD/Q 4 pf Chip Enable Line CC 1 pf Write and Output Enable Lines CW 2 pf These parameters are sampled, not 1% tested. White Electronic Desig Corp. reserves the right to change products or specifi catio without notice. July 22 White Electronic Desig Corporation (62) 47-2 www.whiteedc.com
White Electronic Desig AC CHARACTERISTICS READ CYCLE Symbol 2 25 5 Parameter JEDEC Alt. Min. Max. Min. Max. Min. Max. Units Read Cycle Time tavav trc 2 25 5 Address Access Time tavqv taa 2 25 5 Chip Enable Access Time telqv tacs 2 25 5 Chip Enable to Output in Low Z (1) telqx tclz Chip Disable to Output in High Z (1) tehqz tchz 1 12 Output Hold from Address Change tavqx toh Output Enable to Output Valid tglqv toe 1 2 Output Enable to Output in Low Z (1) tglqx tolz Output Disable to Output in High Z (1) tghqz tohz 8 1 12 Note: Parameter guaranteed, but not tested. FIG. READ CYCLE 1 - HIGH,, LOW tavav A ADDRESS 1 ADDRESS 2 tavqv tavqx Q DATA 1 DATA 2 8F8512C Rd Cyc1 FIG. 4 READ CYCLE 2 - HIGH tavav A tavqv telqx telqv tehqz tglqv tghqz Q tglqx 8F8512C Rd Cyc2 White Electronic Desig Corp. reserves the right to change products or specifi catio without notice. July 22 4 White Electronic Desig Corporation (62) 47-2 www.whiteedc.com
White Electronic Desig AC CHARACTERISTICS READ CYCLE Symbol 55 7 85 1 Parameter JEDEC Alt. Min Max Min Max Min Max Min Max Units Read Cycle Time tavav trc 55 7 85 1 Address Access Time tavqv taa 55 7 85 1 Chip Enable Access Time telqv tacs 55 7 85 1 Chip Enable to Output in Low Z (1) telqx tclz 5 5 5 5 Chip Disable to Output in High Z (1) tehqz tchz 5 4 Output Hold from Address Change tavqx toh Output Enable to Output Valid tglqv toe 4 4 45 5 Output Enable to Output in Low Z (1) tglqx tolz Output Disable to Output in High Z (1) tghqz tohz 5 4 Note 1: Parameter guaranteed, but not tested. Note 1: Parameter guaranteed, but not tested. AC CHARACTERISTICS WRITE CYCLE Write Cycle Symbol 2 25 5 Parameter JEDEC Alt. Min Max Min Max Min Max Units Write Cycle Time tavav twc 2 25 5 Chip Enable to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Data Hold Time telwh teleh tavwl tavel tavwh taveh twlwh twleh twhax tehax twhdx tehdx tcw tcw tas tas taw taw twp twp twr TWR tdh tdh Write to Output in High Z (1) twlqz twhz 1 12 Data to Write Time tdvwh tdveh tdw tdw 12 12 2 2 Output Active from End of Write (1) twhqx twlz 2 2 2 2 2 2 25 25 White Electronic Desig Corp. reserves the right to change products or specifi catio without notice. July 22 5 White Electronic Desig Corporation (62) 47-2 www.whiteedc.com
White Electronic Desig AC CHARACTERISTICS WRITE CYCLE Symbol 55 7 85 1 Parameter JEDEC Alt. Min Max Min Max Min Max Min Max Units Write Cycle Time tavav twc 55 7 85 1 Chip Enable to End of Write telwh teleh tcw tcw 5 5 7 7 8 8 Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Data Hold Time Note 1: Parameter guaranteed, but not tested. tavwl tavel tavwh taveh twlwh twleh twhax tehax twhdx tehdx tas tas taw taw twp twp twr twr tdh tdh 5 5 5 5 Write to Output in High Z (1) twlqz twhz 5 4 Data to Write Time tdvwh tdveh tdw tdw 5 5 4 4 Output Active from End of Write (1) twhqx twlz 5 5 5 7 7 7 7 8 8 8 8 FIG. 7 WRITE CYCLE 1 - CON TROLLED A tavav telwh tavwh twhax twlwh tavwl tdvwh twhdx D DATA VALID Q twlqz HIGH Z twhqx 8F8512C Write Cyc1 White Electronic Desig Corp. reserves the right to change products or specifi catio without notice. July 22 6 White Electronic Desig Corporation (62) 47-2 www.whiteedc.com
White Electronic Desig FIG. 8 WRITE CYCLE 2 - CON TROLLED tavav A tavel teleh D taveh twleh tehax tdveh tehdx DATA VALID Q 8F8512C Write Cyc2 HIGH Z White Electronic Desig Corp. reserves the right to change products or specifi catio without notice. July 22 7 White Electronic Desig Corporation (62) 47-2 www.whiteedc.com
White Electronic Desig DATA RETENTION CHARACTERISTICS LP 7-1 Only Characteristic Sym Test Conditio Min Typ Max Unit 7 C 85 C Data Retention Voltage =.2V 2 V Data Retention Quiescent Current ICCDR -.2V 2V 1 125 185 μa VIN -.2V V 2 2 25 μa Chip Disable to Data Retention Time (1) tcdr or VIN.2V Operation Recovery Time (1) tr tavav* *Read Cycle Time Note: Parameter guaranteed, but not tested. FIG. 9 DATA RETENTION CON TROLLED DATA RETENTION MODE 4.5V 4.5V tcdr tr -.2V 8F8512C Data Retent. ORDERING INFORMATION Standard Power Speed () Package No. 2M6C 2 18 25M6C 25 18 5M6C 5 18 7BSC 7 6 85BSC 85 6 1BSC 1 6 55B6C 55 91 7B6C 7 91 85B6C 85 91 1B6C 1 91 Low Power with Data Retention Speed () Package Leads EDI8F8512LP7BSC 7 6 EDI8F8512LP85BSC 85 6 EDI8F8512LP1BSC 1 6 EDI8F8512LP7B6C 7 91 EDI8F8512LP85B6C 85 91 EDI8F8512LP1B6C 1 91 Note: To order an Industrial grade product substitute the letter C in the Suffix with the letter I, e.g., 7B6C becomes 7B6I. White Electronic Desig Corp. reserves the right to change products or specifi catio without notice. July 22 8 White Electronic Desig Corporation (62) 47-2 www.whiteedc.com
White Electronic Desig PACKAGE DESCRIPTIONS PACKAGE NO. 6: 6 PIN SINGLE-IN-LINE PACKAGE 4.4 Max.. Max.125 Min.575.5.2.16 5 x.1 =.5.1 8F8512C Pkg1 PACKAGE NO. 91: 2 PIN DUAL-IN-LINE PACKAGE 1.6 MAX. NOTE 2 U5 R1 U1 U2 R2.64 MAX..85..1 TYP. x.1 1.5 REF..248 MAX..175.125.25..62.59 8F8512C Pkg 2 PACKAGE NO. 18: 2 PIN DUAL-IN-LINE PACKAGE.1.5 1 8F8512C Pkg 1.7 MAX. x.1 1.5 REF..64 MAX..55 MAX. NOT RECOMMENDED FOR NEW DESIGNS.175.125 ALL DIMENSIONS ARE IN INCHES.62.59 White Electronic Desig Corp. reserves the right to change products or specifi catio without notice. July 22 9 White Electronic Desig Corporation (62) 47-2 www.whiteedc.com