Universal Verification Methodology (UVM) Module 5

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Transcription:

Universal Verification Methodology (UVM) Module 5 Venky Kottapalli Prof. Michael Quinn Spring 2017

Agenda Assertions CPU Monitor System Bus Monitor (UVC) Scoreboard: Cache Reference Model Virtual Sequencer Test Coverage

Assertions An Assertion is a check embedded in the design Monitor and report: Expected behavior Forbidden behavior Example: cpu_rd and cpu_wr should not be high at the same time Used in: Static verification: formal verification techniques Dynamic verification: simulation Assertions are not new: always @(posedge clk) if (cpu_rd && cpu_wr) $error( read and write cannot be high );

Need for Assertions Improved observability: Close to source of bug -> lesser debug Automatically and constantly checks behavior Improved efficiency Verif engineers can focus on system-level issues Concisely documents design intent Improved reuse Perfect for IP methodology Tool independent

Types of Assertions Immediate assertions Placed within procedural code Example: within an always block Suitable only for simulation (dynamic verification) Concurrent assertions Placed outside all procedural code Must include a clocking event Suitable for both formal and simulation

Assertions Evaluation uses sampled values i.e. pre-clock values Sequences: Temporal property that spans multiple clock cycles Delay operator (##) @(posedge clk) A ##1 B ##3 C Replication operator [*n] @(posedge clk) B ##1 A[*2] Refer to A Practical Guide for SystemVerilog Assertions ebook available for download from the library

Overlapping Implication Operator

Non-overlapping Implication Operator

Assertions Where to place them in our TB? CPU-lv1 interface System bus interface Examples? Uses: simple protocol checks

Demo Exercise Write sample assertions for Cpu level1 interface System bus interface DIY exercise: Additional assertions for both interfaces

Arbiter Recap: Intermediate TestBench Transaction Sequencer for CPU0 CPU 0 Driver Sequence Test cases/sequences Cache Lv1 Cache Lv1 Cache Lv1 Cache Lv1 Cache Lv2 Main Memory

Recap: Our Objective CPU Agent Scoreboard Checkers tlm Sequencer tlm Monitor tlm Driver tlm Coverage vi vi Cache LV1 (core x)

Arbiter Sequence Virtual Sequencer Test cases/sequences Sequencer for CPU0 Sequencer for CPU1 Sequencer for CPU2 Sequencer for CPU3 Transaction CPU 0 Driver CPU 1 Driver CPU 2 Driver CPU 3 Driver CPU0 monitor Checker Cache Reference Model CPU1 monitor Cache Lv1 Cache Lv1 Cache Lv1 Cache Lv1 CPU2 monitor CPU3 monitor Coverage Collector System Bus Monitor Cache Lv2 Main Memory

CPU Monitor Observe the interface between the CPU and level-1 cache Capture the observations into the CPU monitor packet Transfer the packet to the scoreboard once complete What fields must we populate? Data Address Request Type etc.

CPU Monitor Packet

Demo Exercise Define the cpu monitor Capture the transaction on the cpu-level1 interface into a cpu monitor packet Include the monitor into the cpu agent DIY exercise: Complete the code for the monitor All fields in the cpu monitor packet must be populated

System Bus Monitor Observe the activity on the system bus Which core raised the processor request? Which core received grant? What other fields must be populated? Proc core Snoop core Address Data Transaction type? bus_rd, bus_rdx, invalidate?

System Bus Monitor Packet

Demo Exercise Define the system bus monitor Capture the transaction on the system bus interface into a packet Define a environment (uvm_env) that includes: Agent (CPU0) System bus monitor DIY exercise: Complete the code for the monitor All fields in the sbus packet must be populated

Scoreboard Functions of the scoreboard Transfer function (reference model): transaction level model Expected data storage: expected activity on system bus Elaborate checkers (system level checks) CPU0 monitor Scoreboard CPU0 monitor CPU0 monitor Reference model Expected data storage Checking System bus Monitor CPU0 monitor

Analysis Interface

Implementation

Analysis Interface Example

Analysis Interface Connection

Multiple Analysis Imp Connections

Demo Exercise Connect the analysis TLM interface between the monitors and the scoreboard Walk-through the reference model code What to do when we receive CPU monitor packet? What to do when we receive a Sbus packet? When/what do we check? Sbus packet: expected vs received Data When to update cache model?

Arbiter Recap: Intermediate TestBench Transaction Sequencer for CPU0 CPU 0 Driver Sequence Test cases/sequences CPU 0 Monitor Cache Lv1 Cache Lv1 Cache Lv1 Cache Lv1 Scoreboard System Bus Monitor Cache Lv2 Main Memory

Virtual Sequences

Why Virtual Sequences?

Virtual Sequencer

Connecting the handles

p_sequencer variable Allows a sequence to access properties of its sequencer Virtual sequencer has handles for each of the CPU sequencers Control the transaction on each of the CPU cores Temporal control: read on cpu0 Delay of 10 clock cycles read on cpu2

Virtual Sequence Example

Demo Exercise Create 4 CPU agents corresponding to each of the level1 caches Include these agents within the env Provide Virtual interfaces for all CPU agents Connect all CPU monitors to the scoreboard Create a virtual sequencer with handles for each of the cpu sequencers Assign handles within env Create a sequence for read hit Dcache Modify the test to set default sequence for the virtual sequencer

Coverage Example

Project Instructions How to add a new test, sequence? To-do Driver Monitor Sequences Assertions Checkers Coverage Minimal info required for bug report

References Verification Excellence by Ramdas Cadence SV Tutorial (most slides from here) Cadence UVM Tutorials Udemy Course on SoC Verification Testbench.in Verification Academy Courses Duolos Video Tutorials Accellera UVM Standard Verification Academy UVM Cookbook SystemVerilog for verification by Chris Spear

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Thank You Introduction to Hardware Design Verification CSCE/ECEN 489/689

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