Contents 1 Introduction 2 Functional Verification: Challenges and Solutions 3 SystemVerilog Paradigm 4 UVM (Universal Verification Methodology)

Transcription

1 1 Introduction Functional Design Verification: Current State of Affair Where Are the Bugs? Functional Verification: Challenges and Solutions Verification Challenges and Solutions Reduce Time to Develop Reduce Time to Simulate Reduce Time to Debug Reduce Time to Cover: Check How Good Is Your Testbench A Comprehensive Verification Plan SystemVerilog Paradigm SystemVerilog Language Umbrella SystemVerilog Language Evolution UVM (Universal Verification Methodology) What Is UVM? Polymorphism UVM Hierarchy UVM Testbench UVM Test UVM Environment UVM Agent UVM Sequence Item UVM Sequence UVM Sequencer UVM Driver UVM Monitor UVM Scoreboard xv

2 xvi 4.4 UVM Class Library UVM Transaction-Level Communication Protocol: Basics Basic Transaction-Level Communication Hierarchical Connections Analysis Ports and Exports UVM Phases Build Phases Run-Time Phases Cleanup Phases UVM Example: One Modeling a Sequence Item Building UVM Driver Basic Sequencer and Driver Interaction Building UVM Sequencer Building UVM Monitor UVM Agent: Connecting Driver, Sequencer, and Monitor Building the Environment UVM Top-Level Module (Testbench) Example UVM Example: Two DUT: lpi.sv lpi_if.sv lpi_seq_item.sv lpi_sequencer.sv lpi_driver.sv lpi_monitor.sv lpi_agent.sv lpi_basic_sequence.sv lpi_basic_test.sv lpi_env.sv lpi_top_v_sequencer.sv lpi top environment.sv lpi_testbench.sv UVM Is Reusable Constrained Random Verification (CRV) Productivity Gain with CRV CRV Methodology Basics of CRV Random Variables: Basics Random Number System Functions and Methods Random Weighted Case: Randcase SystemVerilog Assertions (SVA) Evolution of SystemVerilog Assertions SystemVerilog Assertion Advantages

3 xvii Assertions Shorten Time to Develop Assertions Improve Observability Assertions Shorten Time to Cover One-Time Effort: Many Benefits Creating an Assertion Test Plan: PCI Read Example PCI: Read Protocol Assertion Test Plan (Verification Team) PCI: Read Protocol Assertions Test Plan (Design Team) SVA Assertion Methodology Components What Type of Assertions Should I Add? Protocol for Adding Assertions How Do I know I Have Enough Assertions? Use Assertions for Specification and Review Immediate Assertions Concurrent Assertions Overlapping and Nonoverlapping Operators Clocking Basics Sampling Edge (Clock Edge) Concurrent Assertions: Binding Properties Binding Properties (Scope Visibility) Operators ##m: Clock Delay ##[m:n]: Clock Delay Range [*m]: Consecutive Repetition Operator [*m:n]: Consecutive Repetition Range [=m]: Repetition Non-consecutive [=m:n]: Repetition Non-consecutive Range [->m] Non-consecutive GoTo Repetition Operator sig1 throughout seq seq1 within seq seq1 and seq seq1 or seq seq1 intersect seq Local Variables SystemVerilog Assertions: Applications SVA Application: Infinite Delay Range Operator SVA Application: Consecutive Delay Range Operator SVA Application: Consecutive Delay Range Operator SVA Application: Antecedent as Property Check. Consequent as Hard Failure SVA Application: State Transition Check of a State Machine

4 xviii SVA Application: Multi-threaded Operation SVA Application: A Request Grant Bus Protocol SVA Application: Machine Check Exception SVA Application: req followed by ack SystemVerilog Functional Coverage (SFC) Difference Between Code Coverage and Functional Coverage SystemVerilog Components for Complete Coverage Assertion (ABV) and Functional Coverage (SFC)-Based Methodology Follow the Bugs! SystemVerilog Covergroup Basics SystemVerilog Coverpoint Basics SystemVerilog Bins : Basics Covergroup in a Class Cross Coverage Bins for Transition Coverage Performance Implications of Coverage Methodology Know What You Should Cover Know When You Should Cover When to Cover (Performance Implication) SystemVerilog Functional Coverage: Applications PCI Cycles Frame Length Coverage Clock Domain Crossing (CDC) Verification Design Complexity and CDC Metastability Synchronizer Two-Flop Synchronizer (Identical Transmit and Receive Clock Frequencies) Three-Flop Synchronizer (High-Speed Designs) Synchronizing Fast-Clock (Transmit) into Slow-Clock (Receive) Domains Multi-bit Synchronization Design of an Asynchronous FIFO Using Gray Code Counters CDC Checks Using SystemVerilog Assertions CDC Verification Methodology Automated CDC Verification Step 1: Structural Verification Step 2: Protocol Verification Step 3: Debug CDC Verification at Gate Level EDA Vendors and CDC Tools Support Mentor

5 xix 9 Low-Power Verification Power Requirements: Current Industry Trend Dynamic Low-Power Verification Challenges UPF (Unified Power Format) UPF Evolution UPF Methodology Low-Power Design Terminology/Definitions UPF: Detailed SoC Example Design/Logic Hierarchy Navigation Power Domain Creation Supply Power to the Power Domains: Supply Network Power Switch Creation Supply Port States Power State Table State Retention Strategies Isolation Strategies Level Shifting Strategies Power Estimation at Architecture Level UPF Features Subset (IEEE ) Static Verification (Formal-Based Technologies) What Is Static Verification? Static Verification Umbrella Static Formal Verification (Aka Model Checking Aka Static Functional Verification) Critical Logic Blocks for Static Formal SystemVerilog Assertions and Assumptions for Static Formal and Simulation SystemVerilog Assume and Static Formal Verification Static Formal vs. Simulation Static Formal + Simulation Hybrid Verification Methodology Logic Equivalence Check (LEC) LEC Technology RTL to RTL Verification RTL to Gate Verification Gate to Gate Verification ESL (C/ C++/ SystemC model) to RTL (Sequential Equivalence Checking SEC) Layout vs. Schematic (LVS) Physical Verification RTL Lint Structural Checks Low Power Structural Checks X-State Verification Connectivity Verification

6 xx 11 ESL (Electronic System Level) Verification Methodology ESL (Electronic System Level) How Does ESL Help with Verification? ESL Virtual Platform Use Cases OSCI TLM 2.0 Standard for ESL Loosely Timed (LT) TLM 2.0 Transaction-Level Modeling Approximately Timed (AT) TLM 2.0 Transaction-Level Modeling Virtual Platform Example Advantages of a Virtual Platform Open Virtual Platform (OVP) Initiative Rationale for Software Virtual Platforms (OVP n.d.) ESL/Virtual Platform for Design Verification Overview Virtual Platform and RTL Co-simulation and Verification Virtual Platform as a Reference Model in UVM Scoreboard ESL to RTL Reuse Methodology Design and Verification Reuse: Algorithm ESL: TLM Design and Verification Reuse: ESL/TLM 2.0 RTL Design and Verification Reuse: Algorithm ESL-TLM 2.0 RTL Hardware/Software Co-verification Overview Hardware/Software Co-verification Using Virtual Platform with Hardware Emulation Hardware Emulation and Prototyping Emulation System Compile Time Difference Between Emulator and FPGA-Based Prototype Myths About Emulation-Based Acceleration (Rizzati) Speed Bridge Virtual Platform Hardware Emulation Interface and Methodology Different Types of Hardware/Software Co-verification Configurations

7 xxi 12.5 Hardware/Software Co-verification Using Virtual Platform with Hardware Accelerator Cadence Palladium Mentor Veloce Synopsys Zebu Analog/Mixed Signal (AMS) Verification Overview Major AMS Verification Challenges and Solutions Disparate Methodologies Analog Model Abstractions and Simulation Performance Low-Power Management Real Number Modeling (RNM) of Analog Blocks wreal nettype AMS Assertion (SVA)-Based Methodology AMS Simulator: What Features Should It Support? Integrated Simulation Solution for Fastest Simulation Throughput Support for Wide Spectrum of Design Languages Support for Different Levels of Model Abstraction AMS Low-Power Verification Support Support for SystemVerilog-Based UVM Methodology Including Coverage-Driven and Assertion-Based Methodologies SoC Interconnect Verification Overview SoC Interconnect Verification: Challenges and Solutions Performance Analysis Interconnect Functional Correctness and Verification Completeness SoC Interconnect Stimulus Generation Stress Verification: Random Concurrent Tests SoC Interconnect Response Checker SoC Interconnect Coverage Measurement Cadence Interconnect Solution (Cadence-VIP n.d.) Cadence Interconnect Validator (Basic) Cadence Interconnect Validator (Cache Coherent) Cadence Interconnect Workbench Synopsys Cache Coherent Subsystem Verification Solution for Arteris Ncore Interconnect (NoC)

8 xxii 15 The Complete Product Design Life Cycle Overview Product Design and Development Flow Design Specification PCB (Printed Circuit Board) Design Schematic Design Pre-layout Signal Integrity (SI), Power Integrity (PI), and Thermal Integrity (TI) Simulation Layout, Fabrication, and Assembly Post-layout Signal Integrity (SI), Power Integrity (PI), and Thermal Integrity (TI) Simulation Hardware Bring-Up and Debug ASIC/FPGA Design HDL Design Pre-synthesis Simulation Post-synthesis/Place and Route Simulation, Timing Closure Integration Verification Test Plan Specification Testbench and Test Program Development Functional Test Gate-Level Verification Functional/Gate Regression Emulation Voice Over IP (VoIP) Network SoC Verification Voice Over IP (VoIP) Network SoC VoIP Network SoC Verification Plan Identify Subsystems Within VoIP Network SoC Determine Subsystem Stimulus and Response Methodology SoC Interconnect Verification Low-Power Verification Static Formal or Static + Simulation Hybrid Methodology Assertion Methodology Functional Coverage Software/Hardware Co-verification Simulation Regressions: Hardware Acceleration or Emulation or FPGA Prototyping Virtual Platform Cache Memory Subsystem Verification: UVM Agent Based Cache Subsystem Identify Subsystems Within the Cache Subsystem Determine Subsystem Stimulus and Response Methodology Cache Subsystem Interconnect Verification

9 xxiii 17.5 Low-Power Verification Static Formal or Static + Simulation Hybrid Assertions Methodology (SVA) Coverage Methodology (Functional: SFC, Code, and SVA cover ) Software/Hardware Co-verification Simulation Regressions: Hardware Acceleration or Emulation or FPGA Prototyping ESL: Virtual Platform for Software and Test Development Cache Memory Subsystem Verification: ISS Based Bibliography Index

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