ECE 331 Digital System Design

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ECE 331 Digital System Design Tristate Buffers, Read-Only Memories and Programmable Logic Devices (Lecture #17) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6 th Edition, by Roth and Kinney, and were used with permission from Cengage Learning.

Tristate Buffers Spring 2011 ECE 331 - Digital System Design 2

Tristate Buffer A tristate buffer can output 3 different values: Logic 1 (high) Logic 0 (low) High-Impedance control input output Spring 2011 ECE 331 - Digital System Design 3

Tristate Buffers Enable Spring 2011 ECE 331 - Digital System Design 4

Building a Mux with Tristate Buffers Outputs can be shorted together Only one buffer is enabled at a time Spring 2011 ECE 331 - Digital System Design 5

IC Bi-directional I/O Pin Spring 2011 ECE 331 - Digital System Design 6

Read-Only Memories Spring 2011 ECE 331 - Digital System Design 7

ROM A read-only memory (ROM) consists of an array of semiconductor devices that are interconnected to store a set of binary data. Once binary data is stored in the ROM, it can be read out whenever desired, but the data that is stored cannot be changed under normal operating conditions. Data is written to the ROM once, and read from the ROM many times. Spring 2011 ECE 331 - Digital System Design 8

ROM address data Spring 2011 ECE 331 - Digital System Design 9

ROM Basic Structure address data 10

Building Logic Functions using ROM F 0 = Σm(0, 1, 4, 6) F 1 = Σm(2, 3, 4, 6, 7) What functions are realized by the ROM for F 2 and F 3? Spring 2011 ECE 331 - Digital System Design 11

Building Logic Functions using ROM Spring 2011 ECE 331 - Digital System Design 12

Building Logic Functions using ROM A 5 = A 4 A 6 = A 5 ' Spring 2011 ECE 331 - Digital System Design 13

Programmable Logic Devices Spring 2011 ECE 331 - Digital System Design 14

Programmable Logic Device A programmable logic device (or PLD) is a general name for a digital integrated circuit capable of being programmed to provide a variety of different logic functions. When a digital system is designed using a PLD, changes in the design can easily be made by changing the programming of the PLD without having to change the wiring in the system. Programmable Logic Devices (PLDs) include: Programmable Logic Arrays (PLAs) Programmable Array Logic (PALs) Complex Programmable Logic Devices (CPLDs) Field Programmable Gate Arrays (FPGAs) Spring 2011 ECE 331 - Digital System Design 15

Programmable Logic Array A Programmable Logic Array (PLA) performs the same basic function as the ROM. A PLA with n inputs and m outputs can realize m functions of n variables A PLA consists of An AND array to realize product terms An OR array to realize the output functions Thus, a PLA implements SOP expressions. Spring 2011 ECE 331 - Digital System Design 16

PLA Basic Structure 17

Building Logic Functions with PLA F 0 = Σm(0, 1, 4, 6) F 1 = Σm(2, 3, 4, 6, 7) What functions are realized by the PLA for F 2 and F 3? Spring 2011 ECE 331 - Digital System Design 18

Building Logic Functions using PLA Wired-OR Wired-AND same functions as previous slide Spring 2011 ECE 331 - Digital System Design 19

Building Logic Functions using PLA OR AND 20

Programmable Array Logic The Programmable Array Logic (PAL) is a special case of the PLA AND array is programmable OR array is fixed A PAL is less expensive than the more general PLA. A PAL is easier to program. Spring 2011 ECE 331 - Digital System Design 21

Building Logic Functions using PAL fixed programmable Spring 2011 ECE 331 - Digital System Design 22

Building Logic Functions using PAL Spring 2011 ECE 331 - Digital System Design 23

Complex Programmable Logic Device A Complex Programmable Logic Device integrates many PLAs (or PALs) onto a single chip. In addition to the individual PLAs (or PALs) being programmable, the interconnection between these components is also programmable. A small digital system can be realized using A single CPLD Necessary memory elements (i.e. flip-flops) Spring 2011 ECE 331 - Digital System Design 24

CPLD Architecture of the Xilinx XCR3064XL CPLD (Figure based on figures and text owned by Xilinx, Inc., Courtesy of Xilinx, Inc. Xilinx, Inc. 1999-2003. All rights reserved.) Spring 2011 ECE 331 - Digital System Design 25

CPLD CPLD Function Block and Macrocell (A Simplified Version of XCR3064XL) Spring 2011 ECE 331 - Digital System Design 26

Field Programmable Gate Array A Field Programmable Gate Array consists of An array of identical logic cells An interconnection network between logic cells The logic cells, aka Configurable Logic Blocks (CLBs), are programmable. The interconnection between CLBs is also programmable. The CLBs are surrounded by a ring of I/O blocks which connect the CLBs to the I/O pins. Spring 2011 ECE 331 - Digital System Design 27

Layout of a Typical FPGA Spring 2011 ECE 331 - Digital System Design 28

Simplified Configurable Logic Block 29

Implementation of a Lookup Table A 4-input Lookup Table (LUT) is, essentially, a reprogrammable ROM with 16 1-bit words. Spring 2011 ECE 331 - Digital System Design 30

Questions? Spring 2011 ECE 331 - Digital System Design 31

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