I 4 I 3 I 2 I 1 I 0 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 T-125. ROM Truth Table (Partial) 1997 by Prentice-Hall, Inc.

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1 997 by Prentice-Hall, Inc. ano & Kime Upper Saddle River, New Jersey 7458 T-5 Inputs Outputs I 4 I 3 I I I A 7 A 6 A 5 A 4 A 3 A A A RO Truth Table (Partial)

2 997 by Prentice-Hall, Inc. ano & Kime Upper Saddle River, New Jersey 7458 T-6 Inputs Outputs A A A B 5 B 4 B 3 B B B Decimal Truth Table for Circuit of Example 6-

3 T-7 Programming Table for the PLA in Figure 6- TABLE 6-4 Programming Table for the PLA in Figure 6- Inputs Outputs Product term A B C (T) F (C) F AB AC BC ABC by Prentice-Hall, Inc. ano & Kime Upper Saddle River, New Jersey 7458

4 T-8 PAL Programming Table TABLE 6-5 PAL Programming Table Product term AND Inputs A B C D W Outputs 3 W ABC A BCD A BCD Y AB CD B D Z W ACD A B CD 997 by Prentice-Hall, Inc. ano & Kime Upper Saddle River, New Jersey 7458

5 T-9 Block Diagram of emory n data input lines k address lines Read Write emory unit k words n bits per word n data output lines 997 by Prentice-Hall, Inc. ANO & KIE Upper Saddle River, New Jersey 7458

6 T-3 Contents of a 4 x 6 emory emory address Binary Decimal 3 emory contents 997 by Prentice-Hall, Inc. ANO & KIE Upper Saddle River, New Jersey 7458

7 T-3 emory Cycle Timing Waveforms ns Clock T T T3 T4 T Address Address valid emory enable Read/ Write Data input Data valid 75 ns ns (a) Write cycle Clock T T T3 T4 T Address Address valid emory enable Read/ Write Data output Data valid 65 ns (b) Read cycle 997 by Prentice-Hall, Inc. ANO & KIE Upper Saddle River, New Jersey 7458

8 T-3 Static RA Cel Select B S Q C B R Q C 997 by Prentice-Hall, Inc. ANO & KIE Upper Saddle River, New Jersey 7458

9 T-33 RA Bit Slice odel Word Select B S Q C B R Q C Word Word n Select S R Q Q Word Word n Read/Write logic Data in S R Q Q Data in Read/ Write Data out Bit (b) Symbol Read/ Write Write logic Bit Read logic Data out (a) Logic diagram 997 by Prentice-Hall, Inc. ANO & KIE Upper Saddle River, New Jersey 7458

10 T-34 6-Word by -Bit RA Chip A 3 A 3 4 to 6 Decoder 3 Word A A A A A Data input 6 x RA Data output A Read/ Write 4 5 emory enable (a) Symbol Read/Write logic Data input Data in Read/ Write Data out Bit Data output Read/ Write Chip (b) Block diagram 997 by Prentice-Hall, Inc. ANO & KIE Upper Saddle River, New Jersey 7458

11 T-35 Three-state Buffer EN IN OUT IN OUT Hi-Z EN (a) Logic symbol (b) Truth table 997 by Prentice-Hall, Inc. ano & Kime Upper Saddle River, New Jersey 7458

12 T-36 Three-state Buffers Forming a ultiplexed Line OL EN EN IN IN OL Hi-Z (S) IN EN OL (S) (S) IN (S) EN (a) Logic Diagram (b) Truth table 997 by Prentice-Hall, Inc. ano & Kime Upper Saddle River, New Jersey 7458

13 T-37 Diagram of a 6 x RA Using a 4 x 4 RA Cell Array Row decoder A 3 to 4 Decoder A 3 Row Read/Write logic Read/Write logic Read/Write logic Read/Write logic Data in Data out Data in Data out Data in Data out Data in Data out Read/ Write Bit Read/ Write Bit Read/ Write Bit Read/ Write Bit Data input Read/ Write Column 3 Data output Column decoder to 4 Decoder with enable A A Enable Chip 997 by Prentice-Hall, Inc. ANO & KIE Upper Saddle River, New Jersey 7458

14 T-38 Block Diagram of an 8 x RA Using a 4 x 4 RA Cell Array Row decoder A A to 4 Decoder 3 Row Read/Write logic Read/Write logic Read/Write logic Read/Write logic Data in Data out Data in Data out Data in Data out Data in Data out Read/ Write Bit Read/ Write Bit Read/ Write Bit Read/ Write Bit Data input Data input Read/ Write Column decoder Column to Decoder with enable Enable Data output Data output A Chip 997 by Prentice-Hall, Inc. ANO & KIE Upper Saddle River, New Jersey 7458

15 T-39 Symbol for a 64K x 8 RA Chip 64K x 8 RA Input data 8 DATA 8 Output data Address 6 ADRS Chip CS Read/ Write R/ W 997 by Prentice-Hall, Inc. ANO & KIE Upper Saddle River, New Jersey 7458

16 T-4 Block Diagram of a 56K x 8 RA Address Lines Lines Input data 8 emory enable EN 3 to 4 decoder 64K x 8 RA DATA ADRS CS Read/ Write R/W -65,535 64K x 8 RA DATA ADRS CS R/W 65,536-3,7 64K x 8 RA DATA ADRS CS R/W 3,7-96,67 64K x 8 RA DATA ADRS CS 8 R/W 96,68-6,43 Output data 997 by Prentice-Hall, Inc. ANO & KIE Upper Saddle River, New Jersey 7458

17 T-4 Block Diagram of a 64K x 6 RA 6 input data lines 8 8 Address 6 64K x 8 RA 64K x 8 RA Chip Read/ Write 8 6 DATA ADRS CS R/W DATA 6 ADRS CS R/W output data lines 997 by Prentice-Hall, Inc. ano & Kime Upper Saddle River, New Jersey 7458

18 T-4 Internal Logic of a 3 x 8 RO I I I I 3 I 4 5 to 3 decoder A 7 A 6 A 5 A 4 A 3 A A A 997 by Prentice-Hall, Inc. ano & Kime Upper Saddle River, New Jersey 7458

19 T-43 Programming the RO According to Table 6- I I I I 3 I 4 5 to 3 decoder Fuse intact Fuse blown A 7 A 6 A 5 A 4 A 3 A A A 997 by Prentice-Hall, Inc. ano & Kime Upper Saddle River, New Jersey 7458

20 T-44 RO Implementation of Example 6- A A A 8 x 4 RO B B B B 3 B 4 A A A B 5 B 4 B 3 B B 5 (a) Block diagram (b) RO truth table 997 by Prentice-Hall, Inc. ANO & KIE Upper Saddle River, New Jersey 7458

21 T-45 Basic Configuration of Three PLDs Inputs Fixed AND array (decoder) Programmable Connections Programmable OR array Outputs (a) Programmable read-only memory (PRO) Inputs Programmable Connections Programmable AND array Fixed OR array Outputs (b) Programmable array logic (PAL) device Inputs Programmable Connections Programmable AND array Programmable Connections Programmable OR array Outputs (c) Programmable logic array (PLA) device 997 by Prentice-Hall, Inc. ano & Kime Upper Saddle River, New Jersey 7458

22 T-46 PLA with Three Inputs, Four Product Terms, and Two Outputs A B C AB 3 AC BC Fuse intact Fuse blown 4 ABC C C B B A A F F 997 by Prentice-Hall, Inc. ANO & KIE Upper Saddle River, New Jersey 7458

23 T-47 Solution to Example 6- BC A B BC A B A A C F = AB + AC + BC F = AB + AC + BC C F = AB + AC + ABC F = AC + AB + ABC PLA programming table Outputs Product term Inputs A B C (C) F (T) F AB AC BC 3 ABC by Prentice-Hall, Inc. ANO & KIE Upper Saddle River, New Jersey 7458

24 T-48 PAL device with Four Inputs, Four Outputs, and a Three-wide AND-OR Structure Product term AND gates inputs F 3 I 4 5 F I F 3 I 3 9 F 4 I by Prentice-Hall, Inc. ANO & KIE Upper Saddle River, New Jersey 7458

25 T-49 Connection ap for PAL Device as Specified in Table 6-5 Product term AND gates inputs A A B B C C D D W W W 3 A B All fuses intact (always = ) 7 8 Y C 9 Z D Fuse intact Fuse blown A A B B C C D D W W 997 by Prentice-Hall, Inc. ANO & KIE Upper Saddle River, New Jersey 7458

26 T-5 Altera A 7 Structure (Reprinted with Permission of Altera Corporation, Altera Corp., 99) I/O control Logic array Logic array Logic array Logic array Programmable interconnect array I/O control Logic array Logic array Logic array Logic array Logic array Logic array Logic array Logic array I/O control Logic array Logic array Logic array Logic array I/O control 997 by Prentice-Hall, Inc. ANO & KIE Upper Saddle River, New Jersey 7458

27 T-5 Actel ACT 3 Structure (Reprinted Courtesy of Actel Corporation, Actel Corp., 993) Vertical routing track Horizontal routing channel and tracks - Logic module - l/ module 997 by Prentice-Hall, Inc. ano & Kime Upper Saddle River, New Jersey 7458

28 T-5 Actel Logic odules (Reprinted Courtesy of Actel Corporation, Actel Corp., 993) D 4 to U D 4 to U D D D 3 S S OUT D D D 3 S S D C CLR OUT A B A B A B A B CLK CLR (a) C (combinational) module (b) S (sequential) module 997 by Prentice-Hall, Inc. ano & Kime Upper Saddle River, New Jersey 7458

29 T-53 ilinx C4 FPGA Structure (Adapted with Permission of ilinx, Inc.) Single length Long lines - Input/Output Block (IOB) - Configurable logic (CLB) - Switch matrix 997 by Prentice-Hall, Inc. ANO & KIE Upper Saddle River, New Jersey 7458

30 T-54 SRA Bit Use in ilinx FPGAs G S D (a) Pass transistor control U S A B C F(A, B, C) (b) ultiplexer control (c) Look up table implementation 997 by Prentice-Hall, Inc. ano & Kime Upper Saddle River, New Jersey 7458

31 T-55 Example of ilinx Switch atrix (Adapted with Permission of ilinx, Inc.) (a) Switch atrix Transistors (b) Examples of Connections 997 by Prentice-Hall, Inc. ano & Kime Upper Saddle River, New Jersey 7458

32 T-56 Simplified Diagram of a ilinx Configurable Logic Block (Adapted with permission of ilinx, Inc.) G G G3 Look up Table for G' G' H DIN S/R EC U G4 6 bits of SRA Look up Table for H' H' DIN F' G' H' S S/R Control U D PRE EC CLR YQ F F F3 Look up Table for F' 8 bits of SRA F' U G' H' S U S Y F4 6 bits of SRA DIN F' G' H' S S/R Control U D PRE EC CLR Q K (CLOCK) U F' H' S S - S 997 by Prentice-Hall, Inc. ANO & KIE Upper Saddle River, New Jersey 7458

33 T-56 Sketch of ilinx IOB Structure (Adapted with Permission of ilinx, Inc.) Three-state TS Output Data O FPGA Interior PRE D CLR OUTPUT I/O PIN Input Data PRE D Input Data CLR INPUT 997 by Prentice-Hall, Inc. ano & Kime Upper Saddle River, New Jersey 7458

Fig. 6-1 Conventional and Array Logic Symbols for OR Gate

Fig. 6-1 Conventional and Array Logic Symbols for OR Gate 6- (a) Conventional symbol (b) Array logic symbol Fig. 6- Conventional and Array Logic Symbols for OR Gate 2 Prentice Hall, Inc. 6-2 k address lines Read n data input lines emory unit 2 k words n bits