Virtual memory Hung-Wei Tseng
Why virtual memory How VM works VM and cache Outline 2
Virtual memory 3
Scenario I An application is design on machine A with memory size X. Can we safely execute the same application on another machine B with memory size Y? physical memory of machine A Application physical memory of machine B? 4
Scenario II Both application A and application B would like to use the same machine Each application should not touch data of the other. This is called protection in OS Application A Physical memory of the machine Application B 5
Why Virtual Memory? Every process runs on virtual memory space Process: a running program in the operating system virtual memory memory. Physical memory caches memory pages from Single program can exceed the size of physical Multiple processes can share a single main memory. virtual address space of program A virtual address space of program B 6
Memory Hierarchy Fastest, Most Expensive CPU $ Main Memory Secondary Storage Main memory is a cache for Virtual Memory A: Fully Associative B: page size! S: (Since it s FA) Replacement policies? LRU, random... Operating system manages the mapping between physical and virtual VM addresses Biggest 7
How VM works 8
Virtual memory An abstraction of memory space available for programs/software/programmer Programs execute using virtual memory address The operating system and hardware work together to handle the mapping between virtual memory addresses and real/physical memory addresses 9
Address translation Processor uses virtual addresses, main memory uses physical memory addresses Virtual address space is organized into pages The system references the page table to translate addresses each process has its own page table the page table content is maintained by OS valid virtual page # offset physical page # offset
Hierarchical page table Break the virtual page number into several pieces If one piece has N bits, build an 2N -ary tree Only store the part of the tree that contain valid pages valid Walk down the tree to translate the virtual address level index level 2 index offset physical page # offset 3
Hierarchical page table valid 4
Page fault When the referenced memory page is not mapped to physical memory The processor raises an exception and transfers the control (change the PC) to operating system code that handles the page fault LRU or other page replacement policies to decide the evicting page Fetch the demanding page from secondary storage (hard drive, SSD) Transfer the control back to the original program Could be slow! The access time of hard drive is more than 6ms 5
PC Pipeline with exception PCWrite PCSrc m ux IF/IDWrite hazard detection unit IF/ID ID/EX EX/MEM MEM/WB Control m ux ID/EX.MemRead WB ME EX m ux m ux WB ME WB RegWrite 4 Add Shi> le> 2 Add RegWrite Cause EPC MemWrite Read Address Instruc(on Memory inst[3:] inst[5:] inst[25:2] inst[2:6] 6 Read Reg Register Read Reg 2 File Write Reg Write Data signextend 32 Read Data Read Data 2 m ux ForwardA m ux RegDst ForwardB m ux Zero ALU ALUop Address Write Data Data Memory MemRead Read Data MemtoReg m ux ForwardA ForwardB forwarding unit ALUSrc 6
VM & Cache 7
Cache + Virtual Memory. VA Processor $ PA 3. 2. PA Too slow! main memory Processor. path! VA the critical TLB increase TLB $ 2. PA TLB: Translation Look-aside Buffer main memory a cache of page table small, high-associativity miss penalty: access to page table in main memory 8
Cache+Virtual Memory Processor Virtual Cache The cache also uses virtual addresses Address translation is required only when miss.. VA TLB $. VA 2. PA main memory 9
Problems of Virtual Cache Multiple processes accessing to the same virtual address Process A accessed x. Process B also want to access x Flush the cache when context switch Attach PID to cache virtual addresses of A x x? virtual addresses of B x 2
Problems of Virtual Cache Alias: A physical address maps to different virtual addresses Two copies of data in cache due to copy on write. One may get the wrong data if the other is modified. virtual address x x3 x x3 physical address xff 2
Virtual indexed, physical tagged cache Force aliasing virtual addresses mapped to the same cache location. Cache stores tag fields of physical addresses the physical tag is also the physical page number! virtual page # TLB physical page # page offset $ index+block offset physical tag == physical page # C = ABS lg(s)+lg(b) = 2 if A = (DM cache) C = *(2 2 ) = 4KB physical page # offset 22
Virtual indexed, physical tagged cache. VA Processor. VA Force aliasing virtual addresses mapped to the same cache location. Cache stores tag fields of physical addresses 2. PA TLB = miss $ main memory 2. PA 23
9 bits index, 6 bits offset AMD Athlon 64 64KB D-L cache, 64B block, 2-way associative. Windows 7 has 4KB page size Page offset 2 bits How to achieve virtual indexed, physically tagged? Check a total of 8 possible location. Invalid all aliasing blocks and fetch new from low level hierarchy. 25
Q & A 27