ESD Protection Circuits: Basics to nano-metric ASICs Manoj Sachdev University of Waterloo msachdev@ece.uwaterloo.ca September 2007 1
Outline Group Introduction ESD Basics Basic ESD Protection Circuits Nano-metric ESD Challenge ESD circuits for nano-metric regime 2
Group Introduction 5 PhDs, 2 masters and 2 PDFs Applied, industrially driven research Generous funding levels Core strengths in circuit design, testing, quality and reliability 3
Group: Low Power Research Driven by low power signal processing & bio-implantable applications Research focus Active power reduction, clocking strategies Dynamic voltage scaling architecture for portable app. Leakage power reduction: Investigation of RBB effectiveness with scaling 4
Group: High Performance Circuits Driven by high speed arithmetic circuits (Adders, register files, ALU), and CDRs Research focus To build timing diagnostics into multi-ghz ALUs Leakage and active power reduction Clock de-skewing Thermal issues in high performance circuits 5
Group: Memory Research Driven by embedded SRAMs and Soft Error Robustness Research Focus SRAM cell stability & ckt techniques for detection Low power embedded SRAMs Soft Error Robust memories & flip-flops Error Correction Circuit s for soft error mitigation 6
Group: ESD Research Driven by reducing chip failures due to ESD Research Focus ESD strategies for multiple supply domains ESD protection circuits for High speed I/Os Fast response ESD protection circuits 7
Outline Group Introduction ESD Basics Basic ESD Protection Circuits Nano-metric ESD Challenge ESD circuits for nano-metric regime 8
ESD Basics :Motivation Electrostatic Discharge (ESD) is responsible for up to 70% of failures in semiconductor industry An ESD event creates high currents and electric fields in semiconductor devices High currents may lead to thermal runaway High electric fields cause dielectric breakdown 9
ESD Basics When two dissimilar materials are separated an ESD charge may develop Caused by the removal of electrons from surface atoms of materials Factors Magnitude of static charge Contact quality Rate of separation 10
Human Body Model (HBM) R A B R b =1.5k V C b =100pF DUT Mimics the human touching of the Device Under Test (DUT) Voltages as high as 10kV can be developed HBM modeled by series resistance (R b = 1.5kΩ) and capacitance (C b = 100pF) 11
Machine Model (MM) R A B 0.5uH V 200pF DUT Represents the damage caused by charged machine touching the DUT Voltages as high as 100-500V can be generated MM is modeled by capacitance (C = 200pF) and series inductance of machine (0.μ5H) 12
Charge Device Model (CDM) R A B V DUT Cap Discharge event between charged DUT and grounded conductor Modeled by Capacitor (Cap) in series with DUT Total Capacitance (Cap) is dependant on Device, package impedance 13
ESD Stress Comparison HBM rise time ~ 2-10ns, decay time 130-170ns CDM very high amplitude, occurs for 500ps-1000ps CDM failures on rise due to automated manufacturing 14
Zapping Modes Positive ESD with respect to V SS (PS-mode) Negative ESD with respect to V SS (NS-mode) V DD V DD V ESD V ESD V SS V SS 15
Zapping Modes Positive ESD with respect to V DD (PD-mode) Negative ESD with respect to V DD (ND-mode) V DD V DD V ESD V ESD V SS V SS 16
HBM / MM / CDM Testers HBM/MM/CDM testers apply ESD stress to the DUT Magnitude/polarity of the stress set by the user Test can be destructive Results in pass or fail The device fails when leakage is increased significantly ICMS-700 HBM/MM tester 17
TLP Tester Transmission Line Pulse (TLP) is becoming popular Measures I-V characteristic of the DUT Non-destructive Programmable current pulse of 100ns are applied to the DUT 2 nd breakdown current determines the ESD robustness Barth 4002 TLP tester 18
Outline Group Introduction ESD Basics Basic ESD Protection Circuits Nano-metric ESD Challenge ESD circuits for nano-metric regime 19
ESD Protection Methods Snapback-based Non-snapback-based Turn on before oxide breakdown Trigger and conduct during the whole ESD event Minimum parasitics Do not trigger under normal power-up 20
Diode Under ESD Conditions Forward biased: Low trigger voltage Low on resistance Reverse biased: High trigger voltage High on resistance 21
MOS Under ESD Conditions Has a parasitic bipolar transistor Avalanche breakdown gives I gen and I sub When V base = 0.7V, npn turns on Snapback When I(drain) = I t2, npn can be destroyed Drain n+ n+ I gen V base I sub R sub p-sub 22
Snapback Protection: MOSFET MOSFET is used in Grounded- Gate configuration (GGNMOS) V DD PAD PreDriver Substrate and Gate triggering is often needed I/O PAD GGNMOS PreDriver V SS PAD ESD Protection Device Buffer stage 23
ESD Protection Wish List V t1 < Oxide breakdown To trigger NMOS before oxide breaks down V t2 > V t1 To ensure uniform triggering of all fingers V h > V DD To enhance latch-up immunity (V DD + 10%) I t2 as high as possible Increase current carrying capability ESD A GGNMOS cannot meet all the above requirements for contemporary technologies 24
SCR Under ESD Conditions SCR is a pnpn device In CMOS the junctions are: p + -nwell-psub-n + Anode V DD PAD PreDriver n + p + n + p + n-well I/O PAD p + n - p - PreDriver n + p-sub V SS PAD ESD Protection Device Buffer stage 25
SCR Characteristic Avalanche breakdown of nwell-psub I Rnwell and I Rpsub When V BE reaches 0.7V, npn (or pnp) turns on Positive feedback turns on the pnp (or npn) Snapback Anode I(anode) R n-well (V t2, I t2 ) (V h, I h ) (V t1, I t1 ) R p-sub V(anode) 26
ESD Devices: Comparison Protection level: SCR and FB diode are the best Trigger voltage: FB Diode is too low NMOS is the best SCR should be modified Holding voltage: NMOS is ok SCR should be modified Figure of merit Protection level/capacitance 27
Non-Snapback Protection: Clamps ESD event V(1) rises turning on M 0 R C C C + inverters should keep M 0 on to discharge all ESD energy Advantages Protect against different zapping conditions Disadvantages Can turn on during normal power-up ESD event: t r : between 100ps and 60ns duration: up to 1μs Regular power-up: In millisecond range Hot plug app. power-up as low as 1μs 28
Outline Group Introduction ESD Basics Basic ESD Protection Circuits Nano-metric ESD Challenge ESD circuits for nano-metric regime 29
Challenges with Scaling Breakdown Voltage of CMOS devices is decreasing Traditional ESD structures not scaling with technology scaling Larger ULSI, thinner metallization, shallower junctions Increasingly difficult to provide low impedance, low capacitance discharge path 30
Challenges: Charged Device Model 14 12 10 8 6 Current (A) 4 2 0 HBM MM CDM -2-4 -6 0 20 40 60 80 100 120 Time (ns) Lower Technologies (90nm, 65nm) damage occur at lower voltages Traditional ESD circuits trigger slower High speed chips larger package decoupling cap Higher CDM discharge current!! CDM failures on rise due to automated manufacturing 31
Challenges: Multiple Supply Domains Multiple supply domains in SoC s Pin to pin ESD protection requirement Multiple zapping modes Challenge to Overcome Noise Coupling & groundbouncing issues between analog & digital supplies 32
Challenges: Multiple Chip Module Resistance of the path can be very high (Multiple Chip Module) Minimization of Parasitic Capacitance attributed to the High Speed I/O s due to ESD Circuit 33
Outline Group Introduction ESD Basics Basic ESD Protection Circuits Nano-metric ESD Challenge ESD circuits for nano-metric regime 34
Strategy Device Simulation MOS models, circuit simulators are not designed to handle snapback behavior ESD circuits are designed with device simulators (Medici and Sequoia) Device cross section is created in the simulator Quasi-DC simulation predicts DC characteristic, i.e. V t1 and V h I t2 is estimated using thermal simulation and monitoring maximum temperature of the ESD protection device 35
Design Steps 1. Calibrate the device simulator with the desired technology Junction depth and substrate doping are available from technology documents 2. Verify the technology model by simulating a MOS transistor Trial and error is used to achieve the typical I(on), V th, current gain and 3. Draw the cross-section of the ESD device 36
Design Example #1 LVTSCR p-type n-type contact oxide Mesh of the Low-Voltage-Triggered SCR (LVTSCR) created in Medici Reducing grid spacing increases accuracy and simulation time 37
Snapback Protection Requirements Reduce first breakdown voltage SCR has higher V t1 compared to MOS V t1 of both MOS and SCR are higher than oxide breakdown voltage Latch-up immunity Very important in SCR devices Increasing second breakdown current SCR has higher I t2 per width Reducing parasitic capacitance SCR provides protection with less capacitance I(anode) (V t2, I t2 ) (V h, I h ) (V t1, I t1 ) 38 V(anode)
Gate-Coupling V gs I sub npn triggers faster V t1 For higher V gs (strong inversion region): impact ionization is decreased V t1 increases 5 4.8 4.6 4.4 Vt1 (V) 4.2 4 3.8 3.6 3.4 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 V(Gate) (V) 39
Substrate Triggering V sub Transistor triggers with lower V t1 Drain 5 4.5 n + n + Vt1 (V) 4 3.5 p-sub 3 2.5 Sub 2 0 0.25 0.5 0.75 1 1.25 1.5 V(Sub) (V) 40
GST-LVTSCR SCR is modified by adding a gate electrode to reduce V t1 (LVTSCR) M G provides gate triggering Can be as small as 5μm M S provides substrate triggering Simulation results V t1 reduces from 12V to 4.85V Semenov et. al., Microelectronics Reliability, 2005 41
GST-LVTSCR (Measurement) GST-LVTSCR was fabricated in 0.13μm CMOS technology TLP measurements V t1 = 5V I t2 = 1.8A HBM measurements Leakage (A) 1.00E-12 1.00E-10 1.00E-08 1.00E-06 1.00E-04 2.50E+00 2.00E+00 1.50E+00 Current (A) 1.00E+00 TLP I-V 5.00E-01 TLP Leakage Device passes ±3kV 0.00E+00 0 2 4 6 8 10 Voltage (V) 42
Example #2 Increasing V h In holding region both Q 1 and Q 2 are in saturation SCR Anode R n-well I 1 Q 1 V h = V EB1 + V CE2(sat) High V h SCR (R E is added) Q 2 R E I 2 R p-sub V h = V EB1 + V CE(sat) + R E I 1 V h = V EB1 + V CE(sat) + V EB1 R E /R n-well Anode Cathode R E Cathode R E V h n + p + n + p + n-well Semenov et. al., ISQED, 2004 p-sub 43
Increasing Holding Voltage Simulation results Applied to SCR V h is increased without an increase in V t1 R E is implemented with diode and MOS and applied to LVTSCR TLP Measurement results V h is increased from 2.29V to 3.49V and 4.55V Increase in V t1 is less than 8% 1 0.01 0.0001 Log I(anode) (A) 1E-06 1E-08 1E-10 1E-12 1.20E-01 LVTSCR HighVhMOS 1.00E-01 HighVhDiode 8.00E-02 I(anode) (A) 6.00E-02 4.00E-02 2.00E-02 V(anode) (V) 0 5 10 15 20 25 SCR R=2k R=5k 44 0.00E+00 0 1 2 3 4 5 6 7 8 V(anode) (V)
Example #3 ESD Clamps To solve false triggering, the triggering circuit is divided into rise time detector and delay element Time constant is approximately 40ns Delay of the delay element should be more than 1μs 45
Thyristor-Based Clamp V DD C C M 1 M 4 1 2 3 M 0 R C M 2 M 3 R 1 V SS Rise Time Detector Delay Element CMOS thyristor is used to create the delay element R C C C = 40ns R 1 to keep M 0 off under normal conditions Hossein et. al., ESD Symposium 2007 46
Circuit-Level Simulation The clamp is circuit simulated with 2kV HBM stress V(3) shows that clamp turns off after 1μs Peak voltage of the clamp is less than 6V Voltage (V) 7 6 5 4 3 2 1 0 VDD V(1) V(3) -1 0E+0 3E-7 5E-7 8E-7 1E-6 1E-6 2E-6 Time (s) 47
Device-Level Simulation Device simulation is done with Sequoia Peak temperature is in transistor M 0 During a 2kV HBM stress T max of the clamp is 375K Hot-spot is in the gatedrain boundary 48
Measurements Clamp was fabricated in 0.18μm technology Log Leakage (A) HBM test 1E-09 0.0000001 0.00001 0.001 0.1 10 2.5 Clamp passes 3kV stress and fails at 3.5kV TLP test Current (A) 2 1.5 1 Leakage current is 7nA Second breakdown current is 1.8A 0.5 0 TLP I-V TLP Leakage 0 5 10 15 Voltage (V) 49
Example #4 CML Driver Design Two stage 3Gbps CML driver is designed in 0.13μm CMOS tech. Diff. Input Diff. Output 400mV 800mV Bias of the driver is provided through an external resistor Rise/fall time Jitter 150ps 1ps 50
Measured Results 5000 V out t r Jitter 4000 CML (simulation) 850mV 116ps 229fs Jitter (fs) 3000 2000 CML+MOS (measured) CML+LVTSCR (measured) 500mV 315ps 3.7ps 700mV 148ps 700fs Both Protection schemes achieved 3kV HBM protection 1000 0 0 100 200 300 400 500 600 700 ESD Capacitance (ff) Beyond C ESD =150fF jitter increases significantly Hossein et. al., CICC 2007 51
Conclusion ESD remains major cause of chip failures ESD affects entire manufacturing from devices systems Significant challenges for nano-metric technologies ESD circuit design is an art Device simulator are useful in design process 52
Acknowledgement Help of Hossein Sarbishaei, Sumanjit Singh, and Oleg Semenov is greatly appreciated for this presentation 53