VHDLPrimeri Poglavlje3.doc. end process seq; Slika 3.1: Anatomija osnovne definicije test bench-a

3. Verifikacija projekta - Test bench entity TestBench is end entity TestBench; architecture TB_Arhitektura of TestBench is component UUT (Arhitektura_UUT) port( end component UUT; prazan entitet -- deklarisanje lokalnih signala i konstanti { { Deklaracija komponente za UUT { Po~etak opisa arhitekture u1: UUT port map ( konkurentno: ); sekvencionalno: seq: process end process seq; end architecture TB_Arhitektura; { { Instanciranje komponente koja se testira Testiranje Kraj opisa arhitekture Slika 3.1: Anatomija osnovne definicije test bench-a Definisanje pobude i željenog odziva Da bi se ispitao odziv Prvog_primera na sve moguće kombinacije ulaznih signala potrebno je da se kolo pobudi sa najviše osam kombinacija prikazanih u Tabeli 3.1. Tabela 3.1 A B C Y 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 1

A 0 40 80 120 160 200 240 280 320 B 0 40 80 120 160 200 240 280 320 C 0 40 80 120 160 200 240 280 320 Y 0 40 80 120 160 200 240 280 320 Slika 3.2: Vremenski dijagram pobudnih signala (A, B, C) i očekivanog odziva (Y) Vreme na slici 3.2 dato je u ns. Primer 3.1: library IEEE; use IEEE.std_logic_1164.all; entity TestBench is end entity TestBench; architecture Prvi_projekat_TB of TestBench is component Prvi_projekat port (A, B, C: in std_logic; Y: out std_logic); end component; signal A, B, C, Y: std_logic; -- deklarisanje signala -- instanciranje komponente koja se testira UUT: Prvi_projekat port map ( A => A, B => B, C => C, Y => Y); -- Opis pobude preko konkurentne dodele vrednosti signala -- Definisanje pobude signala C C <= 0, 1 after 40ns, 0 after 80ns, 1 after 120ns, 0 after 160ns, 1 after 200ns, 0 after 240ns, 1 after 280ns, 0 after 320ns; -- Definisanje pobude signala B B <= 0, 1 after 80ns, 0 after 160ns, 1 after 240ns; -- Definisanje pobude signala A A <= 0, 1 after 160ns; end architecture Prvi_projekat_TB;

Primer 3.2: library IEEE; use IEEE.std_logic_1164.all; entity TestBench is end entity TestBench; architecture Prvi_projekat_TB of TestBench is component Prvi_projekat port (A, B, C: in std_logic; Y: out std_logic); end component; signal A, B, C, Y: std_logic; -- deklarisanje signala -- Uveden 3-bitni signal 'ulaz' da bi se olaksao opis pobude -- MSB signala ulaz ulaz(2) odgovara signalu A, -- ulaz(1) odgovara signalu 'B' -- LSB signala ulaz ulaz(0) odgovara signalu C, signal ulaz: std_logic_vector (2 downto 0); -- definisanje konstante constant PropDelay: time := 40 ns; -- UUT: Prvi_projekat port map (A => ulaz(2), B => ulaz(1), C => ulaz(0), Y => Y); -- Opis pobude sekvencijalno u okviru procesa 'seq' seq: process ulaz <= "000"; ulaz <= "001"; ulaz <= "010"; ulaz <= "011"; ulaz <= "100"; ulaz <= "101"; ulaz <= "110"; ulaz <= "111"; end process seq; end architecture Prvi_projekat_TB;

- k-ti član vektora ulaz izdvaja se jednostavno pisanjem ulaz(k); - dodeljivanje vrednosti vektoru zahteva da se umesto jednostrukih, koriste dvostruki navodnici. Napomena: U narednim primerima koristi se Test Banch Wizard pomocu koga je deo VHDL kôda automatski generisan. Taj deo kôda je zasencen.

Primer 3.3: --************************************************************* --* This file is automatically generated test bench template * --* By ACTIVE-VHDL <TBgen v1.10>. Copyright (C) ALDEC Inc. * --* * --* This file was generated on: 7:05 PM, 11/30/01 * --* Tested entity name: Prvi_projekat * --* File name contains tested entity: $DSN\src\prviprojekatstruct.vhd * --************************************************************* library ieee; use ieee.std_logic_1164.all; -- Add your code here... use Nase_primitive.all; entity tb_wizard is end tb_wizard; architecture TB_WIZARD_ARCH of tb_wizard is -- Component declaration of the tested unit component Prvi_projekat port( A : in std_logic; B : in std_logic; C : in std_logic; Y : out std_logic ); end component; -- Stimulus signals - signals mapped to the input and inout ports of tested entity signal A : std_logic; signal B : std_logic; signal C : std_logic; -- Observed signals - signals mapped to the output ports of tested entity signal Y : std_logic; -- Add your code here... signal ulaz: std_logic_vector (2 downto 0); signal izlaz: std_logic; constant PropDelay: time := 40 ns; constant Citaj: time := 10ns; -- Unit Under Test port map UUT : Prvi_projekat port map (A => ulaz(2), B => ulaz(1), C => ulaz(0), Y => Y );

-- Add your stimulus here... seq: process ulaz <= "000"; izlaz <= '1'; wait for Citaj; assert (Y = izlaz) report "Greska za 000" severity warning; ulaz <= "001"; izlaz <= '1';wait for Citaj; assert (Y = izlaz) report "Greska za 001" severity warning; ulaz <= "010"; izlaz <= '0';wait for Citaj; assert (Y = izlaz) report "Greska za 010" severity warning; ulaz <= "011"; izlaz <= '1';wait for Citaj; assert (Y = izlaz) report "Greska za 011" severity warning; ulaz <= "100"; izlaz <= '0'; wait for Citaj; assert (Y = izlaz) report "Greska za 100" severity warning; ulaz <= "101"; izlaz <= '1'; wait for Citaj; assert (Y = izlaz) report "Greska za 101" severity warning; ulaz <= "110"; izlaz <= '0';wait for Citaj; assert (Y = izlaz) report "Greska za 110" severity warning; ulaz <= "111"; izlaz <= '1'; wait for Citaj; assert (Y = izlaz) report "Greska za 111" severity warning; end process seq; end TB_WIZARD_ARCH; configuration TESTBENCH_FOR_Prvi_projekat of tb_wizard is for TB_WIZARD_ARCH for UUT : Prvi_projekat use entity work.prvi_projekat(protok_podataka); end for; end for; end TESTBENCH_FOR_Prvi_projekat;

dat a2 Zapi s dat a1 No MU IN i 1 0 1 1 0 1 0 1 0 0 0 0 1 1 5 0 1 2 0 0 0 1 1 1 1 0 0 1 1 0 0 7 0 1 3 1 0 1 1 1 0 1 1 0 1 0 0 1 2 1 0................................................ n 0 1 0 1 0 1 0 0 0 1 0 0 0 9 1 1 Deklarisanje zapisa Zapi s Type Zapi s i s record dat a1: st d_l ogi c_vect or ( 7 downt o 0) ; dat a2: st d_l ogi c_vect or ( 4 downt o 0) ; No: i nt eger; MU: st d_l ogi c; IN: st d_l ogi c; end record Zapi s; Poziv na pojedine delove Zapi s - a: referenca vrednost Zapi s. dat a1( 2) 0001110 Zapi s. dat a2( 3) 01001 Zapi s. No (1) 5 Zapi s. MU (2) 0 Zapi s. I N (2) 1 Slika 3.3: Grafička predstava, deklaracija i poziv na pojedine vrednosti zapisa

Primer 3.4: --************************************************************* --* This file is automatically generated test bench template * --* By ACTIVE-VHDL <TBgen v1.10>. Copyright (C) ALDEC Inc. * --* * --* This file was generated on: 7:05 PM, 11/30/01 * --* Tested entity name: Prvi_projekat * --* File name contains tested entity: $DSN\src\prviprojekatstruct.vhd * --************************************************************* library ieee; use ieee.std_logic_1164.all; -- Add your code here... use std.textio.all; use Nase_primitive.all; entity tb_wizard is end tb_wizard; architecture TB_WIZARD_ARCH of tb_wizard is -- Component declaration of the tested unit component Prvi_projekat port( A : in std_logic; B : in std_logic; C : in std_logic; Y : out std_logic ); end component; -- Stimulus signals - signals mapped to the input and inout ports of tested entity signal A : std_logic; signal B : std_logic; signal C : std_logic; -- Observed signals - signals mapped to the output ports of tested entity signal Y : std_logic; -- Add your code here... signal ulaz: std_logic_vector (2 downto 0); signal izlaz: std_logic; constant PropDelay: time := 40 ns; constant Citaj: time := 10ns; constant Broj_kombinacija: integer :=8; type Vektor is record Pobuda: std_logic_vector (2 downto 0); Kontrola: std_logic; end record; type Kombinacije is array (0 to Broj_kombinacija -1) of Vektor; constant TabelaVektora: Kombinacije := ((Pobuda => "000", Kontrola => '1'), (Pobuda => "001", Kontrola => '1'), (Pobuda => "010", Kontrola => '0'),

(Pobuda => "011", Kontrola => '1'), (Pobuda => "100", Kontrola => '0'), (Pobuda => "101", Kontrola => '1'), (Pobuda => "110", Kontrola => '0'), (Pobuda => "111", Kontrola => '1')); -- Unit Under Test port map UUT : Prvi_projekat port map (A => ulaz(2), B => ulaz(1), C => ulaz(0), Y => Y ); -- Add your stimulus here... Petlja: process variable Greska: boolean := false; variable Privremeni: Vektor; variable Poruka: line; for i in TabelaVektora'range loop Privremeni := TabelaVektora(i); ulaz <= Privremeni.Pobuda; izlaz <= Privremeni.Kontrola; wait for Citaj; if Y /= izlaz then write (Poruka, string'("greska u ")); write (Poruka, now); writeline (output, Poruka); Greska := true; end if; end loop; assert Greska report " Nema gresaka" severity note; wait; end process Petlja; end TB_WIZARD_ARCH; configuration TESTBENCH_FOR_Prvi_projekat of tb_wizard is for TB_WIZARD_ARCH for UUT : Prvi_projekat use entity work.prvi_projekat(strukturni_opis); end for; end for; end TESTBENCH_FOR_Prvi_projekat;

Citanje test vektora za Prvi_projekat iz fajla Test vektor Prvog projekta i datum: # Test vektor prvog projekta # 08. Dec. 2001 0001 0011 0100 0110 1000 1011 1100 1111 Primer 3.5: --************************************************************* --* This file is automatically generated test bench template * --* By ACTIVE-VHDL <TBgen v1.10>. Copyright (C) ALDEC Inc. * --* * --* This file was generated on: 9:17 PM, 12/2/01 * --* Tested entity name: Prvi_projekat * --* File name contains tested entity: $DSN\src\prviprojekatstruct.vhd * --************************************************************* library ieee; use ieee.std_logic_1164.all; -- Add your library and packages declaration here... use IEEE.STD_LOGIC_TEXTIO.all; use STD.TEXTIO.all; use Nase_primitive.all; entity prvi_projekat_tb is end prvi_projekat_tb; architecture TB_ARCHITECTURE of prvi_projekat_tb is -- Component declaration of the tested unit component Prvi_projekat port( A : in std_logic; B : in std_logic; C : in std_logic; Y : out std_logic ); end component; -- Stimulus signals - signals mapped to the input and inout ports of tested entity signal A : std_logic; signal B : std_logic; signal C : std_logic; -- Observed signals - signals mapped to the output ports of tested entity signal Y : std_logic; -- Add your code here...

signal izlaz: std_logic; constant PropDelay: time := 40 ns; constant Citaj: time := 10ns; -- ovo je pomocni signal signal TacanOdziv: boolean := false; -- Deklarisanje fajla iz koga se cita file UlazniFajl: text is in "ulaznifajl.txt"; type Vektor is record Pobuda: std_logic_vector (2 downto 0); Kontrola: std_logic; end record; -- Unit Under Test port map UUT : Prvi_projekat port map (A => A, B => B, C => C, Y => Y ); --Below VHDL code is an inserted.\src\ulaznifajl.vhs --User can modify it... -- Add your stimulus here... Ucitaj: process -- Ucitava iz fajla -- "UlazniFajl" variable Red: line; variable DobroCita: boolean; variable Privremeni: Vektor; while not endfile (UlazniFajl) loop readline (UlazniFajl, Red); read (Red, Privremeni.Pobuda, good => DobroCita); next when not DobroCita; read (Red, Privremeni.Kontrola); A <= Privremeni.Pobuda(2); B <= Privremeni.Pobuda(1); C <= Privremeni.Pobuda(0); izlaz <= Privremeni.Kontrola; end loop; assert TacanOdziv report "Simulacija izpravno okoncana" severity note; wait; end process Ucitaj;

-- Kontrola izlaza Proveri: process variable Poruka: line; wait for Citaj; if Y /= izlaz then write (Poruka, string'("greska u trenutku ")); write (Poruka, now); writeline (output, Poruka); TacanOdziv <= True; end if; end process Proveri; end TB_ARCHITECTURE; configuration TESTBENCH_FOR_Prvi_projekat of prvi_projekat_tb is for TB_ARCHITECTURE for UUT : Prvi_projekat use entity work.prvi_projekat(strukturni_opis); end for; end for; end TESTBENCH_FOR_Prvi_projekat; end TESTBENCH_FOR_Prvi_projekat;

Kasnjenje VH 0,9 VH 0,1 VH TR TF Slika 3.4: Električna šema NOR2 kola u CMOS tehnologiji i R/F kašnjenje Primer 3.6: InertniA <= A after 10ns; ZakasneliA <= transport A after 10ns; Na slici 3.5 prikazani su efekti koji nastaju kada se na ulazu pojavi signal čija je dužina trajanja veća (a) i manja (b) od definisanog kašnjnja 10ns. 20ns 5ns A InertniA 10ns InertniA 10ns ZakasneliA ZakasneliA a) b) Slika 3.5: Razlika izmedju inercionog i transportnog kašnjenja

Modeli komponenata sa kasnjenjem Primer 3.7: --Model invertora library IEEE; use IEEE.std_logic_1164.all; entity INVT is generic ( thl: time := 2 ns; tlh: time := 1 ns); port ( i: in std_logic; o: out std_logic); end entity INVT; architecture rtlt of INVT is o <= (not i) after tlh when (i = '0') else (not i) after thl; end architecture rtlt; -- ======================================= -- Model AND2 library IEEE; use IEEE.std_logic_1164.all; entity AND2T is generic ( tlh: time := 2ns; thl: time := 4ns); port ( i1: in std_logic; i2: in std_logic; y: out std_logic); end entity AND2T; architecture rtlt of AND2T is y <= '1' after tlh when (i1 = '1' and i2 = '1') else '0' after thl; end architecture rtlt; -- ====================================== -- Model OR2 library IEEE; use IEEE.std_logic_1164.all; entity OR2T is generic ( thl: time := 2 ns; tlh: time := 1 ns); port ( i1: in std_logic; i2: in std_logic; y: out std_logic);

end entity OR2T; architecture rtlt of OR2T is y <= '1' after tlh when (i1 = '1' or i2 = '1') else '0' after thl; end architecture rtlt; -- ====================================== -- Nove modele smesticemo u paket Nase_primitiveT library IEEE; use IEEE.std_logic_1164.all; package Nase_primitiveT is component INVT generic ( thl: time; tlh: time); port ( i: in std_logic; o: out std_logic); end component INVT; component AND2T generic ( thl: time; tlh: time); port ( i1: in std_logic; i2: in std_logic; y: out std_logic); end component AND2T; component OR2T generic ( thl: time; tlh: time); port ( i1: in std_logic; i2: in std_logic; y: out std_logic); end component OR2T; end package Nase_primitiveT; -- ======================================= library IEEE; use IEEE.std_logic_1164.all; entity Prvi_projekat is port ( A: in std_logic; B: in std_logic; C: in std_logic; Y: out std_logic ); end entity Prvi_projekat; use work.nase_primitivet.all; -- koristi sve -- komponente iz -- paketa "Nase_primitiveT"

-- Definisanje strukturnog opisa arhitekture architecture Strukturni_opisT of Prvi_projekat is -- nema deklaracije "component" signal nota, notb, and2_out: std_logic; INV_1: invt generic map (thl => 10ns, tlh => 20ns) port map (i => A, o => nota); INV_2: invt generic map (thl => 10ns, tlh => 20ns) port map (i => B, o => notb); I_kolo: AND2T generic map (thl => 10ns, tlh => 20ns) port map (i1 => nota, i2 => notb, y => and2_out); ILI_kolo: OR2T generic map (thl => 10ns, tlh => 20ns) port map (i1 => and2_out, i2 => C, y => Y); end architecture Strukturni_opisT; -- =========================================================

--************************************************************* --* This file is automatically generated test bench template * --* By ACTIVE-VHDL <TBgen v1.10>. Copyright (C) ALDEC Inc. * --* * --* This file was generated on: 12:54 PM, 12/9/01 * --* Tested entity name: Prvi_projekat * --* File name contains tested entity: $DSN\src\prviprojekatstructT.vhd * --************************************************************* library ieee; use ieee.std_logic_1164.all; -- Add your library and packages declaration here... use IEEE.STD_LOGIC_TEXTIO.all; use STD.TEXTIO.all; use Nase_primitiveT.all; entity prvi_projekat_tb is end prvi_projekat_tb; architecture TB_ARCHITECTURE of prvi_projekat_tb is -- Component declaration of the tested unit component Prvi_projekat port( A : in std_logic; B : in std_logic; C : in std_logic; Y : out std_logic ); end component; -- Stimulus signals - signals mapped to the input and inout ports of tested entity signal A : std_logic; signal B : std_logic; signal C : std_logic; -- Observed signals - signals mapped to the output ports of tested entity signal Y : std_logic; -- Add your code here... signal izlaz: std_logic; constant PropDelay: time := 100 ns; constant Citaj: time := 50ns; -- ovo je pomocni signal signal TacanOdziv: boolean := false; -- Deklarisanje fajla iz koga se cita file UlazniFajl: text is in "ulaznifajl.txt"; type Vektor is record Pobuda: std_logic_vector (2 downto 0); Kontrola: std_logic; end record; -- Unit Under Test port map UUT : Prvi_projekat port map (A => A, B => B,

C => C, Y => Y ); -- Add your stimulus here... Ucitaj: process -- Ucitava iz fajla -- "UlazniFajl" variable Red: line; variable DobroCita: boolean; variable Privremeni: Vektor; while not endfile (UlazniFajl) loop readline (UlazniFajl, Red); read (Red, Privremeni.Pobuda, good => DobroCita); next when not DobroCita; read (Red, Privremeni.Kontrola); A <= Privremeni.Pobuda(2); B <= Privremeni.Pobuda(1); C <= Privremeni.Pobuda(0); izlaz <= Privremeni.Kontrola; end loop; assert TacanOdziv report "Simulacija izpravno okoncana" severity note; wait; end process Ucitaj; -- Kontrola izlaza Proveri: process variable Poruka: line; wait for Citaj; if Y /= izlaz then write (Poruka, string'("greska u trenutku ")); write (Poruka, now); writeline (output, Poruka); TacanOdziv <= True; end if; end process Proveri; end TB_ARCHITECTURE; configuration TESTBENCH_FOR_Prvi_projekat of prvi_projekat_tb is for TB_ARCHITECTURE for UUT : Prvi_projekat use entity work.prvi_projekat(strukturni_opist); end for; end for; end TESTBENCH_FOR_Prvi_projekat; -- =======================================================