ECE U530 Digital Hardware Synthesis. Course Accounts and Tools

Transcription

1 ECE U530 Digital Hardware Synthesis Prof. Miriam Leeser Sept 13, 2006 Lecture 3: Basic VHDL constructs Signals, Variables, Constants VHDL Simulator and Test benches Types Reading: Ashenden 2.1, 2.2, 5.1, 5.2 Complete tutorial by Monday Sept 18 Quiz in class on Monday, Sept 25 based on tutorial ECE U530 F06 Course Accounts and Tools You must have a COE account for this course Programming assignments will be done on WinCOE systems on second floor of Snell Engineering or 9 Hayden labs Tools: Xilinx ISE version 6.2i, Modelsim 5.7e If you are registered for this class, A sub-directory called Courses/ECEU530 will automatically appear in your home directory IMPORTANT: Do NOT create this directory! Do not use this as your active working directory! only files submitted for homework should be in this directory use your home directory (Z:) for all design work! tutorial should be done in your home directory 2

2 Xilinx and Modelsim Tutorial Create a directory for this course in your COE home directory: Open an Explorer window (right click on Start and choose Explore) Navigate to Coewin winusers User_Name This is your directory on the COE system Create a new folder called 530local: right click in the directory and choose New Folder (You may already have a folder called ECEU530) Note: It is important that you not put empty spaces in any directory in the path for this course. The software tools do not recognize empty spaces. All names must be 8 characters or less. 3 For Help with Tools For help with Xilinx or Modelsim: send an to mel@coe.neu.edu Tell me, as specifically as possible: what the problem is what machine you are running on and where Is it a problem in Modelsim or Xilinx... For help with login, coe account,etc. send to: help@coe.neu.edu 4

3 5 6

4 7 Analysis Elaboration Simulation Synthesis Design Processing 8

5 Analysis Check for syntax and semantic errors syntax: grammar of the language semantics: the meaning of the model Analyze each design unit separately entity declaration architecture body Analyzed design units are placed in a library in an implementation dependent internal form current library is called work 9 Elaboration Flattening the design hierarchy create ports create signals and processes within architecture body for each component instance, copy instantiated entity and architecture body repeat recursively bottom out at purely behavioral architecture bodies Final result of elaboration flat collection of signal nets and processes 10

6 Elaboration Example d0 reg4(struct) bit0 d_latch d q q0 clk d1 bit1 d_latch d q q1 clk d2 bit2 d_latch d q q2 clk d3 bit3 d_latch d q q3 en clk gate and2 a y b int_clk clk 11 Elaboration Example d0 reg4(struct) bit0 d_latch(basic) d q q0 clk bit1 d1 d_latch(basic) d q q1 clk bit2 d2 d_latch(basic) d q q2 clk bit3 d3 d_latch(basic) d q q3 gate clk en clk and2(basic) a y b int_clk process with variables and statements 12

7 Simulation Execution of the processes in the elaborated model Discrete event simulation time advances in discrete steps when signal values change events A processes is sensitive to events on input signals specified in wait statements resumes and schedules new values on output signals schedules transactions event on a signal if new value different from old value 13 14

8 Test Benches Testing a design by simulation Use a test bench model an architecture body that includes an instance of the design under test applies sequences of test values to inputs monitors values on output signals either using simulator or with a process that verifies correct operation 15 Test Bench Example entity test_bench is end entity test_bench; architecture test_reg4 of test_bench is signal d0, d1, d2, d3, en, clk, q0, q1, q2, q3 : bit; begin dut : entity work.reg4(behav) port map ( d0, d1, d2, d3, en, clk, q0, q1, q2, q3 ); stimulus : process is begin d0 <= 1 ; d1 <= 1 ; d2 <= 1 ; d3 <= 1 ; wait for 20 ns; en <= 0 ; clk <= 0 ; wait for 20 ns; en <= 1 ; wait for 20 ns; clk <= 1 ; wait for 20 ns; d0 <= 0 ; d1 <= 0 ; d2 <= 0 ; d3 <= 0 ; wait for 20 ns; en <= 0 ; wait for 20 ns; wait; end process stimulus; end architecture test_reg4; 16

9 Regression Testing Test that a refinement of a design is correct that lower-level structural model does the same as a behavioral model Test bench includes two instances of design under test behavioral and lower-level structural stimulates both with same inputs compares outputs for equality Need to take account of timing differences 17 Regression Test Example architecture regression of test_bench is signal d0, d1, d2, d3, en, clk : bit; signal q0a, q1a, q2a, q3a, q0b, q1b, q2b, q3b : bit; begin dut_a : entity work.reg4(struct) port map ( d0, d1, d2, d3, en, clk, q0a, q1a, q2a, q3a ); dut_b : entity work.reg4(behav) port map ( d0, d1, d2, d3, en, clk, q0b, q1b, q2b, q3b ); stimulus : process is begin d0 <= 1 ; d1 <= 1 ; d2 <= 1 ; d3 <= 1 ; wait for 20 ns; en <= 0 ; clk <= 0 ; wait for 20 ns; en <= 1 ; wait for 20 ns; clk <= 1 ; wait for 20 ns; wait; end process stimulus;... 18

10 Regression Test Example verify : process is begin wait for 10 ns; assert q0a = q0b and q1a = q1b and q2a = q2b and q3a = q3b report implementations have different outputs severity error; wait on d0, d1, d2, d3, en, clk; end process verify; end architecture regression; 19 20

11 Synthesis Register Transfer Level Synthesis: Translates register-transfer-level (RTL) design into gate-level netlist Restrictions on coding style for RTL model Tool dependent High Level Synthesis Translate behavioral code to RTL level Beyond the scope of this course Logic Level Synthesis Tranlate gate-level net list into implementation technology 21 Basic Design Methodology Requirements RTL Model Simulate Synthesize Gate-level Model Simulate Test Bench ASIC or FPGA Place & Route Timing Model 22 Simulate

12 Modeling Digital Systems: Definitions System is made up of components connected by signals Model interface to components (entity) and their behavior (architecture) A signal carries logical values logical values: 1 and 0 these are abstractions for real voltage values convenient for modeling digital systems Signals change value over time a change in value is an event A time ordered sequence of events on a signal produces a waveform 23 Example: Half Adder Inputs Outputs a b s c c = a. b s = a + b a c b Half adder s 24

13 Half Adder Timing a b s c time a b c s Event on b: XOR evaluates causes s to change value There is a propagation delay associated with a logic gate evaluating 25 Events and Signals Event: 0 1 transition 1 0 transition Signal values: 0, 1 When simulator starts, signals are undefined: U What happens if I have a short circuit? Driving both 0 and 1 on same wire: X (meaning for simulation, not for synthesis) High Impedance output: Z Don t Care: 26

14 Signal Types In VHDL all signals have types We use the type std_logic It is defined in a package: ieee.std_logic_1164.all It defines a std_logic signal to be able to have values: 0, 1, X, U, Z, and 3 others 27 Half Adder in VHDL Describe entity, architecture library ieee; use ieee.std_logic_1164.all; entity half_adder is port (a,b: in std_logic; sum, carry: out std_logic); end entity half_adder; half_adder is the name of the entity port ( ); is the port list 28

15 VHDL syntax VHDL syntax: coment ; ends a line VHDL is case INsensitive halfadder is the same as HALFADDER is the same as halfadder From the language templates in the Xilinx tool: entity ENTITY_NAME is port ( <port_declarations> ); end ENTITY_NAME; 29 VHDL ports port (a,b: in std_logic; sum, carry: out std_logic); A port is described as: A signal name A mode: in, out or inout (many synthesis tools do not allow inout) A type we are using std_logic library ieee; use ieee.std_logic_1164.all; ieee package defines the type std_logic and operators on std_logic (and, or,...) Packages are stored in a library 30

16 Half Adder Architecture So far we have only described the interface Architecture describes how the half adder behaves architecture blogic of half_adder is begin sum <= (a xor b) after 5 ns; carry <= (a and b) after 5 ns; end architecture blogic; Boolean logic operators: and, or, nand, nor, xor, xnor, not these are defined in package std_logic 31 Signal Assignment sum <= (a xor b) after 5 ns; <= is signal assignment signal assignment always has some delay associated with it sum <= (a xor b) after 5 ns; gets evaluated whenever a or b change sum gets updated 5 nseconds later (simulator) To understand this, need to know something about how the simulator works 32

17 Event: 0 1 transition 1 0 transition Events Over time, a sequence of events on a signal produce a waveform on that signal The effects of an event propagate through the circuit: events on inputs cause changes on internal signals and on output signals ouputs are inputs to other circuits... Digital circuits are modeled with: events, delays, concurrent operation, waveforms 33 VHDL Simulator Assumption: All gates have some delay between input changing and output changing minimum delay is δ Simulator models delays, events, concurrency Events change in value at a discrete point in time In other words, transitions are instantaneous There is no delay for the transition itself 34

18 VHDL s Simulation Model 1. Initialize all signals, set time to t =0 2. For all signals that have events at time t, activate processes, statements or gates triggered by those signals 3. Evaluate processes and schedule events on outputs to occur at future time (never NOW!) by putting events in time queue 4. If there are more events (or simulation time not over) Then update t to next event and go to step 2 Else simulation over Next event may be at t + δ, t + 5ns, t + 2 minutes VHDL Simulation This is discrete event simulation: Advance time to next event Only model events or changes in the circuit Alternative: advance time to next possible time and simulate. This is NOT used in VHDL. Two stages: propagate events and signals and evaluate their effects Schedule outputs to change some time in the future 36

19 Simulation Definitions Signals are values on wires that change over time Components (gates, flip-flops,...) take signals as inputs and generate signals as outputs A system is a set of components connected by wires An event occurs on a signal when it changes value An event has a time associated with it 37 Discrete Event Simulation Discrete Event Simulation (DES) has an event list data structure: Ordered list of future events Ordered by time stamp of event time stamp is time in future that event will occur Simulator clock keeps track of current time in system State of simulation: value of all signals at current time Initially all signals are uninitialized 38

20 39 40

21 How to use the simulator Describe circuit in VHDL Describe inputs to circuit for simulation purposes How are input events described? In simulator, manually set inputs look at outputs or write a testbench to set inputs monitor outputs User writes a testbench: Can be written in VHDL Includes Design Under Test (DUT) as a component Specifies input stimuli, may check outputs Usually no ports in a testbench Usually NOT synthesizable 41 Xilinx has a tool for creating a testbench The Xilinx suite has a tool that will automatically create a testbench for you: You create a waveform using a graphical display The Xilinx Tools automatically translate this into VHDL See ECEU323 lab 1 for using the testbench generator and for automatically launching Modelsim from the Xilinx tools: ECEU323 Lab 1 Section 5.1 You can do the same thing for a VHDL design! This is in the tutorial ECEU323 Lab 2 Section 4.1 explains how to print out the bitmap from your Modelsim waveform window 42

22 Testbench TESTBENCH MODEL Stimuli VHDL Part Model Results File Input File / Graphical Output 43 VHDL Features Designs may be decomposed hierarchically Each design element has both an interface and an architectural specification Architectural specifications can use an algorithm or a structure to define the element's operation, or a mix of the two Concurrency, timing, and clocking can be modelled The logical operation and timing behavior of a design can be simulated 44

23 Modeling Hardware With VHDL Package Generic Entity Ports Behavioral Functional Dataflow Structural Architecture Architecture Architecture Architecture 45 Modeling Hardware with VHDL (2) 46

24 47 48

25 An architecture may use other entities. A high-level architecture may use a lower-level entity multiple times Multiple top-level architectures may use the same lower-level entity This forms the basis for hierarchical system design Hierarchical Design VHDL Language Details In the text file of a VHDL program, the entity declaration and the architecture definition are separated The language is not case sensitive Comments begin with 2 hyphens (--) and finish at the end of the line. VHDL defines many reserved words(port, is, in, out, begin, end, entity, architecture, if, case,...).

26 Entity Declaration Syntax mode specifies the signal direction: in: input to the entity out: output of the entity inout: input and output of the entity signal-type is a built-in or user-defined signal type Architecture Definition Syntax The declarations can appear in any order In signal declarations, internal signals to the architecture are defined: signal signal-names : signal-type;

27 53 54

28 Signals, Variables, Constants A signal describes a waveform A signal is a series of time, event pairs Signals correspond to wires in a circuit A variable is a value Variables have no notion of time associated with them Variables do not directly model something in a circuit Variables are helpers for programming constructs A constant is a variable that cannot be changed Signals and variables can be initialized (Many synthesis tools do not allow signals to be initialized) Constants MUST be initialized, and can never be changed 55 VHDL Types All signals, variables, and constants MUST have an associated type A type specifies the set of valid values for the object and the operators that can be applied to it VHDL is a strongly typed language VHDL has several pre-defined types: integer includes the range through boolean has two values, true and false character includes the characters in the ISO 8-bit character set

29 VHDL Operators Built-in operators for integer and boolean types Enumerated Types Enumerated types are defined by listing the allowed values STD_ULOGIC is an enumerated type in VHDL

30 User Defined Types User-defined types are common in VHDL programs User defined types can be enumerated types or subtypes of an existing type type traffic_light_state is (reset, stop, start, go); subtype bitnum is integer range 31 downto 0; constant BUS_SIZE: integer := 32; VHDL Array Types Array types are also user-defined

31 VHDL Types types scalar types access types file types composite types discrete types floatingpoint types physical types array types record types integer types enumeration types real time unconstrained array types constrained array types integer severity_level bit_vector file_open_status string boolean file_open_kind bit character 61 Constants, Variables, Signals constants have type and value the value never changes variables have type, initial value (optional) updated without delay signals have type always delay before updating variable assignment: sequential statement := evaluates when you come across it in the code signal assignment: concurrent statement <= evaluates when signal on right hand side (RHS) changes I can mix variables and signals I cannot mix types! 62

32 Variables vs. Signals Variables have a current value, changes immediately used in behavioral style code auxilliary functions Signals are a sequence of (value, time) pairs used for wires in a circuit values on signals can be viewed as a waveform 63 Concurrent vs. Sequential Concurrent VHDL statements are active all the time whenever inputs change, outputs can be scheduled to change Sequential VHDL statements are evaluated when they are reached in the program Concurrent and sequential statements can be used to describe combinational hardware Concurrent and sequential statements can be used to describe sequential hardware Type of VHDL statement is about the code, not the circuit! 64

33 VHDL concurrent statements A signal assignment is a concurrent statement: Y <= ((not sel) and A) or (sel and B)); statement is evaluated whenever sel, A, or B change A process statement is a concurrent statement process( A, B, sel) is begin Y <= ((not sel) and A) or (sel and B)); end process; 65 Process statement process ( ) <declarations> sensitivity begin list <sequential statements> end process; If signal on sensitivity list changes, evaluate process A signal assignment statement is a one-line process all signals on the RHS of the signal assignment statement are automatically in the sensitivity list 66

34 Signal Assignment is a Process The signal assignment: Y <= ((not sel) and A) or (sel and B)); Is the SAME as the process statement: process( A, B, sel) is begin Y <= (A and (not sel)) or (B and sel); end process; NOTE: <= -- signal assignment := -- variable assignment = -- comparison if sel = 0 67 Sequential Statements Must be inside a process Why? so simulator knows when to evaluate them Sequential statements: variable assignment if... then... else 68

35 Libraries and Packages Libraries provide a set of hardware designs, components, and functions that simplify the task of designing Packages provide a collection of commonly used data types and subprograms used in a design The following is an example of the use of the IEEE library and its STD_LOGIC_1164 package: LIBRARY ieee; USE ieee.std_logic_1164.all; 69 Signals Signals represent wires and storage elements within a VHDL design Signals may only be defined inside architectures Signals are associated with a data type Signals may have attributes VHDL is a strongly typed language: Explicit type conversion is supported Implicit type conversion is not supported 70

36 Signal Representations Binary number representations are sufficient for software programming languages Forcing 1 Binary 1 Forcing 0 0 Physical wires cannot be modelled accurately using a binary number representation Additional values are necessary to accurately represent the state of a wire 71 IEEE Packages IEEE defined a 9 valued logic system IEEE developed two packages for this system STD_LOGIC_1164.VHD Defines the basic value system and associated functions Used as is by vendors NUMERIC_STD.VHD Provides overloaded arithmetic and other operators for synthesis Vendors have developed their own versions of this 72

37 STD_LOGIC_1164 Data Types STD_LOGIC_1164 is a standardized package that implements a set of data types Data Type STD_ULOGIC STD_ULOGIC_VECTOR STD_LOGIC STD_LOGIC_VECTOR Characteristics MVL 9, Unresolved MVL 9, Unresolved, Array MVL 9, Resolved MVL 9, Resolved, Array IEEE recommends the use of the STD_LOGIC and STD_LOGIC_VECTOR data types 73 STD_LOGIC_ Logic Values IEEE Standard type STD_ULOGIC is ( U,-- Uninitialized X,-- Forcing Unknown 0,-- Forcing 0 1, -- Forcing 1 Z,-- High Impedance W,-- Weak Unknown L,-- Weak 0 H,-- Weak 1 -,-- Don t care ); 74

38 Signal Strengths Needed to model bus contention Logic values have strength 0 strong zero; 1 strong one L weak zero; H weak one Models the effect of source impedance Suppose R is the resolution function, then strong dominates weak, i.e. 0 R H = H R 0 = 0 1 R L = L R 1 = 1 75 Unknown Values X: value is 0 or 1 W: value is L or H X and W are unknown values that arise from: Bus contention, i.e. resolving opposite values of the same strength yields unknowns of that strength 0 R 1 = 1 R 0 = X L R H = H R L = W error conditions, e.g, a flip flop has an unknown state Strength and weakness applied among values and unknowns also, e.g.: L R X = X, 1 R W = 1 76

39 Z and Z represents high impedance, i.e., the output of a tristate buffer that is turned off represents don t care synthesis: represents a logic don t care that can be used for logic minimization Can cause trouble in comparison statements simulation: sometimes acts like an X, is converted to an X when operated on 77 What happens if we connect the outputs of two logic gates to the same point? 78

40 Tristate Logic and Z The most common tristate device is the tristate buffer When E =0, Y = A, i.e. this is a noninverting buffer When E =1, the output is in the high-z state 79 Tristate logic Multiple tristate gates can have their outputs connected together, provided that at most one of them is enabled at any one time If you enable more than one of the gates, you are back to the same old problem of devices fighting one another It is therefore important to design the enable logic correctly 80

41 Resolution CONSTANT resolution_table : stdlogic_table := ( U X 0 1 Z W L H ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- U ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- X ( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- 0 ( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- 1 ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- Z ( 'U', 'X', '0', '1', 'W', 'W', 'W','W', 'X' ), -- W ( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- L ( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- H ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', X', 'X' ) -- - ); 81 STD_LOGIC Definition *** industry standard logic type *** SUBTYPE std_logic IS resolved std_ulogic; unconstrained array of std_logic for use -- in declaring signal arrays TYPE std_logic_vector IS ARRAY ( NATURAL RANGE <>) OF std_logic; 82

42 Resolution Function - Resolved FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic IS VARIABLE result: std_ulogic := 'Z'; -- weakest state default BEGIN -- the test for a single driver is essential -- otherwise the loop would return 'X' for a single -- driver of '-' and that would conflict with the -- value of a single driver unresolved signal IF (s'length = 1) THEN RETURN s(s'low); ELSE FOR i IN s'range LOOP result := resolution_table(result, s(i)); END LOOP; END IF; RETURN result; END resolved; 83